KR920004904B1 - Delay circuit - Google Patents

Abstract

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Description

Delay circuit

1 is a circuit diagram of a delay circuit according to an embodiment of the present invention.

2 is an internal circuit diagram of a CMOS current mirror type differential amplifier used as a voltage comparator provided in the delay circuit of FIG.

3 is a waveform diagram of a signal generated in a main part of the delay circuit of FIG.

4 is a waveform diagram of a signal generated in the main part of the delay circuit of FIG. 1 when noise is applied to the power supply voltage and the ground potential.

5 is a circuit configuration diagram in which the delay circuit of FIG. 1 is changed.

FIG. 6 is a waveform diagram of signals generated in major portions of the delay circuit of FIG.

* Explanation of symbols for main parts of the drawings

10: delay circuit 12: charge / discharge circuit

14: input terminal 16: the first signal line

18: voltage comparator 20: second signal line

22: reference voltage generator 24: switch circuit

Vcc: Power supply voltage Vss: Ground potential

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to delay circuits, and in particular, to delay circuits suitable for use in semiconductor integrated circuit (IC) devices, such as dynamic random access memory (DRAM).

In general, IC devices such as DRAMs have a delay circuit that properly sets the internal timing to provide proper synchronous operation between the internal circuit portions. A typical delay circuit includes a charge / discharge circuit to which an input signal? 1 is supplied, a reference voltage generator, and a voltage comparator for detecting a potential difference between two elements. As the level of the input signal? 1 changes, for example, from the "low" level to the "high" level, the capacitor transition of the charge / discharge circuit also changes.

When the node voltage coupled to the variable capacitor potential becomes equal to a constant reference voltage, the output voltage? 2 of the comparator is inverted. Therefore, the input signal? 1 is delayed by the interval (delay time?) Between the supply of the input signal and the inversion of the output voltage? 2 of the comparator. This delay time [tau] can be set to an appropriate value for each IC element since the circuit constants of the capacitor and the resistor can be arbitrarily set to a desired value by appropriately designing them.

However, the conventional delay circuit has a drawback that the delay time?, Which must be constant, is changed by noise generated by the change of the power supply voltage Vcc. Since the power supply line and the magazine potential line of the IC element to which the delay circuit is applied are shared by a plurality of internal circuit portions of the IC element, various noises are likely to occur in these lines. The generation of such noise causes either or both of the supply voltage Vcc and the ground potential Vs in these lines to change in the form of AC current. In DRAM, the charging / discharging of many bit lines is executed in a short range at the time of data call, and the potential change in the power line of the DRAM is noticeable. The potential change of the power supply line unstable the node voltage of the charge / discharge circuit of the delay circuit, thereby making the output voltage ø2 inversion time of the comparator unstable. Therefore, it is difficult to keep the delay time τ stable at the desired designed value.

An object of the present invention is to provide a delay circuit that can maintain a constant delay time of a semiconductor integrated circuit even if the power supply voltage of the circuit changes.

In order to achieve the above object, the present invention provides a specific delay circuit for an IC device having a charge / discharge circuit, a voltage divider, and a comparator. The charge / discharge circuit receives the input signal? 1 and selectively executes charging and discharging in response to the input signal? 1 to generate a variable output voltage. The voltage divider receives the power supply voltage of the IC element and divides the power supply voltage to provide a reference voltage having a predetermined constant potential. In the comparator, a charge / discharge circuit and a voltage divider are coupled to the first and second input terminals, respectively, and the output voltage of the charge / discharge circuit is compared with a reference voltage. The male position circuit electrically separates the second input of the comparator from the voltage divider by receiving the input signal ø1 and performing a switching operation in response to the input signal. The capacitor maintains a reference voltage at the second input of the comparator while the comparator is electrically disconnected from the voltage divider.

The objects and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments.

Referring to Fig. 1, reference numeral 10 denotes a delay circuit according to a preferred embodiment of the present invention. The delay circuit 10 is composed of DRAM (not shown) and includes two MOS type field effect transistors (hereinafter referred to as MOSFETs or simply FETs), that is, P-channel MOSFET Q1 and n-channel MOSFET Q2, resistors. And a charge / discharge circuit 12 composed of R1 and capacitor C1. The common gate node of FER (Q1, Q2) is coupled to the input terminal 14 to which the input signal? 1 is supplied. The first signal line 16 having the FETs Q1 and Q2 coupled to the drain node is provided with a capacitor C1 between the ground potential Vss. The potential on the first signal line 16 is represented by V1.

The voltage comparator 18 is coupled with the signal line 16 at the sign inversion input, the reference voltage generator 22 is coupled at the unsigned input, and the second signal line 20 is coupled. The reference voltage generator 22 is a voltage divider consisting of a series circuit of a resistor R2 and a resistor R3 provided between a power supply voltage Vcc and a ground potential Vss. The voltage divider performs a normal voltage division operation to separate the power supply Vcc applied to one resistor R2 according to the resistance ratio of R2 to R3 and serves as a reference voltage to be supplied to the unsigned inverting input of the comparator 18. The divided voltage is provided to the signal line 20. The comparator 18 is a CMOS current mirror type differential amplifier formed of five FETs T1 to T5 as shown in FIG. The gates of the FETs T1 and T2 operate as unsigned and inverted inputs of the comparator 18. The common node of the FETs T2 and T4 acts as the output of the comparator 18 from which the output voltage? 2 is calculated. The sources of the FETs T3 and T4 are coupled to the power supply voltage Vcc through the FET T5.

The delay circuit 10 of the present invention is characterized in that the switch circuit 24 is provided between the resistors R2 and R3 as shown in FIG. In particular, the switch circuit 24 comprises a series circuit consisting of two FETs Q3 and Q4, the former FET Q3 being provided between the resistor R2 and the signal line 20 and the latter FET Q4. ) Is installed between line 20 and resistor R3. When these FETs Q3 and Q4 are brought into a conductive state, each of the resistors R2 and R3 is electrically coupled to the signal line 20 so that the voltage divider 22 can apply the divided voltage to the line 20. Perform normal operation. When the FETs Q3 and Q4 are in a non-conductive state, the resistors R2 and R3 are separated from the line 20 so that the line 20 electrically follows. The gates of the FETs Q3 and Q4 are commonly coupled and the inverter 26 is coupled between the input terminal 14 of the delay circuit 10 and the common gate node N1. The voltage at node N1 is represented by V3.

As shown in FIG. 1, the additional capacitor C2 is provided between the line 20 and the ground potential Vss. The capacitance of the capacitor C2 is set such that the ratio of this capacitance to the parasitic capacitance of the signal line 20 is equal to the ratio of the capacitance of the capacitor C1 to the parasitic capacitance of the signal line 16.

With reference to FIGS. 3 and 4, the operation mode of the delay circuit 10 will be described. In the following description, the basic operation of the delay circuit 10 will first be described with reference to FIG. 3 and the signal delay operation of the delay circuit 10 will be described with reference to FIG. This is a case where a potential change occurs between the ground potential Vss and the power supply voltage Vcc of the DRAM to which the delay circuit is applied.

While the input signal? 1 is at the " low " level, the P-channel FET Q1 of the charge / discharge circuit 12 is in a conductive state and the n-channel FET Q2 is in a nonconductive state. Therefore, the power supply voltage Vcc flows to the capacitor C1 through the FET Q1. The corresponding charge is accumulated in the capacitor C1. At this time, the inverter 26 of the switch circuit 24 generates a high level output voltage and the FETs Q3 and Q4 become conductive in response to the output voltage, whereby a voltage divider consisting of resistors R2 and R3 Coupled with line 20, the potential on signal line 20 is set as the reference voltage generated by reference voltage generator 22. The potential V2 of the line 20 is defined as follows.

V2 = Vcc · R3 / (R2 + R3)... … … … … … … … (One)

The output of the comparator 18 has a low level because the output voltage of the charge / discharge circuit 12, that is, the potential V1 of the line 16 is greater than the reference voltage or the transition V2 of the line 20.

As shown in FIG. 3, when the input signal? 1 changes from low level to high level at time t1, the P-channel FET Q1 of the charge / discharge circuit 12 is in a non-conductive state and the n-channel FET ( Q2) becomes a conductive state. Thus, the charge accumulated in the capacitor C1 is discharged through the FET Q2 and the resistor R1. Thus, as shown in FIG. 3, the potential V1 of the signal line 16 (that is, the output voltage of the charge / discharge circuit 12) gradually decreases.

The "on" resistance of the FET Q2 is smaller than the resistor R1 and the output voltage V1 of the charge / discharge circuit 12 is described as follows.

V1 (t) ^{-Vcce-t / c1.R1} ... … … … … … … … … (2)

When the gradually decreasing voltage V1 becomes equal to the reference voltage V2 at time t2, the output voltage of the comparator 18 changes from the "low" level to the "high" level as shown in FIG. The interval or delay time? Between time t1 and t2 is defined by the following equation.

τ = C 1 R 1 lig (1 + R 2 / R 3). … … … … … … … … (3)

The level change of the output voltage? 2 is delayed by the time? From the time point at which the potential level of the input signal? 1 changes. The delay time τ can be freely set by changing the CR time constant of the charge / discharge circuit 12. In other words, the input signal? 1 is delayed by the time? To become the output voltage? 2 of the delay circuit 10.

When the input signal? 1 is in the high level state, the output voltage V3 of the inverter 26 becomes low level, and the FETs Q3 and Q4 of the switching circuit 24 are brought into the non-conductive state at the same time. Thus, the voltage divider resistors R2 and R3 of the voltage divider 22 are electrically separated from each other. At the same time, the line 20 coupled with the unsigned inverting input of the comparator 18 is electrically insulated from the resistors R2 and R3 and electrically floated while the line 20 maintains the reference voltage V2. . Since the reference voltage V2 is kept constant by the capacitor C2, the potential of the line 20 is set to the reference voltage V2.

Even if a change occurs in the power supply voltage Vcc, the ground potential Vss, or both by such a configuration, the potential of the line 20 is independent of the potential change, so that a stable reference voltage V2 is fixed to the comparator 28. Can be supplied.

Therefore, it is possible to prevent the delay time? From becoming unstable due to the change in the power supply voltage Vcc. This improves the reliability of the delay time [tau]. In addition, the delay circuit of the present invention is designed so that these resistors are insulated from each other when the line 20 is separated from the voltage distribution resistors R2 and R3. Therefore, the current flow through the voltage divider 22 can be completely blocked, so that the series circuit of the resistors R2 and R3 is not influenced by the change of the power supply voltage Vcc at all, and the power consumption of the voltage divider can be reduced. To be able.

The operation of the delay circuit 10 of the present invention in the case where the following power supply voltage Vcc and ground potential Vss changes is described in detail. As shown in FIG. 4, the power supply voltage Vcc is undesirably increased as indicated by reference numeral 30 before the input signal ø1 is changed from the "low" level to the "high" level at time t1. Consider the case where the potential level is changed to Vcc1. In this case, the changed power supply voltage Vcc1 is applied to the capacitor C1 of the charge / discharge circuit 12 and the potential of the capacitor C1 gradually starts from this voltage Vcc1 when the discharge starts at time t1. Decreases. Once discharge is initiated, the FET Q1 is brought into a nonconductive state as described above to insulate the capacitor C1 from the power supply voltage Vcc, whereby the capacitor C1 is no longer affected by the voltage noise. Do not. Due to the distribution of the power supply voltage Vcc changed before time t1, the reference voltage V2 on the line 20 is also undesirably increased when the line 20 is electrically floating at time t1. The reference voltage V2 'in this case is defined as follows.

V2 '= Vcc1R3 / (R2 + R3)... … … … … … … … … (4)

After time t1, voltage divider resistors R2 and R3 are insulated from each other and separated from voltage divider 22 and line 20 is insulated from these resistors R2 and R3. Therefore, the line 20 is not affected by the change in the low source voltage. Therefore, whether or not a change occurs in the power supply voltage Vcc, the interval between the potential change time t1 of the input signal ø1 and the potential change time t2 of the output voltage ø2, that is, the delay time τ is always constant. .

Next, consider a case where the noise 32 occurs at the ground potential Vss after the time t1. In this case, since capacitors C1 and C2 are set to satisfy the above relationship, the capacitors C1 and C2 are generated at the lines 16 and 20 by the capacitor coupling generated by applying the ground potential noise 32 to the lines 16 and 20. The potential changes become equal to each other. Thus, it is possible to provide a delay circuit 10 that is insensitive to short range potential changes in power supply voltage Vcc and / or ground potential Vss. This delay circuit 10 is particularly suitable for IC devices such as DRAN.

5 illustrates another embodiment of the present invention, wherein an AND gate 40 is provided between the common gate node N1 of the FETs Q3 and Q4 of the switch circuit 24 and the inverter 26. It is. The AND gate 40 receives a control signal? 0 at its first input and an input signal? 1 at its second input. As shown in Fig. 6, the control signal? 0 changes from the "low" level to the "high" level before the level of the input signal changes from the "low" level to the "high" level. The time difference between the level change of the control signal? 0 and the input signal? 1 is represented by Tα. The output voltage signal of inverter 26 can thus be supplied via AND gate 40 to the common gate node of FETs Q3 and Q4 only by time Tα. Therefore, the high gate voltage is provided to the common gate node N1 only for the time Tα and the FETs Q3 and Q4 are in the non-conductive state only for the same time Tα. The time Tα is equal to the setting of the voltage V2 distributed on the line 20 by applying the power supply voltage Vcc to the signal line 20 through the voltage divider 22 and charging the capacitor C2. As such, it is set to have the minimum required time interval.

By this arrangement, the voltage divider 22 is operated only for a short time Tα before the input signal ø1 changes from the "low" level to the "high" level, and immediately deactivates when the time Tα elapses. It becomes the operating state. Therefore, leakage current or passage current can be minimized, and resistance values of voltage distribution resistors R2 and R3 can be minimized.

Accordingly, the signal line 20 may be maintained at the distribution voltage V2 by the reduced impedance until the charging / discharging of the signal line 16 is actually started.

While specific embodiments of the invention have been described thus far, many modifications are possible without departing from the spirit and scope of the invention.

For example, the capacitors C1 and C2 coupled to the first and second signal lines 16 and 20, respectively, are connected to a low power supply voltage, that is, a ground potential Vss, but they are connected to a high power supply voltage, that is, a power supply voltage Vcc. It can also be designed to connect to. In addition, although the CR delay circuit configuration using the linear resistor R and the linear capacitor C has been described so far, a MOSFET may be used instead of the R1 of the charge / discharge circuit 12. The delay circuit thus constructed has a corresponding power supply voltage dependency and temperature dependency.

Claims (28)

A delay circuit for a semiconductor integrated circuit device comprising: (a) first circuit means (12) for generating a variable output voltage by receiving an input signal and selectively executing charge / discharge in response to the input signal; (b) second circuit means (22) for generating a voltage having a predetermined constant potential as a reference voltage by receiving a power supply voltage of said element and dividing this power supply voltage; (c) third circuit means (18) having first and second inputs coupled to the first and second circuit means, respectively, for comparing the output voltage of the first circuit means with the reference voltage; (d) fourth circuit means (24) for electrically separating the second input of the third circuit means from the second circuit means by receiving the input signal and performing a switching operation in response to the input signal; (e) a semiconductor circuit comprising: a fifth circuit means (C2) for holding said reference voltage at said second input of said third means while said third circuit means is separated from said second circuit means; Delay circuit for integrated circuit devices. 2. The delay circuit according to claim 1, wherein the second recovery stage comprises a series circuit composed of first and second resistors to divide the power supply voltage at a predetermined division ratio. 3. The delay circuit as set forth in claim 2, wherein said fourth circuit means includes transistor means provided between said first and second resistors and changing its electrical state in response to said input signal. 4. The delay circuit of claim 3, wherein said transistor means electrically isolates said first and second resistors from said third circuit means when in a nonconductive state. 5. The delay circuit according to claim 4, wherein the transistor means comprises a series circuit of two transistors in which gate electrodes are coupled to each other. 6. The circuit of claim 5, wherein the fourth circuit means further comprises an inverter coupled to a commonly coupled gate electrode of the two transistors, whereby the input signal is commonly coupled gate of the two transistors through the inverter. A delay circuit, characterized in that supplied to the electrode. 7. The delay circuit as claimed in claim 6, wherein said fifth circuit means comprises a capacitor coupled to a second input of said third circuit means. (a) charge / discharge circuit means (12) for receiving an input signal and generating an output voltage in response to the input signal; (b) voltage divider means (22) having first and second resistors which divide the power supply voltage and are coupled in series to each other to receive the power supply voltage and provide a reference voltage having a constant potential level; (c) a sign inverting input coupled to said charge / discharge circuit means via a first signal line and an unsigned inverted input coupled to said voltage divider means via a second signal line, wherein said Comparator means (18) for comparing an output voltage with said reference voltage; (d) mounted between the first and second resistors of the voltage divider means to receive the input signal, to electrically separate the first and second resistors from each other and to separate the second signal lines from the first and second resistors; Switch circuit means (24) for selectively entering a nonconductive state in response to said input signal to separate from a second resistor, thereby bringing said second signal line into an electrically floating state; (e) is coupled to the second signal line to receive the reference voltage for charging when the switch circuit means is in the conducting state, and to apply the reference voltage on the second signal line when the switch means is in the nonconductive state. And a voltage holding means (C2) for holding. 9. The apparatus of claim 8, wherein the switch circuit means comprises a first transistor provided between the first resistor and the second signal line and a second transistor provided between the second signal line and the second resistor. And the first and second transistors are simultaneously brought into a nonconductive state. 10. The control means (40) according to claim 9, further comprising: (f) a control means (40) coupled to said switch circuit means to cause said switch circuit means to be in a conductive state only during a predetermined time interval before a change in level of said input signal occurs. Delay circuit further comprising. 11. The apparatus of claim 10, wherein the charge / discharge circuit means is coupled to the first signal line and selectively coupled to the first capacitor to selectively receive the power supply voltage to perform a charging operation. And a third resistor, wherein the first capacitor is discharged through the third resistor. 12. The delay circuit according to claim 11, wherein said voltage holding means comprises a second capacitor coupled to said second signal line. 13. The method of claim 12, wherein the second capacitor has a capacitance such that the ratio of the capacitance of the first capacitor to the parasitic capacitance of the first signal line is equal to the ratio of the capacitance of the second capacitor to the parasitic capacitance of the second signal line. Delay circuit characterized in that it has. The transistor of claim 13, wherein the first and second transistors further include an inverter having their gate electrodes coupled to each other and coupled to the gate electrode, wherein the input signal is connected to the first and second transistors through the inverter. And a delay circuit supplied to the gate electrode. 15. The delay circuit as set forth in claim 14, wherein said control means comprises an AND gate circuit provided between said inverter and said gate electrodes of said first and second transistors. 16. The delay circuit of claim 15, wherein the comparator means comprises a CMOS current mirror differential amplifier. A delay circuit for a semiconductor integrated circuit device, comprising: charge / discharge means (12) for receiving an input signal and generating a variable output signal in response to the input signal; Voltage divider means (22) for receiving a first voltage and generating a reference voltage having a constant potential level; Comparator means (18) having a first input (-) connected to said charge / discharge means and a second input (+) connected to said voltage divider means and for comparing the output voltage with said reference voltage to said charge / discharge means; Switch means (24) for electrically separating said second input of said comparing means from said voltage divider means in response to said input signal; And a second capacitor means (C2) connected to a second voltage and said second input of said comparator means, said charge / discharge means being connected to said first capacitor means (C1) connected to said second voltage and said first input. Delay circuit comprising a. 18. The delay circuit of claim 17, wherein one of the first and second voltages is a voltage power supply of a semiconductor integrated circuit device. 19. The apparatus of claim 18, further comprising: first conductor means (16) for supplying the output voltage of said charge / discharge means to said first input (-) of said comparator means, and said reference voltage for said second input of said comparator means ( A second conductor means 20 for supplying +), wherein said first capacitor means is connected to said first semiconductor means and said second capacitor means is connected to said second conductor means. Delay circuit. 20. The delay circuit of claim 19, wherein said switch means comprises a transistor coupled to said second conductor means. 20. The delay circuit of claim 19, wherein said switch means comprises transistors coupled to said second conductor means. 20. The delay circuit according to claim 19, wherein said switch means comprises a series circuit of transistors in which gate electrodes are connected to each other. 23. The natural circuit of claim 22, wherein the switch means further comprises an inverter having an input for receiving the input signal and an output coupled to the gate electrodes of the transistors. 20. The delay circuit of claim 19, wherein the first input of the comparator means is a sign inversion input and the second input of the comparator means is an unsigned inversion input. A charge / discharge circuit 12 connected between the first power supply voltage and the second power supply voltage and including a first capacitor; A reference voltage generator circuit 22 connected between the first and second voltages to generate a constant voltage; A comparator (18) having a sign inverting input connected to said charge / discharge circuit and an unsigned inverting input connected to said reference voltage generating circuit; Switch means (24) for selectively separating said comparator from said reference voltage generating circuit; And a second capacitor (C2) coupled to said unsigned inverting input of said comparator, wherein said first and second capacitors are coupled to one of said first and second voltages. 26. The delay circuit according to claim 25, wherein the reference voltage generating circuit includes a voltage divider circuit having a resistance. 27. The delay circuit of claim 26, wherein the switch means comprises transistors to electrically separate the resistors from each other and to electrically disconnect the unsigned inverting input of the comparator from the resistors of the voltage divider circuit. 28. The delay circuit of claim 27, wherein the charge / discharge circuit includes a resistor connected in parallel with the first capacitor.

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