GB2038085A - Random access memory cell with polysilicon bit line - Google Patents
Random access memory cell with polysilicon bit line Download PDFInfo
- Publication number
- GB2038085A GB2038085A GB7849115A GB7849115A GB2038085A GB 2038085 A GB2038085 A GB 2038085A GB 7849115 A GB7849115 A GB 7849115A GB 7849115 A GB7849115 A GB 7849115A GB 2038085 A GB2038085 A GB 2038085A
- Authority
- GB
- United Kingdom
- Prior art keywords
- bit line
- transfer device
- storage cell
- random access
- access memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 32
- 229920005591 polysilicon Polymers 0.000 title claims description 23
- 210000000352 storage cell Anatomy 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 238000013500 data storage Methods 0.000 claims abstract description 7
- 239000003990 capacitor Substances 0.000 claims abstract description 6
- 210000004027 cell Anatomy 0.000 claims description 25
- 238000004519 manufacturing process Methods 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 230000015654 memory Effects 0.000 abstract description 2
- 238000002179 total cell area Methods 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 3
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
- G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A data storage cell for use in dynamic random access semiconductor memories, comprises a MIS capacitor 1,2 and a MOSFET 2-5 whose source 5 is connected to a bit line 8 formed of a layer of polycrystalline silicon. A greater fraction of the total cell area is thus made available for data storage and the bit line to substrate capacitance is reduced in comparison to conventional data storage cells. <IMAGE>
Description
SPECIFICATION
Random access memory cell with polysilicon bit line
This invention relates to data storage cells of
metal oxide semiconductor (MOS) type, and in particular to dynamic random access semiconductor memories (RAM) constructed from arrays of such transistor cells.
One-transistor cells are cells which store data in the form of charge in a MOS capacitor and which write or read this data via a single transistor known as a transfer device.
The transfer device in a conventional RAM cell acts as an on-off gate between a transfer device drain and a transfer device source. The transfer device drain of the RAM cell is the data storage region and the transfer device source, called a bit line, comprises of a diffused region in the substrate. The bit line, which is a common source for the transfer devices of many data storage cells, extends across an array of cells and has a sense amplifier at one end. Only one transfer device of a cell on the bit line is turned on at any one time. The stored charge representing data is then transferred from the storage region of this cell onto the bit line. The bit line experiences a change in potential which is detected by the sense amplifier. To store new data in the storage region of this cell the bit line is taken to the appropriate potential before turning off the transfer device.
A conventional RAM cell is illustrated in
Figs. 1 (a) and 1(b). Fig. 1 (a) is a plan view of part of a RAM array showing a conventional
RAM cell. Fig. 1 (b) shows a section through the array on line 'A-A'. A single cell in this array will be described. A first polysilicon layer 1 forms a capacitor plate for a substrate region where data is stored as charge. The stored charge is held in an inversion layer formed in the substrate region 2 underneath the first polysilicon layer 1. A second layer of polysilicon 3 forms the gate of the transfer device and the charge is transferred via a transfer device channel 4. A bit line 5 is formed by a region of diffusion. Layers of oxide used to isolate the polysilicon layers are ommitted for clarity from the sectional views.
Regions of oxide 6 isolate the charge stored in the substrate region 2 from a bit line 7 of a neighbouring cell.
According to the present invention there is provided a one transistor storage cell for a random access memory array which comprises a data charge storage region, a transfer device and a bit line wherein the bit line is formed in polysilicon.
Embodiments of the invention will now be described with reference to Figs. 2 and 3 of accompanying drawings in which:~
Figure 2(a) is a plan view of part of RAM array showing a RAM cell.
Figure 2(b) is a sectional view of this cell along the line BB.
Figure 3(a) is an alternative form of a RAM array and
Figure 3(b) is a sectional view of a RAM cell in this array along the line CC.
Referring to Figs. 2(a) and 2(b) the first polysilicon layer 1 and the second polysilicon layer 3 have different shapes to those in the conventional RAM cell. The storage region 2 and the transfer device channel 4 are similar to those of the conventional RAM cell of Fig.
1. However, the source of the transfer device is connected to a region of diffusion 5 which is shared with only one other cell and whose area is minimised in comparison with the large area of common diffused bit line in the conventional array of RAM cells. The many small areas of diffusion 5 are connected to-~ gether electrically with a stripe 8 of the same polysilicon as that used for the transfer device gate which makes contact with each diffusion area 5 by means of a buried contact opening 9. A common bit line is thus formed.
In this array the first polysilicon layer 1 consists of an electrically continuous sheet with slots opened where the transfer devices and buried contacts are located. A region of oxide 6 isolates the charge stored in the substrate region 2 the charge storage region of an adjacent cell 2A. The bit line, formed by the same polysilicon as used for the transfer device gate, passes over the top of polysilicon 1 where it covers oxide 6.
There are several different ways by which the array may be made. The buried contact may be defined by etching a window in the transfer device gate dielectric, which is an oxide or a nitride and an oxide, before the bit line polysilicon is deposited. Alternatively the buried contact area may be defined with a protective nitride plug deposited before the transfer device gate oxide is grown as described in our co-pending application No.
J.M.Young-J.P.Perry-R.Wakefield 6-1-1.
This nitride plug is removed before the bit line polysilicon is deposited. In either case an extra masking step is necessary to define the buried contact. Figs. 3(a) and 3(b) show a completely separate third layer of polysilicon 11 which may be used for the bit line. The bit line 7 of neighbouring cells is also of this third polysilicon. This permits a more compact layout or larger storage area as no spacing between the bit line and transfer device gate is required. A separate mask to define the buried contact is not needed. However, a mask is required to define the third polysilicon layer.
In order to clarify all the figures aluminium word lines connected the transfer device gates and their contact openings are not shown. Ion implantation masks which may also be part of the array are also not shown. Layers of oxide used to isolate between polysilicon layers are omitted from the sectional views.
Claims (14)
1. A one transistor storage cell for a random access memory array which comprises a data charge storage region, a transfer device and a bit line wherein the bit line is formed in polysilicon.
2. A one transistor storage cell for a random access memory array, comprising a first polycrystalline silicon layer forming a capacitor plate for a substrate region where the data is stored as charge, and a second polycrystalline silicon layer forming a gate of a transfer device wherein the stored charge is transferred via a transfer device channel to a bit line and wherein the bit line is formed from polycrystalline silicon.
3. A one transistor storage cell as claimed in claim 1 or 2 wherein the same polysilicon is used for the transfer device gate and for the bit line.
4. A one transistor storage cell as claimed in claim 1 or 2 wherein a different polysilicon is used for the bit line than that used for the transfer device gate.
5. A one transistor storage cell as claimed in any one of the claims above, wherein a bit line of a neighbouring cell overlaps the data storage capacitor polysilicon of the storage cell.
6. A one transistor storage cell as claimed in any one of the preceding claims wherein the bit line is connected by means of a buried contact opening to a diffused region which is a source of the transfer device.
7. A one transistor storage cell substantially as described with reference to Fig. 2 or 3 of the accompanying drawings.
8. A random access memory array constructed of cells as claimed in any one of the claims 1 to 5.
9. A method of making a one transistor storage cell substantially as described herein with reference to Figs. 2 and 3 of the accompanying drawings.
CLAIMS (26 Jul 1979)
10. A random access memory array which includes a number of storage cells, wherein each said storage cell is a one transistor storage cell including a first polycrystalline silicon layer forming a capacitor plate for a substrate region where the data is stored as charge, and a second polycrystalline silicon layer forming a gate of a transfer device wherein the stored charge is transferred via a transfer device channel to a bit line, and wherein the or each said bit line is formed from a strip of polycrystalline silicon which is associated with a plurality of storage cells.
11. A random access memory array as claimed in claim 10 wherein the same polycrystalline silicon is used for the transfer device gate of each said storage cell and for the or each said bit line.
12. A random access memory array as claimed in claim 10 wherein a different polycrystalline silicon is used for the or each said bit line than that used for the transfer device gate of each said storage cell.
13. A random access memory array as claimed in any one of claims 10 to 12 wherein the or each said bit line is connected by means of a buried contact opening to a diffused region which is a source of the transfer device.
14. A random access memory array which includes a number of storage cells, wherein each said storage cell is a one transistor storage cell substantially as described with reference to Fig. 2 or 3 of the accompanying drawings.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB7849115A GB2038085B (en) | 1978-12-19 | 1978-12-19 | Random access memory cell with polysilicon bit line |
| DE19792949689 DE2949689A1 (en) | 1978-12-19 | 1979-12-11 | INTRANSISTOR MEMORY CELL FOR A DYNAMIC SEMICONDUCTOR MEMORY WITH OPTIONAL ACCESS |
| JP16418679A JPS5583259A (en) | 1978-12-19 | 1979-12-19 | Random access memory cell with polycrystalline bit wire |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB7849115A GB2038085B (en) | 1978-12-19 | 1978-12-19 | Random access memory cell with polysilicon bit line |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB2038085A true GB2038085A (en) | 1980-07-16 |
| GB2038085B GB2038085B (en) | 1983-05-25 |
Family
ID=10501815
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB7849115A Expired GB2038085B (en) | 1978-12-19 | 1978-12-19 | Random access memory cell with polysilicon bit line |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JPS5583259A (en) |
| DE (1) | DE2949689A1 (en) |
| GB (1) | GB2038085B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4922312A (en) * | 1986-04-30 | 1990-05-01 | Texas Instruments Incorporated | DRAM process with improved polysilicon-to-polysilicon capacitor and the capacitor |
| US5098192A (en) * | 1986-04-30 | 1992-03-24 | Texas Instruments Incorporated | DRAM with improved poly-to-poly capacitor |
| US5244825A (en) * | 1983-02-23 | 1993-09-14 | Texas Instruments Incorporated | DRAM process with improved poly-to-poly capacitor |
| US5359216A (en) * | 1983-02-23 | 1994-10-25 | Texas Instruments Incorporated | DRAM process with improved polysilicon-to-polysilicon capacitor and the capacitor |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4364075A (en) * | 1980-09-02 | 1982-12-14 | Intel Corporation | CMOS Dynamic RAM cell and method of fabrication |
| JPH02146767A (en) * | 1989-07-19 | 1990-06-05 | Mitsubishi Electric Corp | Semiconductor memory device |
-
1978
- 1978-12-19 GB GB7849115A patent/GB2038085B/en not_active Expired
-
1979
- 1979-12-11 DE DE19792949689 patent/DE2949689A1/en not_active Withdrawn
- 1979-12-19 JP JP16418679A patent/JPS5583259A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5244825A (en) * | 1983-02-23 | 1993-09-14 | Texas Instruments Incorporated | DRAM process with improved poly-to-poly capacitor |
| US5359216A (en) * | 1983-02-23 | 1994-10-25 | Texas Instruments Incorporated | DRAM process with improved polysilicon-to-polysilicon capacitor and the capacitor |
| US4922312A (en) * | 1986-04-30 | 1990-05-01 | Texas Instruments Incorporated | DRAM process with improved polysilicon-to-polysilicon capacitor and the capacitor |
| US5098192A (en) * | 1986-04-30 | 1992-03-24 | Texas Instruments Incorporated | DRAM with improved poly-to-poly capacitor |
Also Published As
| Publication number | Publication date |
|---|---|
| DE2949689A1 (en) | 1980-07-03 |
| GB2038085B (en) | 1983-05-25 |
| JPS5583259A (en) | 1980-06-23 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |