GB1491692A - Allocation of storage and generation of routines in data processing system - Google Patents
Allocation of storage and generation of routines in data processing systemInfo
- Publication number
- GB1491692A GB1491692A GB48398/74A GB4839874A GB1491692A GB 1491692 A GB1491692 A GB 1491692A GB 48398/74 A GB48398/74 A GB 48398/74A GB 4839874 A GB4839874 A GB 4839874A GB 1491692 A GB1491692 A GB 1491692A
- Authority
- GB
- United Kingdom
- Prior art keywords
- entry
- pointer
- address
- link
- entries
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/22—Microcontrol or microprogram arrangements
- G06F9/26—Address formation of the next micro-instruction ; Microprogram storage or retrieval arrangements
- G06F9/261—Microinstruction address formation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/448—Execution paradigms, e.g. implementations of programming paradigms
- G06F9/4482—Procedural
- G06F9/4484—Executing subprograms
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Memory System (AREA)
- Computer And Data Communications (AREA)
- Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
- Executing Machine-Instructions (AREA)
Abstract
1491692 Data processing HONEYWELL INFORMATION SYSTEMS Inc 8 Nov 1974 [8 Nov 1973] 48398/74 Heading G4A A data processing system comprises a main memory 108 (Fig. 1) containing routines, each consisting of a sequence of commands to be carried out in response to an instruction received on line 100 and a search table 106 containing, for each routine, an entry identifying the routine and including an address in main memory. If no entry is found for an instruction, the routine with the lowest activity is replaced by the requested routine. The six most significant bits of the instruction are fed by mask 102 to a start table point 104 which has 64 locations each with an address for entry in the table 106 (which has more than 64 locations). The entries are queued so that most recently used and least recently used entries are at opposite ends. Each entry in table 106 includes 5 parameters, (1) a search argument 110; (2) a P-pointer 111; (3) a link pointer 112; (4) H-pointer 113, and (5) a T-pointer 114. The search argument is used to indicate if there is a "hit" between an instruction received and the addressed entry. If there is the P-pointer is used to address the program memory 108. The link pointer indicates the next entry in a linked family of entries, the last member of the family having a zero link pointer. The H- and T- pointers indicate respectively the next more recently and the next less recently used entries. Head and tail pointers 118, 116 indicate the most recently used and least recently used entries in the table. If there is no hit and if the link pointer of the access entry is not zero the entry indicated by the link pointer is accessed to see if there is a hit, in which case its address is put in the table 104 of the initial address link family. This process is continued if there is no hit until the link pointer is zero when an entry is inserted in table 106 of the address indicated by the tail pointer unless the associated program is still active, the head pointer then being up-dated to indicate this entry.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US41406373A | 1973-11-08 | 1973-11-08 |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1491692A true GB1491692A (en) | 1977-11-09 |
Family
ID=23639803
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB48398/74A Expired GB1491692A (en) | 1973-11-08 | 1974-11-08 | Allocation of storage and generation of routines in data processing system |
Country Status (11)
Country | Link |
---|---|
JP (1) | JPS5840273B2 (en) |
BE (1) | BE821998A (en) |
CA (1) | CA1027248A (en) |
CH (1) | CH595662A5 (en) |
DE (1) | DE2451984C2 (en) |
ES (1) | ES430692A1 (en) |
FR (1) | FR2251053B1 (en) |
GB (1) | GB1491692A (en) |
IT (1) | IT1023160B (en) |
NL (1) | NL7413691A (en) |
SE (1) | SE402990B (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5696337A (en) * | 1979-12-28 | 1981-08-04 | Fujitsu Ltd | Resource control system |
US20140281398A1 (en) * | 2013-03-16 | 2014-09-18 | William C. Rash | Instruction emulation processors, methods, and systems |
-
1974
- 1974-07-24 CA CA205,529A patent/CA1027248A/en not_active Expired
- 1974-09-03 JP JP49101264A patent/JPS5840273B2/en not_active Expired
- 1974-10-04 ES ES430692A patent/ES430692A1/en not_active Expired
- 1974-10-18 NL NL7413691A patent/NL7413691A/en not_active Application Discontinuation
- 1974-11-02 DE DE2451984A patent/DE2451984C2/en not_active Expired
- 1974-11-04 SE SE7413818A patent/SE402990B/en unknown
- 1974-11-05 FR FR7436732A patent/FR2251053B1/fr not_active Expired
- 1974-11-05 IT IT53870/74A patent/IT1023160B/en active
- 1974-11-08 GB GB48398/74A patent/GB1491692A/en not_active Expired
- 1974-11-08 CH CH1493974A patent/CH595662A5/xx not_active IP Right Cessation
- 1974-11-08 BE BE150335A patent/BE821998A/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
FR2251053A1 (en) | 1975-06-06 |
DE2451984A1 (en) | 1975-05-15 |
JPS5840273B2 (en) | 1983-09-05 |
IT1023160B (en) | 1978-05-10 |
SE402990B (en) | 1978-07-24 |
ES430692A1 (en) | 1977-05-01 |
DE2451984C2 (en) | 1984-07-26 |
AU7493574A (en) | 1976-05-06 |
CH595662A5 (en) | 1978-02-15 |
BE821998A (en) | 1975-05-09 |
JPS5081034A (en) | 1975-07-01 |
CA1027248A (en) | 1978-02-28 |
SE7413818L (en) | 1975-05-09 |
NL7413691A (en) | 1975-05-12 |
FR2251053B1 (en) | 1978-11-24 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4648035A (en) | Address conversion unit for multiprocessor system | |
US3984817A (en) | Data processing system having improved program allocation and search technique | |
GB1481609A (en) | Apparatus arranged to process a plurality of discrete computing tasks | |
GB1353311A (en) | Memory system | |
GB1492067A (en) | Computer with segmented memory | |
GB1342459A (en) | Data processing systems | |
JPS6436336A (en) | Calculator system | |
GB1129988A (en) | Digital computers | |
GB1233117A (en) | ||
EP0024288A3 (en) | Computer system having at least two processors with shared storage | |
AU542183B2 (en) | Multi-programming data processing system | |
GB1504756A (en) | Peripheral device addressing in data processing system | |
GB1491692A (en) | Allocation of storage and generation of routines in data processing system | |
GB1424105A (en) | Programmed digital data processing system | |
GB1443971A (en) | Computer system with programme-controlled programme counters | |
JPS54148346A (en) | Memory access system for multi-processor system | |
GB1495729A (en) | Apparatus and method for handling exceptions in a data processing system | |
GB1434188A (en) | Data processing systems | |
GB1314486A (en) | Microprogramme control system | |
GB1484459A (en) | Data processing system including semaphores | |
JPS56108154A (en) | Microprogram debug system | |
JPS5733472A (en) | Memory access control system | |
JPS5786181A (en) | Second buffer storage device | |
JPS55157038A (en) | Microprogram control system | |
JPS57150050A (en) | Main storage controller |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PS | Patent sealed [section 19, patents act 1949] | ||
PCNP | Patent ceased through non-payment of renewal fee |