GB1322182A - Testing of apparatus - Google Patents
Testing of apparatusInfo
- Publication number
- GB1322182A GB1322182A GB1322182DA GB1322182A GB 1322182 A GB1322182 A GB 1322182A GB 1322182D A GB1322182D A GB 1322182DA GB 1322182 A GB1322182 A GB 1322182A
- Authority
- GB
- United Kingdom
- Prior art keywords
- circuit
- module
- testing
- division
- pulses
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/32—Monitoring with visual or acoustical indication of the functioning of the machine
- G06F11/321—Display for diagnostics, e.g. diagnostic result display, self-test user interface
- G06F11/322—Display of waveforms, e.g. of logic analysers
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/3193—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault free response
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Human Computer Interaction (AREA)
- Quality & Reliability (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
1322182 Testing circuit modules PLESSEY CO Ltd 18 Aug 1970 43032/69 Heading G1U [Also in Division H3] In a method of testing a circuit module consisting of a plurality of indentical circuit units, e.g. three NOR gates, Fig. 2a, pulses Fig. 2b are applied sequentially to the input terminals 11, 12, ... , 33 of the module and the resulting signals at the output terminals 4, 5, 6 are mixed and displayed on an oscilloscope 9. Differences in the performances of the circuit units constituting the module can then easily be detected. A circuit producing distributed pulses a, b ..., i, Fig. 2b, in response to a linearly rising ramp voltage (100) is described Fig. 8, (not shown), see Division H3. For figures see next page
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB4303269 | 1969-08-29 |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1322182A true GB1322182A (en) | 1973-07-04 |
Family
ID=10427034
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB1322182D Expired GB1322182A (en) | 1969-08-29 | 1969-08-29 | Testing of apparatus |
Country Status (1)
Country | Link |
---|---|
GB (1) | GB1322182A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2167196A (en) * | 1984-11-09 | 1986-05-21 | Membrain Ltd | Device orientation test method |
GB2209224A (en) * | 1987-08-27 | 1989-05-04 | Teradyne Inc | Fault diagnosis in circuits |
-
1969
- 1969-08-29 GB GB1322182D patent/GB1322182A/en not_active Expired
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2167196A (en) * | 1984-11-09 | 1986-05-21 | Membrain Ltd | Device orientation test method |
US4727317A (en) * | 1984-11-09 | 1988-02-23 | Membrain Ltd. | Device orientation test method suitable for automatic test equipment |
GB2209224A (en) * | 1987-08-27 | 1989-05-04 | Teradyne Inc | Fault diagnosis in circuits |
GB2209224B (en) * | 1987-08-27 | 1992-01-29 | Teradyne Inc | Diagnosis of faults in circuits |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PS | Patent sealed | ||
PCNP | Patent ceased through non-payment of renewal fee |