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GB1255334A - Integrated circuits - Google Patents

Integrated circuits

Info

Publication number
GB1255334A
GB1255334A GB5690668A GB5690668A GB1255334A GB 1255334 A GB1255334 A GB 1255334A GB 5690668 A GB5690668 A GB 5690668A GB 5690668 A GB5690668 A GB 5690668A GB 1255334 A GB1255334 A GB 1255334A
Authority
GB
United Kingdom
Prior art keywords
mesas
substrate
electrodes
strips
photo
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB5690668A
Inventor
Gerald George Palmer
Chang Soo Kim
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
General Electric Co
Original Assignee
General Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by General Electric Co filed Critical General Electric Co
Publication of GB1255334A publication Critical patent/GB1255334A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H—ELECTRICITY
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    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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    • H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
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    • H01L2924/30107—Inductance

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

1,255,334. Printed circuit assemblies; semiconductor devices. GENERAL ELECTRIC CO. 29 Nov., 1968 [1 Dec., 1967], No. 56906/68. Headings H1K and H1R. In an integrated circuit structure semiconductor chips are bonded to a dielectric substrate carrying a conductive pattern and contact electrodes of the chips are connected coplanely with terminal members of the conductive pattern. In a first embodiment, Figs. 1A, 1B, a dielectric substrate 3 of alumina, glass or ceramic magnetic material is first provided with a thin film circuit comprising resistors 5 and conductors 4 formed by photo-etch methods or evaporating through a mask. A plurality of terminal conductors or mesas 9 are then constructed at end points on the conductor strips by evaporating a layer of copper over the whole surface and electroplating and removing unwanted copper by a photo-etch process to leave the mesas 9. Mesas 11 which are used in the final assembly to form cross-overs and registration mesas 12 are formed at the same time. Electrical insulation material 13 is then applied over the whole surface after which a semiconductor chip 2 is pressed into material 13 so that contact electrodes 10 are flush with the top surface of material 13. Finally a layer of non- oxidizing metal is evaporated over the entire surface and the conductor strips 14 formed by a photo-etch process. At the same time capacitor electrodes may be formed which co-operate with electrodes formed in the conductor layer 4 to form capacitors. Alternatively the electrodes and strips 14 may be formed by evaporating metal through a photo-resist mask. Passive components such as resistors 5, capacitors 4 and inductors 7 can be formed on the top surface of the dielectric material 13 as well as substrate 1. In the embodiment of Figs. 5A, 5B (not shown) the registration mesas are constructed to a height less than the terminal mesas. The chip may be mounted face down on substrate 21, Fig. 6B, in which case it is bonded to the surface of the substrate by means of a thin film of adhesive material 23. Conductive strips 22 on the layer 23 are coplanar with contact electrodes 25 of the chip and are connected therewith by abbreviated conductor strips 26 which overlay the ends of strips 22 and electrodes 25. Passive components may be deposited on the surface of film 23. The chip may be mounted on a pedestal formed in the surface of substrate 21, Fig. 7 (not shown). A plurality of chips may be mounted on a single substrate, Fig. 8 (not shown), connected to perform digital operations.
GB5690668A 1967-12-01 1968-11-29 Integrated circuits Expired GB1255334A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US68727867A 1967-12-01 1967-12-01

Publications (1)

Publication Number Publication Date
GB1255334A true GB1255334A (en) 1971-12-01

Family

ID=24759796

Family Applications (1)

Application Number Title Priority Date Filing Date
GB5690668A Expired GB1255334A (en) 1967-12-01 1968-11-29 Integrated circuits

Country Status (4)

Country Link
DE (1) DE1812157A1 (en)
FR (1) FR1593872A (en)
GB (1) GB1255334A (en)
NL (1) NL6817108A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3919602A (en) * 1972-03-23 1975-11-11 Bosch Gmbh Robert Electric circuit arrangement and method of making the same

Also Published As

Publication number Publication date
NL6817108A (en) 1969-06-03
FR1593872A (en) 1970-06-01
DE1812157A1 (en) 1969-07-17

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