GB1204805A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- GB1204805A GB1204805A GB30463/68A GB3046368A GB1204805A GB 1204805 A GB1204805 A GB 1204805A GB 30463/68 A GB30463/68 A GB 30463/68A GB 3046368 A GB3046368 A GB 3046368A GB 1204805 A GB1204805 A GB 1204805A
- Authority
- GB
- United Kingdom
- Prior art keywords
- layer
- screen
- transistor
- type
- conductive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/731—Location prior to the connecting process
- H01L2224/73101—Location prior to the connecting process on the same surface
- H01L2224/73103—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1203—Rectifying Diode
- H01L2924/12036—PN diode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Bipolar Transistors (AREA)
Abstract
1,204,805. Semi-conductor devices; circuit assemblies. HITACHI Ltd. 26 June, 1968 [7 July, 1967], No. 30463/68. Headings H1K and H1R. A semi-conductor device is provided with an electrode having a conductive track extending to a point at which it is not covered by a conductive layer insulated from and overlying the electrode. The conductive layer constitutes a protective screen for the active area of the semiconductor device and overlies an insulating layer which isolates it from the electrodes and from the surface of the semi-conductor wafer. The screen protects the insulating layer from moisture and prevents the accumulation of surface charges. As shown, Fig. 2, a planar transistor is produced by epitaxially depositing a high resistivity N-type silicon layer 23 on an N+ type substrate 22 and forming a P-type base region 24, an N+ type emitter region 25 and an N- type collector contact region 26 by diffusion using silicon oxide masking layer 27. Conductive tracks 28, 29, 30 are applied to the collector, base and emitter regions the latter two tracks extending over the oxide layer to points outside the active area of the device. A second insulating layer 31, for example of a silicate glass, is deposited over the surface, windows are formed to expose the conductive tracks 28, 29, 30, and contact pads 32, 33 (34) are applied and a conductive screen 35 is applied over the insulating layer 31 so that it covers the edges of the junctions. Solder layers 36, 37, (38) and 39 are applied to the contact pads 32, 33, (34) and the screen 35 respectively. The transistor is face bonded to the conductors of a printed circuit board 40 which contains a high thermal conductivity metal insert 46 to which the screen 35 is bonded to provide improved thermal radiation. The insert 46 may be arranged in contact with a heat radiator. The screen 35 is connected to a source of constant potential, e.g. ground, and if the transistor is operated in the common emitter configuration screen 35 may be connected directly to the emitter of the transistor. One or both of the insulating layers may comprise silicon nitride. In a transistor not intended for face bonding to a printed circuit, Fig. 1 (not shown), the solder layers are omitted and the collector electrode is applied to the N+ type substrate. In a junction isolated integrated circuit, Fig. 3 (not shown) a resistor (52) and a transistor (53) are covered by a common screen layer (56) comprising an aluminium layer (56b) covered with a layer (56a) of gold or solder. The invention may also be applied to PNP transistors, planar diodes, and mesa type devices.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4333467 | 1967-07-07 |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1204805A true GB1204805A (en) | 1970-09-09 |
Family
ID=12660920
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB30463/68A Expired GB1204805A (en) | 1967-07-07 | 1968-06-26 | Semiconductor device |
Country Status (2)
Country | Link |
---|---|
DE (1) | DE1764619C3 (en) |
GB (1) | GB1204805A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3754170A (en) * | 1971-08-26 | 1973-08-21 | Sony Corp | Integrated circuit device having monolithic rf shields |
US4177480A (en) * | 1975-10-02 | 1979-12-04 | Licentia Patent-Verwaltungs-G.M.B.H. | Integrated circuit arrangement with means for avoiding undesirable capacitive coupling between leads |
US4266239A (en) * | 1976-04-05 | 1981-05-05 | Nippon Electric Co., Ltd. | Semiconductor device having improved high frequency characteristics |
US4380115A (en) * | 1979-12-06 | 1983-04-19 | Solid State Scientific, Inc. | Method of making a semiconductor device with a seal |
US4580157A (en) * | 1979-06-08 | 1986-04-01 | Fujitsu Limited | Semiconductor device having a soft-error preventing structure |
-
1968
- 1968-06-26 GB GB30463/68A patent/GB1204805A/en not_active Expired
- 1968-07-05 DE DE1764619A patent/DE1764619C3/en not_active Expired
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3754170A (en) * | 1971-08-26 | 1973-08-21 | Sony Corp | Integrated circuit device having monolithic rf shields |
US4177480A (en) * | 1975-10-02 | 1979-12-04 | Licentia Patent-Verwaltungs-G.M.B.H. | Integrated circuit arrangement with means for avoiding undesirable capacitive coupling between leads |
US4266239A (en) * | 1976-04-05 | 1981-05-05 | Nippon Electric Co., Ltd. | Semiconductor device having improved high frequency characteristics |
US4580157A (en) * | 1979-06-08 | 1986-04-01 | Fujitsu Limited | Semiconductor device having a soft-error preventing structure |
US4380115A (en) * | 1979-12-06 | 1983-04-19 | Solid State Scientific, Inc. | Method of making a semiconductor device with a seal |
Also Published As
Publication number | Publication date |
---|---|
DE1764619A1 (en) | 1971-05-27 |
DE1764619B2 (en) | 1973-05-24 |
DE1764619C3 (en) | 1973-12-06 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PS | Patent sealed | ||
PE20 | Patent expired after termination of 20 years |