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GB1026524A - Semiconductor device and method of manufacturing same - Google Patents

Semiconductor device and method of manufacturing same

Info

Publication number
GB1026524A
GB1026524A GB12343/63A GB1234363A GB1026524A GB 1026524 A GB1026524 A GB 1026524A GB 12343/63 A GB12343/63 A GB 12343/63A GB 1234363 A GB1234363 A GB 1234363A GB 1026524 A GB1026524 A GB 1026524A
Authority
GB
United Kingdom
Prior art keywords
layer
micron
electrode
mesh
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB12343/63A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
EUROP DES SEMICONDUCTEURS SOC
Original Assignee
EUROP DES SEMICONDUCTEURS SOC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by EUROP DES SEMICONDUCTEURS SOC filed Critical EUROP DES SEMICONDUCTEURS SOC
Publication of GB1026524A publication Critical patent/GB1026524A/en
Expired legal-status Critical Current

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Classifications

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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H01L2924/30111—Impedance matching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

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  • Engineering & Computer Science (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Thyristors (AREA)

Abstract

1,026,524. Semi-conductor devices. SOC. EUROPEENNE DES SEMICONDUCTEURS. March 28, 1963 [March 28, 1962], No. 12343/63. Heading H1K. A semi-conductor device having operating characteristics intermediate those of field transistors and junction transistors comprises, in one embodiment, a silicon wafer 13 (Fig. 5) of high N-type conductivity welded to a metal plate 20 (forming the cathode) and carrying on its upper surface an epitaxially deposited layer 14 of silicon of lower N-conductivity between which and an electrode 19 (forming the anode) consisting of antimony doped gold a control electrode 15 is formed the latter having a mesh form the average diameter of the openings of which is of the order of one micron and the width of the bars of the mesh of the order of 0À1 micron. The control electrode is made of aluminium and some of this alloys with and/or diffuses into the layer 14 thus producing areas of P-type conductivity in the regions 17 immediately underlying the mesh elements the upper surfaces 18 of which are oxidized to provide an insulating alumina coating between these surfaces and electrode 19. Because the small size of the mesh openings, i.e. about one micron, is of the same order as the depth of the depletion zone arising near the interface between the opposite conductivity regions 14, 17 in the absence of a potential difference between these regions, no appreciable current flows between the (anode) electrode 19 and the (cathode) electrode 20 (unless, of course, the voltage applied between the latter electrodes exceeds the breakdown voltage at the P-N- junction). One method of producing the fine mesh which the invention requires comprises screening-off a marginal area 31 (Figs. 7 to 10, not shown) of layer 14, evaporating on to the latter a one micron silver layer 30, heating to 500‹ C. (in vacuo) to produce a multiplicity of silver spherules 32 (2 or 3 microns in diameter), evaporating aluminium over the entire surface and then removing the silver spherules by nitric acid. Heat treatment is then employed to alloy the resulting aluminium grid 33 with the underlying silicon. In another method, a marginal area is masked-off, as before, and over the remaining surface of layer 14 a layer of particles 35 (Figs. 11 and 12, not shown) of silver containing 1% antimony (of about one micron diameter) is deposited from a liquid dispersion to form a micro-screen. Microparticles of gold containing 2% gallium are then sedimented over this screen and settle in part at 36 and in part at 38 and by heating to a temperature above the melting point of the gold-gallium-silicon eutectic the particles 38 are alloyed to the silicon layer 14 to form a foraminous grid structure 39. The anode of the device is then formed by a gold or goldplated metal strip 41 attached by thermocompression at about 300‹ C. and the connection to the control electrode constituted by the grid 39 is effected through the marginal portion 37. The theory of the device is discussed with reference to Fig. 4 (not shown) and a complete encapsulated device is described with reference to Fig. 6 (not shown).
GB12343/63A 1962-03-28 1963-03-28 Semiconductor device and method of manufacturing same Expired GB1026524A (en)

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FR892565A FR1326520A (en) 1962-03-28 1962-03-28 New semiconductor device and its manufacturing process

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GB1026524A true GB1026524A (en) 1966-04-20

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3982264A (en) * 1973-04-25 1976-09-21 Sony Corporation Junction gated field effect transistor

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4106044A (en) * 1974-03-16 1978-08-08 Nippon Gakki Seizo Kabushiki Kaisha Field effect transistor having unsaturated characteristics

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3982264A (en) * 1973-04-25 1976-09-21 Sony Corporation Junction gated field effect transistor

Also Published As

Publication number Publication date
FR1326520A (en) 1963-05-10

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