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FR3076397B1 - Procede de fabrication d'un transistor - Google Patents

Procede de fabrication d'un transistor Download PDF

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Publication number
FR3076397B1
FR3076397B1 FR1763407A FR1763407A FR3076397B1 FR 3076397 B1 FR3076397 B1 FR 3076397B1 FR 1763407 A FR1763407 A FR 1763407A FR 1763407 A FR1763407 A FR 1763407A FR 3076397 B1 FR3076397 B1 FR 3076397B1
Authority
FR
France
Prior art keywords
transistor
stack
active layer
grid
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR1763407A
Other languages
English (en)
Other versions
FR3076397A1 (fr
Inventor
Nicolas Pons
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
X Fab France SAS
Original Assignee
X Fab France SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by X Fab France SAS filed Critical X Fab France SAS
Priority to FR1763407A priority Critical patent/FR3076397B1/fr
Priority to US16/232,847 priority patent/US10868147B2/en
Publication of FR3076397A1 publication Critical patent/FR3076397A1/fr
Application granted granted Critical
Publication of FR3076397B1 publication Critical patent/FR3076397B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6744—Monocrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0251—Manufacture or treatment of multiple TFTs characterised by increasing the uniformity of device parameters

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)

Abstract

La présente invention concerne un procédé de formation d'un transistor à partir d'un empilement de couches comprenant au moins une couche isolante surmontée d'au moins une couche active (110) et d'au moins une première (120) et une deuxième (120) tranchées isolantes définissant dans la couche active une zone d'accueil destinée à accueillir ledit transistor, ledit transistor comprenant un canal de conduction formé en partie au moins dans la couche active (110), le procédé comprenant au moins les étapes suivantes : a) Formation d'un empilement de grille (200) s'étendant au-dessus au moins dudit canal de conduction ; b) Formation d'une zone source et d'une zone drain ; le procédé étant caractérisé en ce que la formation de l'empilement de grille (200) est réalisée de sorte à ménager au moins une première (111) et une deuxième portions (112) de la zone d'accueil, non recouvertes par ledit empilement de grille (200).
FR1763407A 2017-12-29 2017-12-29 Procede de fabrication d'un transistor Active FR3076397B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR1763407A FR3076397B1 (fr) 2017-12-29 2017-12-29 Procede de fabrication d'un transistor
US16/232,847 US10868147B2 (en) 2017-12-29 2018-12-26 Method of manufacturing a transistor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1763407 2017-12-29
FR1763407A FR3076397B1 (fr) 2017-12-29 2017-12-29 Procede de fabrication d'un transistor

Publications (2)

Publication Number Publication Date
FR3076397A1 FR3076397A1 (fr) 2019-07-05
FR3076397B1 true FR3076397B1 (fr) 2019-12-27

Family

ID=61873502

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1763407A Active FR3076397B1 (fr) 2017-12-29 2017-12-29 Procede de fabrication d'un transistor

Country Status (2)

Country Link
US (1) US10868147B2 (fr)
FR (1) FR3076397B1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2600953B (en) * 2020-11-12 2023-06-07 X Fab Global Services Gmbh Reduced flicker noise transistor layout

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8174074B2 (en) * 2009-09-01 2012-05-08 International Business Machines Corporation Asymmetric embedded silicon germanium field effect transistor
US8685847B2 (en) * 2010-10-27 2014-04-01 International Business Machines Corporation Semiconductor device having localized extremely thin silicon on insulator channel region
FR3002078B1 (fr) * 2013-02-11 2015-03-27 Commissariat Energie Atomique Procede de realisation d'une couche semi-conductrice presentant au moins deux epaisseurs differentes
US9219117B2 (en) * 2014-04-22 2015-12-22 Infineon Technologies Ag Semiconductor structure and a method for processing a carrier
KR102449211B1 (ko) * 2016-01-05 2022-09-30 삼성전자주식회사 전계 효과 트랜지스터를 포함하는 반도체 소자
FR3051973B1 (fr) * 2016-05-24 2018-10-19 X-Fab France Procede de formation de transistors pdsoi et fdsoi sur un meme substrat

Also Published As

Publication number Publication date
US10868147B2 (en) 2020-12-15
US20190221656A1 (en) 2019-07-18
FR3076397A1 (fr) 2019-07-05

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