FR3029352B1 - Procede d'assemblage de deux substrats - Google Patents
Procede d'assemblage de deux substratsInfo
- Publication number
- FR3029352B1 FR3029352B1 FR1461544A FR1461544A FR3029352B1 FR 3029352 B1 FR3029352 B1 FR 3029352B1 FR 1461544 A FR1461544 A FR 1461544A FR 1461544 A FR1461544 A FR 1461544A FR 3029352 B1 FR3029352 B1 FR 3029352B1
- Authority
- FR
- France
- Prior art keywords
- substrates
- assembling
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B37/00—Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding
- B32B37/0007—Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding involving treatment or provisions in order to avoid deformation or air inclusion, e.g. to improve surface quality
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B38/00—Ancillary operations in connection with laminating processes
- B32B38/0036—Heat treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B38/00—Ancillary operations in connection with laminating processes
- B32B38/0036—Heat treatment
- B32B2038/0048—Annealing, relaxing
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B2250/00—Layers arrangement
- B32B2250/02—2 layers
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B2307/00—Properties of the layers or laminate
- B32B2307/70—Other properties
- B32B2307/728—Hydrophilic
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B2309/00—Parameters for the laminating or treatment process; Apparatus details
- B32B2309/60—In a particular environment
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B2313/00—Elements other than metals
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B2457/00—Electrical equipment
- B32B2457/14—Semiconductor wafers
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01D—MEASURING NOT SPECIALLY ADAPTED FOR A SPECIFIC VARIABLE; ARRANGEMENTS FOR MEASURING TWO OR MORE VARIABLES NOT COVERED IN A SINGLE OTHER SUBCLASS; TARIFF METERING APPARATUS; MEASURING OR TESTING NOT OTHERWISE PROVIDED FOR
- G01D2207/00—Indexing scheme relating to details of indicating measuring values
- G01D2207/10—Displays which are primarily used in aircraft or display aircraft-specific information
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Thermal Sciences (AREA)
- Quality & Reliability (AREA)
- Chemical & Material Sciences (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
- Ceramic Products (AREA)
- Pressure Welding/Diffusion-Bonding (AREA)
- Analytical Chemistry (AREA)
- Organic Chemistry (AREA)
- Cleaning Or Drying Semiconductors (AREA)
- Lining Or Joining Of Plastics Or The Like (AREA)
- Combinations Of Printed Boards (AREA)
- Adhesives Or Adhesive Processes (AREA)
- Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)
- Coupling Device And Connection With Printed Circuit (AREA)
- Electroluminescent Light Sources (AREA)
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1461544A FR3029352B1 (fr) | 2014-11-27 | 2014-11-27 | Procede d'assemblage de deux substrats |
JP2015227657A JP6643873B2 (ja) | 2014-11-27 | 2015-11-20 | 2枚の基板を積層する方法 |
US14/947,254 US9718261B2 (en) | 2014-11-27 | 2015-11-20 | Assembly process of two substrates |
CN201510830557.2A CN105655243B (zh) | 2014-11-27 | 2015-11-25 | 组合两个衬底的方法 |
KR1020150165535A KR102446438B1 (ko) | 2014-11-27 | 2015-11-25 | 두 개의 기판들의 조립 방법 |
DE102015223347.2A DE102015223347A1 (de) | 2014-11-27 | 2015-11-25 | Verfahren zum verbinden zweier substrate |
AT510142015A AT516576B1 (de) | 2014-11-27 | 2015-11-27 | Verfahren zum Verbinden von zwei Substraten |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1461544A FR3029352B1 (fr) | 2014-11-27 | 2014-11-27 | Procede d'assemblage de deux substrats |
Publications (2)
Publication Number | Publication Date |
---|---|
FR3029352A1 FR3029352A1 (fr) | 2016-06-03 |
FR3029352B1 true FR3029352B1 (fr) | 2017-01-06 |
Family
ID=53298424
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR1461544A Active FR3029352B1 (fr) | 2014-11-27 | 2014-11-27 | Procede d'assemblage de deux substrats |
Country Status (7)
Country | Link |
---|---|
US (1) | US9718261B2 (fr) |
JP (1) | JP6643873B2 (fr) |
KR (1) | KR102446438B1 (fr) |
CN (1) | CN105655243B (fr) |
AT (1) | AT516576B1 (fr) |
DE (1) | DE102015223347A1 (fr) |
FR (1) | FR3029352B1 (fr) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI747517B (zh) | 2015-11-19 | 2021-11-21 | 日商勃朗科技股份有限公司 | 被冷凍生鮮動植物或其部分之製造方法、及被解凍物或其加工物 |
WO2018212335A1 (fr) | 2017-05-18 | 2018-11-22 | ブランテック株式会社 | Dispositif de commande de changement de phase et procédé de commande de changement de phase |
CN111640814B (zh) * | 2020-06-05 | 2022-05-20 | 天津三安光电有限公司 | 一种太阳电池结构及其制备方法 |
US12040513B2 (en) | 2022-11-18 | 2024-07-16 | Carbon Ventures, Llc | Enhancing efficiencies of oxy-combustion power cycles |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07193203A (ja) * | 1993-12-27 | 1995-07-28 | Canon Inc | 半導体基体の製造方法 |
AU9296098A (en) * | 1997-08-29 | 1999-03-16 | Sharon N. Farrens | In situ plasma wafer bonding method |
FR2903808B1 (fr) * | 2006-07-11 | 2008-11-28 | Soitec Silicon On Insulator | Procede de collage direct de deux substrats utilises en electronique, optique ou opto-electronique |
US7575988B2 (en) * | 2006-07-11 | 2009-08-18 | S.O.I.Tec Silicon On Insulator Technologies | Method of fabricating a hybrid substrate |
EP2091071B1 (fr) | 2008-02-15 | 2012-12-12 | Soitec | Procédé pour la liaison de deux substrats |
EP2200077B1 (fr) * | 2008-12-22 | 2012-12-05 | Soitec | Procédé pour la liaison de deux substrats |
US10825793B2 (en) * | 2011-04-08 | 2020-11-03 | Ev Group E. Thallner Gmbh | Method for permanently bonding wafers |
FR2980916B1 (fr) * | 2011-10-03 | 2014-03-28 | Soitec Silicon On Insulator | Procede de fabrication d'une structure de type silicium sur isolant |
FR2980919B1 (fr) * | 2011-10-04 | 2014-02-21 | Commissariat Energie Atomique | Procede de double report de couche |
FR2990054B1 (fr) | 2012-04-27 | 2014-05-02 | Commissariat Energie Atomique | Procede de collage dans une atmosphere de gaz presentant un coefficient de joule-thomson negatif. |
US8796054B2 (en) * | 2012-05-31 | 2014-08-05 | Corning Incorporated | Gallium nitride to silicon direct wafer bonding |
FR3000092B1 (fr) * | 2012-12-26 | 2015-01-16 | Commissariat Energie Atomique | Traitement de surface par plasma chlore dans un procede de collage |
-
2014
- 2014-11-27 FR FR1461544A patent/FR3029352B1/fr active Active
-
2015
- 2015-11-20 JP JP2015227657A patent/JP6643873B2/ja active Active
- 2015-11-20 US US14/947,254 patent/US9718261B2/en active Active
- 2015-11-25 CN CN201510830557.2A patent/CN105655243B/zh active Active
- 2015-11-25 KR KR1020150165535A patent/KR102446438B1/ko active Active
- 2015-11-25 DE DE102015223347.2A patent/DE102015223347A1/de active Pending
- 2015-11-27 AT AT510142015A patent/AT516576B1/de active
Also Published As
Publication number | Publication date |
---|---|
FR3029352A1 (fr) | 2016-06-03 |
JP6643873B2 (ja) | 2020-02-12 |
AT516576B1 (de) | 2019-11-15 |
AT516576A2 (de) | 2016-06-15 |
DE102015223347A1 (de) | 2016-06-02 |
KR102446438B1 (ko) | 2022-09-22 |
KR20160064011A (ko) | 2016-06-07 |
CN105655243A (zh) | 2016-06-08 |
AT516576A3 (de) | 2017-11-15 |
CN105655243B (zh) | 2020-05-15 |
US9718261B2 (en) | 2017-08-01 |
US20160152017A1 (en) | 2016-06-02 |
JP2016103637A (ja) | 2016-06-02 |
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Legal Events
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