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FR3029352B1 - Procede d'assemblage de deux substrats - Google Patents

Procede d'assemblage de deux substrats

Info

Publication number
FR3029352B1
FR3029352B1 FR1461544A FR1461544A FR3029352B1 FR 3029352 B1 FR3029352 B1 FR 3029352B1 FR 1461544 A FR1461544 A FR 1461544A FR 1461544 A FR1461544 A FR 1461544A FR 3029352 B1 FR3029352 B1 FR 3029352B1
Authority
FR
France
Prior art keywords
substrates
assembling
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR1461544A
Other languages
English (en)
Other versions
FR3029352A1 (fr
Inventor
Didier Landru
Capucine Delage
Franck Fournel
Elodie Beche
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
Soitec SA
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat a lEnergie Atomique CEA, Soitec SA, Commissariat a lEnergie Atomique et aux Energies Alternatives CEA filed Critical Commissariat a lEnergie Atomique CEA
Priority to FR1461544A priority Critical patent/FR3029352B1/fr
Priority to US14/947,254 priority patent/US9718261B2/en
Priority to JP2015227657A priority patent/JP6643873B2/ja
Priority to KR1020150165535A priority patent/KR102446438B1/ko
Priority to CN201510830557.2A priority patent/CN105655243B/zh
Priority to DE102015223347.2A priority patent/DE102015223347A1/de
Priority to AT510142015A priority patent/AT516576B1/de
Publication of FR3029352A1 publication Critical patent/FR3029352A1/fr
Application granted granted Critical
Publication of FR3029352B1 publication Critical patent/FR3029352B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B37/00Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding
    • B32B37/0007Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding involving treatment or provisions in order to avoid deformation or air inclusion, e.g. to improve surface quality
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B38/00Ancillary operations in connection with laminating processes
    • B32B38/0036Heat treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B38/00Ancillary operations in connection with laminating processes
    • B32B38/0036Heat treatment
    • B32B2038/0048Annealing, relaxing
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2250/00Layers arrangement
    • B32B2250/022 layers
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2307/00Properties of the layers or laminate
    • B32B2307/70Other properties
    • B32B2307/728Hydrophilic
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2309/00Parameters for the laminating or treatment process; Apparatus details
    • B32B2309/60In a particular environment
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2313/00Elements other than metals
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2457/00Electrical equipment
    • B32B2457/14Semiconductor wafers
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01DMEASURING NOT SPECIALLY ADAPTED FOR A SPECIFIC VARIABLE; ARRANGEMENTS FOR MEASURING TWO OR MORE VARIABLES NOT COVERED IN A SINGLE OTHER SUBCLASS; TARIFF METERING APPARATUS; MEASURING OR TESTING NOT OTHERWISE PROVIDED FOR
    • G01D2207/00Indexing scheme relating to details of indicating measuring values
    • G01D2207/10Displays which are primarily used in aircraft or display aircraft-specific information
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Thermal Sciences (AREA)
  • Quality & Reliability (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Ceramic Products (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
  • Analytical Chemistry (AREA)
  • Organic Chemistry (AREA)
  • Cleaning Or Drying Semiconductors (AREA)
  • Lining Or Joining Of Plastics Or The Like (AREA)
  • Combinations Of Printed Boards (AREA)
  • Adhesives Or Adhesive Processes (AREA)
  • Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)
  • Electroluminescent Light Sources (AREA)
FR1461544A 2014-11-27 2014-11-27 Procede d'assemblage de deux substrats Active FR3029352B1 (fr)

Priority Applications (7)

Application Number Priority Date Filing Date Title
FR1461544A FR3029352B1 (fr) 2014-11-27 2014-11-27 Procede d'assemblage de deux substrats
JP2015227657A JP6643873B2 (ja) 2014-11-27 2015-11-20 2枚の基板を積層する方法
US14/947,254 US9718261B2 (en) 2014-11-27 2015-11-20 Assembly process of two substrates
CN201510830557.2A CN105655243B (zh) 2014-11-27 2015-11-25 组合两个衬底的方法
KR1020150165535A KR102446438B1 (ko) 2014-11-27 2015-11-25 두 개의 기판들의 조립 방법
DE102015223347.2A DE102015223347A1 (de) 2014-11-27 2015-11-25 Verfahren zum verbinden zweier substrate
AT510142015A AT516576B1 (de) 2014-11-27 2015-11-27 Verfahren zum Verbinden von zwei Substraten

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR1461544A FR3029352B1 (fr) 2014-11-27 2014-11-27 Procede d'assemblage de deux substrats

Publications (2)

Publication Number Publication Date
FR3029352A1 FR3029352A1 (fr) 2016-06-03
FR3029352B1 true FR3029352B1 (fr) 2017-01-06

Family

ID=53298424

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1461544A Active FR3029352B1 (fr) 2014-11-27 2014-11-27 Procede d'assemblage de deux substrats

Country Status (7)

Country Link
US (1) US9718261B2 (fr)
JP (1) JP6643873B2 (fr)
KR (1) KR102446438B1 (fr)
CN (1) CN105655243B (fr)
AT (1) AT516576B1 (fr)
DE (1) DE102015223347A1 (fr)
FR (1) FR3029352B1 (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI747517B (zh) 2015-11-19 2021-11-21 日商勃朗科技股份有限公司 被冷凍生鮮動植物或其部分之製造方法、及被解凍物或其加工物
WO2018212335A1 (fr) 2017-05-18 2018-11-22 ブランテック株式会社 Dispositif de commande de changement de phase et procédé de commande de changement de phase
CN111640814B (zh) * 2020-06-05 2022-05-20 天津三安光电有限公司 一种太阳电池结构及其制备方法
US12040513B2 (en) 2022-11-18 2024-07-16 Carbon Ventures, Llc Enhancing efficiencies of oxy-combustion power cycles

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07193203A (ja) * 1993-12-27 1995-07-28 Canon Inc 半導体基体の製造方法
AU9296098A (en) * 1997-08-29 1999-03-16 Sharon N. Farrens In situ plasma wafer bonding method
FR2903808B1 (fr) * 2006-07-11 2008-11-28 Soitec Silicon On Insulator Procede de collage direct de deux substrats utilises en electronique, optique ou opto-electronique
US7575988B2 (en) * 2006-07-11 2009-08-18 S.O.I.Tec Silicon On Insulator Technologies Method of fabricating a hybrid substrate
EP2091071B1 (fr) 2008-02-15 2012-12-12 Soitec Procédé pour la liaison de deux substrats
EP2200077B1 (fr) * 2008-12-22 2012-12-05 Soitec Procédé pour la liaison de deux substrats
US10825793B2 (en) * 2011-04-08 2020-11-03 Ev Group E. Thallner Gmbh Method for permanently bonding wafers
FR2980916B1 (fr) * 2011-10-03 2014-03-28 Soitec Silicon On Insulator Procede de fabrication d'une structure de type silicium sur isolant
FR2980919B1 (fr) * 2011-10-04 2014-02-21 Commissariat Energie Atomique Procede de double report de couche
FR2990054B1 (fr) 2012-04-27 2014-05-02 Commissariat Energie Atomique Procede de collage dans une atmosphere de gaz presentant un coefficient de joule-thomson negatif.
US8796054B2 (en) * 2012-05-31 2014-08-05 Corning Incorporated Gallium nitride to silicon direct wafer bonding
FR3000092B1 (fr) * 2012-12-26 2015-01-16 Commissariat Energie Atomique Traitement de surface par plasma chlore dans un procede de collage

Also Published As

Publication number Publication date
FR3029352A1 (fr) 2016-06-03
JP6643873B2 (ja) 2020-02-12
AT516576B1 (de) 2019-11-15
AT516576A2 (de) 2016-06-15
DE102015223347A1 (de) 2016-06-02
KR102446438B1 (ko) 2022-09-22
KR20160064011A (ko) 2016-06-07
CN105655243A (zh) 2016-06-08
AT516576A3 (de) 2017-11-15
CN105655243B (zh) 2020-05-15
US9718261B2 (en) 2017-08-01
US20160152017A1 (en) 2016-06-02
JP2016103637A (ja) 2016-06-02

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