FR3012668A1 - SILICON-BASED COMPOSITE SUBSTRATE WITH ACTIVE ZONES SEPARATED BY SILICON OXIDE-BASED ELECTRICAL INSULATION ZONES - Google Patents

Abstract

The present invention relates to a composite substrate (1) based on silicon, having, in a vertical sectional plane, active areas (10) of p-doped and / or n-doped silicon, each of the active zones extending over the entire thickness (e) of the substrate, two active zones being separated from each other by at least one electrical insulation zone (20) comprising a mass content of silicon oxide greater than or equal to 50%. It also relates to methods of manufacturing such a composite substrate.

Description

The present invention relates to a novel silicon-based substrate, vertically divided into several sub-cells isolated from each other, and to different process variants for its preparation. Such a substrate is particularly advantageous in the context of the development of photovoltaic cells and modules. Currently, photovoltaic modules (PV) are mainly made from the assembly of mono- or multi-crystalline silicon cells, these cells being generally made from wafers, also called "wafers", of electrical conductivity p. Type n materials are also currently in full development. In PV modules of reasonable size, of the order of m2, the size standard for the wafers (156 x 156 mm) makes the open circuit voltages (Vo, in English terminology) PV modules are limited to a few dozen Volts. Different ways have been explored to try to increase the voltage Vo, PV modules. A first option could be to use materials other than crystalline silicon (Si), in particular semiconductors having amplitudes of band gap (or "band gap" in English) higher than 1.1 eV (electron-volt) silicon, such as an amorphous Si type material on crystalline Si, resulting from the so-called heterojunction technology, or even CdTe type materials (cadmium telluride). Unfortunately, the improvement in terms of open circuit voltages is limited because the use of bandgap semiconductors that are too high (> 2 eV) leads to a significant decrease in the amount of photons absorbed and a loss in efficiency. energy conversion.

Another possibility would be to reduce the size of the cells compared to the current standard of 156 x 156 mm, which would make it possible, by placing in series a greater number of cells forming the module, to increase the value of the voltage. ,. However, this solution would make more difficult handling operations for the development of modules. Moreover, the need to keep a space between cells forming the PV module for the connection leads to a loss of useful area (i.e. allowing the photogeneration of electric carriers). This loss of surface is greater with the implementation of a larger number of cells of reduced size. Finally, except using a technology of rear contact cell (RCC, Rear Contact Cell in English terminology), this solution poses delicate problems of metallization and connectivity. More recently, Pozner et al. [1] have modeled the serialization of cells with vertical p / n junction planes, unlike the configuration of conventional wafers where the junction plane is horizontal. The advantage of this approach is to be able to consider a collective type of treatment, monolithic substrate, for the realization of cells. However, the size of the individual elements is small, of the order of one hundred micrometers, and many technical questions remain open as to the practical realization of such a structure, the cost of which, moreover, risks being very high. It could still be envisaged to make a monolithic wafer of standard size 156 × 156 mm, and to subsequently etch trenches, for example by laser ablation, which would have the effect of actually creating a plurality of cells of smaller size. In this context, an original architecture has recently been proposed by the research center "Energy research center of the Netherlands" (ECN) with a structure of maintenance on the front to overcome handling problems [2]. However, the problem of electrical passivation of the surfaces created by laser ablation is complex, the rates of recombination of surface minority charge carriers being greater than 2,000 cm / s.

Therefore, there remains a need, for the development of high voltage open circuit cells for photovoltaic applications, to make silicon wafers divided into active zones (also called "sub-cells"), separated from each other by areas of electrical insulation. The aim of the present invention is precisely to propose a novel silicon-based substrate, vertically divided into several sub-cells isolated from one another by zones of electrical insulation, guaranteeing good passivation at the interfaces between the active zone and the isolation zone. as well as methods for accessing such a substrate. More specifically, the present invention relates, according to a first of its aspects, to a silicon-based composite substrate having, in a vertical sectional plane, active zones of p-doped and / or n-doped silicon, each of the active zones. extending over the entire thickness of the substrate, two active regions being separated from each other by at least one electrical insulation zone comprising a silicon oxide content by mass greater than or equal to 50%. In the rest of the text, and unless otherwise indicated, the substrate is characterized when observed in its horizontal position. In other words, the substrate extends in at least one direction normal to the vertical direction. Thus, in particular, the substrate according to the invention is defined as being vertically divided into sub-cells, in a vertical sectional plane of the horizontally positioned substrate. By "active zone" is meant an area suitable for implementing the photovoltaic effect. It is a p-doped or n-doped silicon zone.

By "electrical insulation zone" is meant an area of the substrate having a high electrical resistivity, in particular greater than or equal to 2 kflcm and advantageously greater than or equal to 10 kflcm, still more preferably greater than 50 kflcm. In the rest of the text, these zones will be more simply referred to as "insulation zones" or "insulating zones".

According to another of its aspects, the present invention proposes methods making it possible to access, in an easy manner, such a substrate, by cutting a previously formed brick by assembling n-doped and / or p-doped silicon wafers. after creation between said slices of insulating layers. Thus, according to a first variant embodiment, the present invention thus relates to a method for preparing a silicon-based composite substrate by cutting a brick having, in at least one cutting plane, active layers of doped silicon. p and / or doped n separated from each other by electrical insulation layers, comprising at least the steps consisting of: (a) having n-doped silicon wafers and / or p, said wafers being intended to form, by assembly and after creation of the electrical insulation layers, said desired brick; (b) subjecting the faces of the wafers to be joined to a surface treatment which is suitable for imparting a surface roughness of less than or equal to 500 nm; (c) forming, on the surface of silicon wafers treated in step (b), a layer of silicon oxide with a thickness greater than or equal to 100 nm; (d) arranging the oxidized silicon wafers to constitute said desired brick, and assembling said wafers by gluing under conditions conducive to the establishment of covalent Si-O-Si bonds; and (e) cutting said resulting brick after assembly of the slices in step (d), perpendicular to the assembly planes, to obtain said desired substrate. According to a second variant embodiment, the present invention relates to a process for preparing a silicon-based composite substrate, by cutting a brick having, in at least one cutting plane, active layers of p-doped silicon and / or or doped n separated from each other by layers of electrical insulation, comprising at least the steps consisting of: (i) having n-doped and / or p-doped silicon wafers, said slices being intended to form, by assembly and after creation of layers of electrical insulation, said desired brick; (ii) forming, on the surface of the slices to be assembled, a silicon oxide layer having a thickness greater than or equal to 100 nm; (iii) depositing, on the surface of the oxidized silicon wafers, a layer of an aqueous colloidal suspension based on silica, silicon carbide and / or silicon nitride of average particle size less than or equal to 2 μm; (iv) arranging the slices thus coated at the end of step (iii) so as to constitute said desired brick, and assembling said slices by gluing under conditions conducive to the establishment of covalent Si-O-Si bonds, at a temperature greater than or equal to 1000 ° C; and (v) cutting said resulting brick after assembly of the slices in step (iv), perpendicular to the assembly planes, to obtain said desired substrate. We will speak indifferently in the following text of "slices" or "slabs" of silicon. Advantageously, these methods make it possible, by assembling n-doped or p-doped silicon wafers after the insulating layers have been created, to accurately control the size of the active zones n and / or p, as well as the size of the zones of electrical insulation in the silicon substrate formed.

Also, it is possible according to the invention, as developed in the rest of the text, to produce two-dimensional structures, for example with a layout of the active zones in a checkerboard, which advantageously makes it possible to further increase the number of sub-cells of the substrate.

According to yet another of its aspects, the present invention relates to a photovoltaic device, in particular a photovoltaic cell, comprising a composite substrate based on silicon as defined above. The photovoltaic cells according to the invention, divided into a plurality of sub-cells of controlled sizes, advantageously make it possible to produce PV modules having an increased open circuit voltage, while maintaining a reasonable standard size of the order of one m2. Other characteristics, advantages and modes of application of the substrate according to the invention and methods for its preparation will become more apparent on reading the detailed description which follows, examples of embodiments of the invention and the examination attached drawings, in which: - Figure 1 shows, schematically, in a vertical sectional plane, the structure of a composite substrate (1) according to the invention, having six active zones (10) separated from each other by areas of electrical insulation (20); - Figure 2 shows, in top view, the arrangement of the active areas (10) in a checker pattern in a substrate, according to a particular embodiment of the invention; FIG. 3 schematically represents the various steps of a method for preparing a composite substrate according to the invention, according to a first embodiment illustrated in example 1; FIG. 4 schematically represents the various steps of a method for preparing a composite substrate according to the invention, according to a second variant embodiment illustrated in example 2. It should be noted that, for reasons of clarity, the various elements in the figures are represented in free scale, the actual dimensions of the different parts are not respected.

In the rest of the text, the expressions "between ... and ...", "ranging from ... to ..." and "varying from .." are equivalent and mean to mean that the limits are included, except otherwise stated. Unless otherwise indicated, the phrase "comprising / including a" should be understood as "comprising / comprising at least one". COMPOSITE SUBSTRATE In the description that follows, reference is made to the appended FIG. A substrate according to the invention may have a thickness (e) (considered in the vertical direction) ranging from 100 to 500 μm, in particular from 150 to 300 μm. According to a particular embodiment, a substrate according to the invention may have a total length (L) ranging from 10 to 30 cm, in particular from 15 to 20 cm. As mentioned previously, a silicon substrate according to the invention has, in a vertical sectional plane, active zones (10) of p-doped and / or n-doped silicon, separated from each other by electrical isolation zones (20). ) based on silicon oxide. A substrate according to the invention may for example comprise between 2 and 100 active zones, in particular between 5 and 10 active zones. According to a first variant embodiment, the active zones (10) of a substrate 20 according to the invention can be of the same electrical conductivity. In other words, all the active areas of the substrate are n-doped, or alternatively, all the active areas of the substrate are p-doped. According to another variant embodiment, the active zones (10) of a substrate according to the invention may have different electrical conductivities, preferably alternating electrical conductivities. In other words, the substrate may have alternating n-doped active areas (10) and p-doped active areas (10), an n-doped zone and a p-doped zone being separated from each other by an insulating zone (20). The n-doped silicon zones may comprise one or more n-type doping agents. The said n-type doping agent (s) may be chosen from phosphorus (P), arsenic (As), antimony (Sb), and mixtures thereof. Preferably, the n-type doping agent is phosphorus.

The doping level of n-type doping agents, for example phosphorus, may be greater than or equal to 1014 cm-3, in particular between 1014 to 5.1016 cm-3, even more particularly from 5.1014 to 5.1015 cm-3. The n-doped zones may have, independently of one another, a density of electron-type charge carriers ranging from 1014 to 2.1016 cm-3, in particular from 5.1014 to 5.1015 CM-3. The p-doped silicon zones may comprise one or more p-type doping agents. The p-type doping agent (s) may be chosen from boron (B), aluminum (Al), gallium (Ga), indium (In), zinc (Zn) and mixtures thereof. Preferably, the p-type dopant is boron. The doping level of p-type doping agents, for example boron, may be greater than or equal to 1014 cm-3, in particular between 1014 to 5.1016 cm-3, even more particularly from 5.1014 to 1016 cm-3. The p-doped regions may have, independently of one another, a charge density of hole-type charge carriers ranging from 1014 to 2.1016 cm-3, in particular from 5.1014 to 1016 cm-3. The active areas (10) of the substrate according to the invention may have, independently of one another, a width (Li), in the plane of section, ranging from 1 mm to 10 cm, in particular from 5 mm to 5 cm. By the term "independently of one another" is meant that the width (Li) may differ from one active zone to another. In particular, the width of the active zones may differ from an active zone doped n to a p-doped active zone, in the case of a substrate having active zones of alternating electrical conductivity. In the latter case, since the n-type materials are generally less sensitive to metallic impurities than the p-type materials, the photogenerated currents are generally higher in n-doped zones than in p-doped zones. Thus, the widths of the active p-doped and n-doped zones can be adapted during the preparation of the substrate, in particular with a view to optimally matching these currents in the final silicon substrate.

An electrical isolation zone (20) of the substrate according to the invention, separating two active zones between them, comprises a mass content of silicon oxide (SiO2) of at least 50%, relative to the total mass of said zone. insulating. The nature of the electrical insulation zones (20) is likely to vary according to the method used for the preparation of the substrate of the invention, as detailed in the rest of the text. In particular, said electrical insulation zone may comprise a mass content of silicon oxide (also called "silica") greater than or equal to 75%, especially greater than or equal to 90%. More particularly, said electrical insulation zone 10 is formed entirely of silicon oxide (100% by mass). In other words, it consists of silicon oxide. According to a particular variant embodiment, the electrical isolation zones (20) of a substrate of the invention are solely formed of silicon oxide. This is the case, for example, with substrates produced according to the first embodiment variant described below. In another variant embodiment, an electrical insulation zone may comprise one or more material (s) X chosen from silicon nitride (Si3N4) and silicon carbide (SiC), the mass quantity of X being strictly less than 50%, in particular between 0 and 25%, relative to the total mass of said zone 20 of insulation. An insulation zone of the substrate of the invention is formed of particles of one or more materials X at least partially covered by a silica envelope. In this case, the cohesion of the particles is generally obtained by sintering the silica. The isolation zone may also be in the form of a silica matrix in which particles of one or more material (X) X are incorporated. According to one particular embodiment, the insulation zones of a substrate of the invention may comprise or consist of a mixture of silica and silicon carbide (SiC). According to another particular embodiment, the isolation zones of a substrate of the invention may comprise, or even consist of, a mixture of silica and silicon nitride (Si 3 N 4).

The inorganic material particles X preferably have an average particle size of less than or equal to 2 μm, in particular less than or equal to 1 μm, in particular between 20 and 500 nm.

Advantageously, the presence of silica contiguous to the active zones makes it possible to ensure good passivation at the interfaces between the active zones and the isolation zones in the substrate. In particular, the recombination rate of the minority charge carriers at the interfaces between an isolation zone (20) and an active zone (10) of a substrate according to the invention is advantageously strictly less than 2,000 cm / s, in particular less than or equal to 200 cm / s and more particularly less than or equal to 20 cm / s. The recombination rate of the minority charge carriers can be deduced, according to techniques known to those skilled in the art, from the measurement of the lifetime of the minority carriers according to known techniques and devices, for example based on the measurement of the photoconductivity under stationary or transient conditions, subject to taking care to take into account a possible limiting effect by the lifetime of volume. The electrical insulation zones preferably have a resistivity greater than or equal to 2 kflcm, in particular greater than or equal to 10 kflcm, still more particularly 50 kflcm. Said electrical insulation zones may have, independently of each other, a width (L2) in the plane of section ranging from 200 nm to 5 mm, in particular from 100 μm to 500 μm. Indeed, a zone of electrical insulation too long in the final silicon substrate 25 is likely to lead to a loss of active material and therefore a decrease in energy efficiency at the photovoltaic cell and module that will be formed from this substrate. On the other hand, an electrical insulation zone that is too short may be insufficient to ensure good insulation between the n and / or p doped active zones, which can also lead to a decrease in yield at the resulting PV cell. .

According to a particular embodiment, the active zones (10) of the substrate according to the invention can be arranged so as to form a two-dimensional pattern. For example, in a top view of the substrate (substrate observed in a vertical direction), the arrangement of said active areas (10) can form a checker pattern. The side of a square (active areas doped p and / or n) of the checkerboard may be between 1 mm and 10 cm, preferably between 5 mm and 5 cm. In the context of this particular embodiment, the electrical insulation zones (20) then form the perimeter of each of the active zones. This configuration is for example shown in Figure 2. Of course, the invention is not limited to such an arrangement; different configurations, allowing compact paving of the space, other than a checkerboard pattern, can be envisaged within the context of the present invention (for example rectangular patterns, polygonal, etc.). FABRICATION OF THE SUBSTRATE As mentioned above, a composite substrate (1) according to the invention can be obtained by cutting a brick having, in at least one cutting plane, a stack of active layers of p-doped and / or n-doped silicon. separated from each other by layers of electrical insulation, said brick being previously prepared, according to different embodiments, by assembling n-doped silicon wafers and / or p after creation of the intermediate layers of electrical insulation. 1 "Embodiment Reference is made in the following description of this first embodiment to the appended FIG.

According to this first variant, a silicon-based composite substrate (1) according to the invention can be obtained via at least the steps consisting of: (a) disposing wafers (110) of n-doped silicon and / or p, said slices being intended to form, by assembly and after creation of the electrical insulation layers, said desired brick (100); (b) subjecting the faces of the wafers (110) to be bonded to a surface treatment suitable for imparting a surface roughness of less than or equal to 500 nm; (c) forming, on the surface of silicon wafers treated in step (b), a silicon oxide layer (220) of thickness greater than or equal to 100 nm; (d) arranging the oxidized silicon wafers to form said desired brick (100), and assembling said wafers by gluing under conditions conducive to establishing Si-O-Si covalent bonds; and (e) cutting said brick (100) obtained at the end of the assembly of the slices in step (d), parallel to the stacking direction of the layers (110) and (220), to obtain said substrate (1 ) wish. Of course, the nature, the number and the dimensions, in particular the thickness, of the slices (or slabs) of silicon implemented in step (a) are adjusted with regard to the desired brick, and more particularly to the the structure of the substrate that it is desired to form, especially the number and size of the desired active areas. In a particular embodiment, in the case where it is desired to form a composite substrate comprising active zones of the same conductivity (n-doped or p-doped), the silicon slabs in step (a) may advantageously be derived from the cutting a brick (4) silicon (doped n or p-doped). This brick is subsequently designated as "starting brick" to distinguish it from the brick (100), called "final brick", reconstituted by assembling the slabs at the end of step (d). The n-doped or p-doped silicon starting block may be obtained by cutting a monocrystalline silicon ingot formed, according to techniques known to those skilled in the art, by directed solidification, for example by a pulling method such as such as the Czochralski or Bridgman method, or a gradient cooling method, also known as "gradient freeze" in the English language. Preferably, the silicon wafers (110) are obtained by cutting out the starting block, parallel to the ingot growth direction. Such a cutting orientation advantageously makes it possible to overcome the problems of segregation of the dopants and impurities of the ingot. Alternatively, in the case where it is desired to form a substrate having both n-doped active regions and p-doped active regions, the silicon wafers used in step (a) of the process of the invention can be from the cutting of two separate bricks of opposite electrical conductivity.

It is understood that the treatments performed on the silicon wafers in step (b) and (c), can be made only on the face (s) of the slices intended to be opposite another slice of silicon in the final brick. The surface treatment in step (b) may be more particularly carried out by polishing according to means known to those skilled in the art, for example using an abrasive based on silicon carbide particles or diamond. This treatment ensures a good flatness of the surfaces of the slices to be assembled. At the end of this surface treatment, the faces of the slices (110) intended to be assembled in the final brick advantageously have a surface roughness of less than or equal to 500 nm, in particular less than or equal to 200 nm. The surface roughness may for example be measured using a profilometer. Those skilled in the art are able to implement in step (c) techniques known to form, on the surface of the polished faces of the slices obtained at the end of step 15 (b), oxide layers of silicon (220) of desired thickness. They can be formed by subjecting the faces of the wafers to be assembled to a thermal oxidation treatment, operated for example in a thermal oven. It is within the skill of those skilled in the art to adjust the conditions of the oxidation treatment to obtain the desired oxidized layer. The oxidation treatment may for example be carried out at a temperature between 700 and 1300 ° C, in particular between 900 and 1100 ° C. The duration of the thermal oxidation treatment may be between 5 minutes and 5 hours, in particular between 30 minutes and 1 hour. Compared with the silica layers conventionally formed in the field of molecular bonding used in microelectronics (for example in the context of the production of SeOI or SOI type structures), the process of the invention uses thicknesses of greater silicon oxide, able to ensure, in the final brick, a good electrical insulation between the active layers of silicon (n-doped or p-doped silicon wafers) and therefore, at the final substrate, a good electrical insulation between 30 active areas, necessary for photovoltaic applications. In particular, the SiO 2 layers formed on the surface of the slices to be assembled may have, independently of one another, a thickness (Le) of between 100 nm and 10 μm, preferably greater than or equal to 500 nm and more particularly between 500 μm. nm and 5 pm Subsequently, the silicon wafers coated on the surface of a SiO 2 layer are designated by "oxidized" silicon wafers.

The silicon oxide layers formed according to the invention also ensure, at the level of the final brick, a good passivation of the interfaces with the active layers (n-doped or p-doped silicon wafers) and therefore, at the level of the final substrate. , good passivation at the interfaces between the active zones and the isolation zones. In the context of the process for preparing the composite substrate according to the invention, the SiO 2 layers will act as an assembly agent for the silicon wafers. In a fourth step (d) of the process of the invention, the oxidized silicon wafers are arranged to form the brick (100). According to a particular embodiment, as described in example 1 and illustrated in FIG. 3, a brick (100) can simply be (re) constituted by stacking oxidized silicon wafers on each other. The silicon wafers thus positioned, presenting in particular the layers of SiO 2 surface facing each other, are then assembled by intimate bonding, for example operated in an oven. "Intimate bonding" refers to the establishment of strong covalent bonds, not just hydrogen bonds (weaker than covalent bonds). Similarly, it is up to the general knowledge of a person skilled in the art to adjust the conditions for implementing bonding in step (d), especially in terms of temperature and duration, to ensure the establishment of strong bonds Si- O-Si. The bonding may more particularly be carried out at a temperature greater than or equal to 600 ° C., in particular between 600 ° C. and 1200 ° C. and in particular between 800 ° C. and 1000 ° C. Preferably, the intimate bonding temperature in step (d) is strictly less than 1100 ° C, in particular less than or equal to 1000 ° C and more preferably less than or equal to 900 ° C. The duration of the bonding treatment can be between 10 minutes and 2 hours, in particular between 30 minutes and 1 hour.

In the context of this first variant embodiment, the electrical insulation layers, thus established between two active layers of p-doped or n-doped silicon, are made of silicon oxide. The final brick thus obtained at the end of step (d), having in at least one cutting plane, a stack of active layers of p-doped and / or n-doped silicon separated from each other by layers of electrical insulation , is then cut, in a cutting direction parallel to the direction (I) of stacking said layers, as shown schematically in Figure 3e, to obtain the desired substrate. This cutting can be performed by any conventional method known to those skilled in the art, for example using a band saw, a diamond wire or using SiC grains as abrasives. The dimensions of the cut slice are of course chosen with regard to the dimensions of the desired silicon substrate, in particular its thickness (e) and its length (L). 2 "Embodiment Reference is made in the following description of this second embodiment to the appended FIGURE 4. According to this second variant, a silicon-based composite substrate (1) can be obtained via at least one embodiment of the invention. the steps of: (i) disposing wafers (110) of n-doped silicon and / or p, said wafers being intended to form, by assembly and after creation of the electrical insulation layers, said desired brick (100); ii) forming, on the surface of the wafers to be assembled, a layer (220) of silicon oxide having a thickness greater than or equal to 100 nm, (iii) depositing, on the surface of oxidized silicon wafers, a layer (230 ) an aqueous colloidal suspension based on silica, silicon carbide and / or silicon nitride, with an average particle size of less than or equal to 2 μm, (iv) arranging the slices thus coated at the end of the step (iii) to form said brick (100) desired, and assemble said slices by gluing under conditions conducive to the establishment of covalent bonds Si-O-Si, at a temperature greater than or equal to 1000 ° C; and (v) cutting said brick (100) obtained at the end of the assembly of the slices in step (iv), parallel to the assembly direction of the layers (110) and (220), to obtain said substrate (1 ) wish.

As detailed in the context of the first embodiment variant, the p-doped and / or n-doped silicon wafers can be obtained, prior to their implementation in step (i) of the method of the invention, by cutting one or several starting bricks. Compared to the first variant described above, this second process variant advantageously makes it possible to dispense with a step of polishing the surfaces of the starting silicon wafers. Thus, in the context of this second variant embodiment, the unpolished silicon wafers can be directly subjected to a thermal oxidation treatment in order to form, on the surface of the silicon wafers to be assembled, the thick SiO 2 layers. desired. The oxidation treatment may for example be carried out at a temperature of between 700 and 1300 ° C., in particular between 900 and 1100 ° C. The duration of the thermal oxidation treatment may be between 5 minutes and 5 hours, in particular between 30 minutes and 1 hour.

The layers of SiO 2 formed on the surface of the slices to be assembled may have, independently of one another, a thickness (Le) of between 100 nm and 10 μm, preferably a thickness greater than or equal to 500 nm and more particularly between 500 nm and 5 i.tm.

In a third step (iii) of this second process variant, oxidized silicon wafers are deposited on the surface, a layer (230) of an aqueous suspension of colloidal silica, silicon carbide or colloidal silicon nitride. The colloidal suspension more particularly has a mean particle size D50 less than or equal to 2 μm. The average particle size can be determined by Scanning Electron Microscopy.

Preferably, the average particle size of the colloidal suspension deposited on the surface of the slices is less than or equal to 1 μm, in particular less than or equal to 500 nm, and more particularly between 20 and 100 nm. According to a particularly preferred embodiment, the layers deposited in step (iii) are formed of a suspension of colloidal silica. The layers (230) of colloidal suspension deposited in step (iii) may have, independently of one another, a thickness of between 50 μm and 500 μm, in particular between 100 μm and 200 μm. The formation of colloidal suspension layers at the surface of the faces of the oxidized silicon wafers intended to be assembled advantageously makes it possible to overcome the geometric tolerances (thickness variations) inherent in the starting silicon wafers, and thus promotes their assembly. Thus, the silicon wafers thus coated are then arranged to form the brick (100), and assembled by intimate bonding.

According to a particular embodiment, as described in Example 2 and illustrated in FIG. 4, a brick (100) can simply be (re) constituted by stacking, on top of one another, the oxidized silicon wafers coated with the colloidal suspension. . It is within the skill of the person skilled in the art to adjust the conditions for implementing bonding in step (iv), especially in terms of temperature and duration, to ensure the establishment of strong Si-O-Si bonds. between two silicon wafers facing each other. The bonding step (iv) may for example be operated at a temperature between 1000 ° C and 1300 ° C. Preferably, the intimate bonding temperature in step (iv) is greater than or equal to 1100 ° C, in particular between 1100 ° C and 1200 ° C. The duration of the gluing treatment can be between 30 minutes and 4 hours, in particular between 1 hour and 2 hours. During this step (iv), the colloidal suspension layer on the surface of the slices to be assembled is sintered, which advantageously makes it possible to promote the cohesion of the insulation layer thus formed between two silicon wafers.

In the context of this second variant embodiment, the electrical insulation layers, thus established between two active p-doped or n-doped silicon layers, may be formed of a mixture of silica and silicon carbide and / or nitride. Still in the context of this second variant embodiment, the hydrostatic pressure exerted by the silicon wafers stacked on each other is liable to vary according to the height of the stack, the layers of electrical insulation (200) in the final brick formed at the end of the assembly of the slices may have varying thicknesses. Consequently, the width (L2) of the electrical insulation zones (20) in the substrate resulting from the cutting of such a brick may vary from one insulation zone to another. The inventors have however found that these variations in width were not detrimental to the electrical insulation of the sub-cells of the wafer developed from such a substrate. Alternatively, it is possible to use in step (iv) of the method of the invention, a clamping device for ensuring an identical pressure on the various interfaces of the stack, and to obtain electrical insulation layers in the final brick of substantially constant thickness. As for the first process variant, the final brick (100), thus obtained at the end of step (iv), having, in at least one cutting plane, a stack of active layers of p-doped silicon and / or dopé n separated from each other by layers of electrical insulation, is then cut, in a cutting direction parallel to the stacking direction (I) of the layers, as shown schematically in FIG. 2e, to obtain the desired substrate (1) .

Of course, the invention is not limited to the variants illustrated in Figures 3 and 4, wherein the bricks (100) are formed by simple stack of silicon wafers after creation of the intermediate layers of electrical insulation. It is understood that one skilled in the art is able to implement more complex assemblies of silicon slabs, in order to obtain, via one or other of the variants described above, the desired silicon substrates. For example, in the context of the development of a silicon substrate having active zones arranged in a two-dimensional pattern of the checker type, as mentioned above, it is understood that the silicon slabs are then assembled in two perpendicular directions. stacking to form a suitable brick that will provide such a substrate by cutting.

In another of its aspects, the invention also relates to a photovoltaic device, in particular a photovoltaic cell or a photovoltaic module, comprising at least one composite substrate based on silicon according to the invention. Those skilled in the art are able to implement the appropriate conventional treatments, for the development of a photovoltaic cell (PV), from a substrate according to the invention. A substrate according to the invention can thus be used in any type of process for producing a PV cell, for example in so-called "low temperature" heterojunction type technologies, "high temperature" homojunction type technologies. , or PV cell technologies with back contacts. A PV cell, made from a composite substrate according to the invention, is subdivided into sub-cells of smaller size. Such PV cells advantageously produce a high voltage level, while delivering less current. The PV cells obtained according to the invention can then be assembled to develop a photovoltaic module of reasonable size, typically of the order of m2, and having an increased voltage compared to modules made from conventional cells. According to yet another of its aspects, the invention thus relates to a photovoltaic module formed of a set of photovoltaic cells according to the invention. The invention will now be described by means of the following examples, given of course by way of illustration and not limitation of the invention.

EXAMPLES EXAMPLE 1 A boron-doped silicon brick (4) at 1016 atm / cm 3, of 156 × 156 mm 2 base and 250 mm high, is cut into 6 slices (110), also called "slabs" of about 25 mm wide (Figures 3a and 3b). The slabs (110) are then subjected to a grinding / polishing treatment using an abrasive based on diamond particles making it possible to lower the roughness of the faces, measured with the help of a profilometer, to a less than 200 nm (Figure 3c). The slabs thus polished are introduced into a thermal chamber to undergo a first oxidation cycle in a humid atmosphere for 2 hours at 1100 ° C. The thickness of the silicon oxide layers (220) thus formed on the surface of the slabs is about 1 μm (Figure 3d). The slabs are re-stacked one on top of the other, and placed back in the thermal chamber where they are subjected to a heat treatment of 30 minutes at 800 ° C. At the end of this treatment, the reconstituted brick (100) can be manipulated. The brick (100) obtained is then cut into wafers with a thickness of 200 μm in an industrial device (machine B5 from Applied Materials) (FIG. 3e). The wafers obtained comprise 6 active zones (10) separated from each other by electrical insulation zones (20) with a width of approximately 2 μm (FIG. 3f). EXAMPLE 2 A silicon brick (4) doped with phosphorus at 2.1015 atm / cm 3, of 156 x 156 mm 2 base and 250 mm high, is cut into 6 slices (110), also called "slabs" of about 25 mm wide (Figures 4a and 4b).

The slabs (110) are introduced into a thermal chamber to undergo a first oxidation cycle in a humid atmosphere for 2 hours at 1000 ° C. The thickness of the silicon oxide layers (220) thus formed on the surface of slabs is about 600 nm (Figure 4c). After returning to ambient temperature, a colloidal suspension based on water containing 40% by volume of silica grains of average size 100 nm is deposited on the faces of the slabs to be reassembled. The thickness of each of the layers (230) is about 250 μm (Figure 4d). The slabs are stacked on top of each other and placed back into the thermal chamber where they are subjected to a heat treatment of 1 hour at 1200 ° C. At the end of this treatment, the reconstituted brick (100) can be manipulated.

The brick obtained is cut into wafers with a thickness of 200 μm in an industrial device (machine B5 from the company Applied Materials (Figure 4e).) The wafers obtained comprise 6 active zones (10) separated from each other by zones of insulation. The widest of the isolation zones is close to 200 jam and the thinnest is close to 30 jam (Figure 4f).

References: [1] Pozner et al., Progress in Photovoltaics 20 (2012), 197; [2] Mewe et al., Silicon PV Conference, March 25-27, 2013, XIS: A Low-Current, High-Voltage Back-Junction Back-Contact Device, Energy Procedia (2013). 10

Claims (18)

REVENDICATIONS1. A silicon-based composite substrate (1) having, in a vertical section plane, active areas (10) of p-doped and / or n-doped silicon, each of the active regions extending over the entire thickness (e) of the substrate, two active zones being separated from each other by at least one electrical insulation zone (20) comprising a mass content of silicon oxide greater than or equal to 50%. 2. Substrate according to claim 1, wherein said active areas (10) have, independently of each other, a width (L1) of between 1 mm and 10 cm, in particular between 5 mm and 5 cm. 3. Substrate according to any one of the preceding claims, wherein said electrical insulation zone (20) comprises a mass content of silicon oxide greater than or equal to 75%, or is formed entirely of silicon oxide. The substrate of any of the preceding claims, wherein said electrical insulation zone (20) comprises one or more material (s) X selected from silicon carbide and silicon nitride, with a content of mass strictly less than 50%, in particular between 0 and 25%. Substrate according to any one of the preceding claims, wherein each of the electrical insulation zones (20) has a width (L2) of between 200 nm and 5 mm, in particular between 100 μm and 500 μm. Substrate according to any of the preceding claims, wherein the arrangement of said active zones (10) in the substrate, observed in a vertical direction, forms a two-dimensional pattern, in particular of a checker pattern, with the side of a square being more particularly between 1 mm and 10 cm, in particular between 5 mm and 5 cm, said electrical insulation zones forming the periphery of each of the active zones (10). 7. A process for preparing a silicon-based composite substrate (1) by cutting a brick (100) having, in at least one cutting plane, active layers (110) of p-doped silicon and / or doped n separated from each other by electrical insulation layers (200), comprising at least the steps of: (a) providing wafers (110) of n-doped silicon and / or p, said wafers being intended to form, by assembly and after creation of the electrical insulation layers, said brick (100) desired; (b) subjecting the faces of the wafers (110) to be bonded to surface treatment to provide them with a surface roughness of less than or equal to 500 nm; (c) forming, on the surface of silicon wafers treated in step (b), a silicon oxide layer (220) of thickness greater than or equal to 100 nm; (d) arranging said oxidized silicon wafers to form said desired brick (100), and bonding said wafers together under conditions conducive to establishing Si-O-Si covalent bonds; and (e) cutting said brick (100) obtained at the end of the assembly of the slices in step (d), perpendicular to the assembly planes, to obtain said desired substrate (1). 8. Method according to the preceding claim, wherein the SiO2 layers (220) are formed in step (c) by subjecting the faces of the wafers (110) to be assembled to a thermal oxidation treatment, in particular operated at a temperature between 700 ° C and 1300 ° C, especially between 900 ° C and 1100 ° C. 9. Process according to the preceding claim, wherein said thermal oxidation treatment is carried out for a period of between 5 minutes and 5 hours, in particular between 30 minutes and 1 hour. The method according to any one of claims 7 to 9, wherein the bonding in step (d) is carried out at a temperature greater than or equal to 600 ° C, in particular between 600 ° C and 1200 ° C and more. particularly between 800 ° C and 1000 ° C. 25 11. Method according to any one of claims 7 to 10, wherein the bonding step (d) is operated for a period of between 10 minutes and 2 hours, in particular between 30 minutes and 1 hour. 12. A process for preparing a silicon-based composite substrate (1) by cutting a brick (100) having, in at least one cutting plane, active layers (110) of p-doped silicon and / or or doped n separated from each other by electrical insulation layers (200), comprising at least the steps of: (i) having wafers (110) of n-doped silicon and / or p, said wafers being intended to form, by assembly and after creation of the electrical insulation layers, said brick (100) desired; (ii) forming, on the surface of the slices to be assembled, a layer (220) of silicon oxide with a thickness greater than or equal to 100 nm; (iii) depositing, on the surface of the oxidized silicon wafers to be assembled, a layer (230) of an aqueous colloidal suspension, based on silica, silicon carbide and / or silicon nitride and having a lower average particle size or equal to 2 pm (iv) arranging the slices thus coated at the end of step (iii) so as to constitute said desired brick (100), and assembling said slices by gluing at a temperature greater than or equal to 1000 ° C under conditions conducive to the establishment of covalent Si-O-Si bonds; and (v) cutting said brick (100) obtained at the end of the assembly of the slices in step (iv), perpendicular to the assembly planes, to obtain said desired substrate (1). 13. The method of claim 12, wherein said SiO2 layers (220) are formed in step (ii) by subjecting the faces of the wafers (110) to be assembled to a thermal oxidation treatment, in particular operated at a temperature of between 700 ° C and 1300 ° C, especially between 900 ° C and 1100 ° C. 14. Method according to the preceding claim, wherein said thermal oxidation treatment is operated for a period of between 5 minutes and 5 hours, in particular between 30 minutes and 1 hour. 15. A process according to any one of claims 12 to 14, wherein the layer deposited in step (iii) is formed of an aqueous suspension of colloidal silica. 16. Process according to any one of claims 12 to 15, wherein the bonding in step (iv) is carried out at a temperature of between 1000 ° C. and 1300 ° C., in particular between 1100 ° C. and 1 ° C. 200 ° C. 17. A process according to any one of claims 12 to 16, wherein the step (iv) bonding is carried out for a period of between 30 minutes and 4 hours, in particular between 1 hour and 2 hours. 18. A photovoltaic device, in particular a photovoltaic cell, comprising a silicon-based composite substrate as defined in any one of claims 1 to 6.