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FR2903524B1 - Dispositif de memoire avec commande programmable de l'activation des amplificateurs de lecture. - Google Patents

Dispositif de memoire avec commande programmable de l'activation des amplificateurs de lecture.

Info

Publication number
FR2903524B1
FR2903524B1 FR0606122A FR0606122A FR2903524B1 FR 2903524 B1 FR2903524 B1 FR 2903524B1 FR 0606122 A FR0606122 A FR 0606122A FR 0606122 A FR0606122 A FR 0606122A FR 2903524 B1 FR2903524 B1 FR 2903524B1
Authority
FR
France
Prior art keywords
activation
memory device
programmable control
reading amplifiers
amplifiers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0606122A
Other languages
English (en)
Other versions
FR2903524A1 (fr
Inventor
Francois Jacquet
Franck Genevaux
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Priority to FR0606122A priority Critical patent/FR2903524B1/fr
Priority to US11/824,948 priority patent/US7623400B2/en
Publication of FR2903524A1 publication Critical patent/FR2903524A1/fr
Application granted granted Critical
Publication of FR2903524B1 publication Critical patent/FR2903524B1/fr
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/14—Dummy cell management; Sense reference voltage generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/08—Control thereof
FR0606122A 2006-07-05 2006-07-05 Dispositif de memoire avec commande programmable de l'activation des amplificateurs de lecture. Expired - Fee Related FR2903524B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR0606122A FR2903524B1 (fr) 2006-07-05 2006-07-05 Dispositif de memoire avec commande programmable de l'activation des amplificateurs de lecture.
US11/824,948 US7623400B2 (en) 2006-07-05 2007-07-03 Memory device with programmable control for activation of read amplifiers

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0606122A FR2903524B1 (fr) 2006-07-05 2006-07-05 Dispositif de memoire avec commande programmable de l'activation des amplificateurs de lecture.

Publications (2)

Publication Number Publication Date
FR2903524A1 FR2903524A1 (fr) 2008-01-11
FR2903524B1 true FR2903524B1 (fr) 2008-10-17

Family

ID=37499620

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0606122A Expired - Fee Related FR2903524B1 (fr) 2006-07-05 2006-07-05 Dispositif de memoire avec commande programmable de l'activation des amplificateurs de lecture.

Country Status (2)

Country Link
US (1) US7623400B2 (fr)
FR (1) FR2903524B1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10283191B1 (en) * 2018-03-09 2019-05-07 Stmicroelectronics International N.V. Method and circuit for adaptive read-write operation in self-timed memory
KR20200086144A (ko) * 2019-01-08 2020-07-16 울산과학기술원 3진 메모리 셀 및 이를 포함하는 메모리 장치

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB8923037D0 (en) * 1989-10-12 1989-11-29 Inmos Ltd Timing control for a memory
US6172925B1 (en) * 1999-06-14 2001-01-09 Transmeta Corporation Memory array bitline timing circuit
US6285604B1 (en) * 2000-01-06 2001-09-04 Taiwan Semiconductor Manufacturing Co., Ltd. Dummy memory cells for high accuracy self-timing circuits in dual-port SRAM
US6181626B1 (en) * 2000-04-03 2001-01-30 Lsi Logic Corporation Self-timing circuit for semiconductor memory devices
JP4574915B2 (ja) * 2000-12-26 2010-11-04 株式会社東芝 半導体記憶回路
JP4837841B2 (ja) * 2001-06-12 2011-12-14 富士通セミコンダクター株式会社 スタティックｒａｍ
JP4894095B2 (ja) * 2001-06-15 2012-03-07 富士通セミコンダクター株式会社 半導体記憶装置
JP4152668B2 (ja) * 2002-04-30 2008-09-17 株式会社ルネサステクノロジ 半導体記憶装置
JP4408610B2 (ja) * 2002-08-09 2010-02-03 株式会社ルネサステクノロジ スタティック型半導体記憶装置
JP4439167B2 (ja) * 2002-08-30 2010-03-24 株式会社ルネサステクノロジ 半導体記憶装置
US6831853B2 (en) * 2002-11-19 2004-12-14 Taiwan Semiconductor Manufacturing Company Apparatus for cleaning a substrate
JP2004199759A (ja) * 2002-12-17 2004-07-15 Fujitsu Ltd 半導体記憶装置
JP4459527B2 (ja) * 2002-12-18 2010-04-28 パナソニック株式会社 半導体記憶装置
JP4090967B2 (ja) * 2003-08-29 2008-05-28 松下電器産業株式会社 半導体記憶装置
JP2006012240A (ja) * 2004-06-23 2006-01-12 Matsushita Electric Ind Co Ltd 半導体記憶装置およびダミーセルの回路のレイアウト

Also Published As

Publication number Publication date
US7623400B2 (en) 2009-11-24
US20080008020A1 (en) 2008-01-10
FR2903524A1 (fr) 2008-01-11

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Legal Events

Date Code Title Description
ST Notification of lapse

Effective date: 20130329