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FR2880189B1 - Procede de report d'un circuit sur un plan de masse - Google Patents

Procede de report d'un circuit sur un plan de masse

Info

Publication number
FR2880189B1
FR2880189B1 FR0453229A FR0453229A FR2880189B1 FR 2880189 B1 FR2880189 B1 FR 2880189B1 FR 0453229 A FR0453229 A FR 0453229A FR 0453229 A FR0453229 A FR 0453229A FR 2880189 B1 FR2880189 B1 FR 2880189B1
Authority
FR
France
Prior art keywords
deferring
circuit
mass plan
plan
mass
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
FR0453229A
Other languages
English (en)
Other versions
FR2880189A1 (fr
Inventor
Bernard Aspar
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tracit Technologies SA
Original Assignee
Tracit Technologies SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to FR0453229A priority Critical patent/FR2880189B1/fr
Application filed by Tracit Technologies SA filed Critical Tracit Technologies SA
Priority to CNB2005800443969A priority patent/CN100543962C/zh
Priority to PCT/FR2005/051139 priority patent/WO2006070167A1/fr
Priority to JP2007547604A priority patent/JP2008526009A/ja
Priority to US11/793,863 priority patent/US8298915B2/en
Priority to EP05848368A priority patent/EP1829100A1/fr
Priority to KR1020077013647A priority patent/KR20070086316A/ko
Publication of FR2880189A1 publication Critical patent/FR2880189A1/fr
Application granted granted Critical
Publication of FR2880189B1 publication Critical patent/FR2880189B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Thin Film Transistor (AREA)
  • Semiconductor Integrated Circuits (AREA)
FR0453229A 2004-12-24 2004-12-24 Procede de report d'un circuit sur un plan de masse Expired - Lifetime FR2880189B1 (fr)

Priority Applications (7)

Application Number Priority Date Filing Date Title
FR0453229A FR2880189B1 (fr) 2004-12-24 2004-12-24 Procede de report d'un circuit sur un plan de masse
PCT/FR2005/051139 WO2006070167A1 (fr) 2004-12-24 2005-12-22 Procede de report d'un circuit sur un plan de masse
JP2007547604A JP2008526009A (ja) 2004-12-24 2005-12-22 回路を接地面に移動する方法
US11/793,863 US8298915B2 (en) 2004-12-24 2005-12-22 Method of transferring a circuit onto a ground plane
CNB2005800443969A CN100543962C (zh) 2004-12-24 2005-12-22 将电路转移到接地层的方法
EP05848368A EP1829100A1 (fr) 2004-12-24 2005-12-22 Procede de report d'un circuit sur un plan de masse
KR1020077013647A KR20070086316A (ko) 2004-12-24 2005-12-22 접지면 상으로 회로를 전달하는 방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0453229A FR2880189B1 (fr) 2004-12-24 2004-12-24 Procede de report d'un circuit sur un plan de masse

Publications (2)

Publication Number Publication Date
FR2880189A1 FR2880189A1 (fr) 2006-06-30
FR2880189B1 true FR2880189B1 (fr) 2007-03-30

Family

ID=34954819

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0453229A Expired - Lifetime FR2880189B1 (fr) 2004-12-24 2004-12-24 Procede de report d'un circuit sur un plan de masse

Country Status (7)

Country Link
US (1) US8298915B2 (fr)
EP (1) EP1829100A1 (fr)
JP (1) JP2008526009A (fr)
KR (1) KR20070086316A (fr)
CN (1) CN100543962C (fr)
FR (1) FR2880189B1 (fr)
WO (1) WO2006070167A1 (fr)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2871291B1 (fr) * 2004-06-02 2006-12-08 Tracit Technologies Procede de transfert de plaques
US7927975B2 (en) 2009-02-04 2011-04-19 Micron Technology, Inc. Semiconductor material manufacture
FR2963159B1 (fr) * 2010-07-21 2018-01-19 Soitec Procedes de formation de structures semi-conductrices liees, et structures semi-conductrices formees par ces procedes
US8481406B2 (en) 2010-07-15 2013-07-09 Soitec Methods of forming bonded semiconductor structures
JP5847566B2 (ja) * 2011-01-14 2016-01-27 株式会社日立国際電気 半導体装置の製造方法、基板処理方法、基板処理装置およびプログラム
US8906779B2 (en) * 2012-03-30 2014-12-09 International Business Machines Corporation Solar-powered energy-autonomous silicon-on-insulator device
US8530337B1 (en) * 2012-06-22 2013-09-10 International Business Machines Corporation Method of large-area circuit layout recognition
CN104507853B (zh) 2012-07-31 2016-11-23 索泰克公司 形成半导体设备的方法
WO2014177612A1 (fr) * 2013-04-30 2014-11-06 Abb Technology Ag Procédé de fabrication d'un dispositif à semi-conducteurs comprenant une plaquette mince à semi-conducteurs
FR3049761B1 (fr) * 2016-03-31 2018-10-05 Soitec Procede de fabrication d'une structure pour former un circuit integre monolithique tridimensionnel
FR3062238A1 (fr) 2017-01-26 2018-07-27 Soitec Support pour une structure semi-conductrice

Family Cites Families (42)

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US3922705A (en) * 1973-06-04 1975-11-25 Gen Electric Dielectrically isolated integral silicon diaphram or other semiconductor product
US5849627A (en) * 1990-02-07 1998-12-15 Harris Corporation Bonded wafer processing with oxidative bonding
US5034343A (en) * 1990-03-08 1991-07-23 Harris Corporation Manufacturing ultra-thin wafer using a handle wafer
JP2621642B2 (ja) 1990-11-13 1997-06-18 日本電気株式会社 半導体装置およびその製造方法
US6627953B1 (en) * 1990-12-31 2003-09-30 Kopin Corporation High density electronic circuit modules
JP3191972B2 (ja) * 1992-01-31 2001-07-23 キヤノン株式会社 半導体基板の作製方法及び半導体基板
US5276338A (en) * 1992-05-15 1994-01-04 International Business Machines Corporation Bonded wafer structure having a buried insulation layer
US5436173A (en) * 1993-01-04 1995-07-25 Texas Instruments Incorporated Method for forming a semiconductor on insulator device
US5591678A (en) * 1993-01-19 1997-01-07 He Holdings, Inc. Process of manufacturing a microelectric device using a removable support substrate and etch-stop
US5455202A (en) * 1993-01-19 1995-10-03 Hughes Aircraft Company Method of making a microelectric device using an alternate substrate
US5426072A (en) * 1993-01-21 1995-06-20 Hughes Aircraft Company Process of manufacturing a three dimensional integrated circuit from stacked SOI wafers using a temporary silicon substrate
US5391257A (en) * 1993-12-10 1995-02-21 Rockwell International Corporation Method of transferring a thin film to an alternate substrate
JP3435930B2 (ja) * 1995-09-28 2003-08-11 株式会社デンソー 半導体装置及びその製造方法
ATE261612T1 (de) * 1996-12-18 2004-03-15 Canon Kk Vefahren zum herstellen eines halbleiterartikels unter verwendung eines substrates mit einer porösen halbleiterschicht
US6551857B2 (en) * 1997-04-04 2003-04-22 Elm Technology Corporation Three dimensional structure integrated circuits
US6191007B1 (en) * 1997-04-28 2001-02-20 Denso Corporation Method for manufacturing a semiconductor substrate
FR2767604B1 (fr) * 1997-08-19 2000-12-01 Commissariat Energie Atomique Procede de traitement pour le collage moleculaire et le decollage de deux structures
JPH11195712A (ja) * 1997-11-05 1999-07-21 Denso Corp 半導体装置およびその製造方法
US20020089016A1 (en) * 1998-07-10 2002-07-11 Jean-Pierre Joly Thin layer semi-conductor structure comprising a heat distribution layer
FR2795866B1 (fr) * 1999-06-30 2001-08-17 Commissariat Energie Atomique Procede de realisation d'une membrane mince et structure a membrane ainsi obtenue
US6482725B1 (en) * 1999-08-18 2002-11-19 Advanced Micro Devices, Inc. Gate formation method for reduced poly-depletion and boron penetration
WO2001080308A2 (fr) * 2000-04-14 2001-10-25 S.O.I.Tec Silicon On Insulator Technologies Procede pour la decoupe d'au moins une couche mince dans un substrat ou lingot, notamment en materiau(x) semi-conducteur(s)
FR2809867B1 (fr) * 2000-05-30 2003-10-24 Commissariat Energie Atomique Substrat fragilise et procede de fabrication d'un tel substrat
US6890835B1 (en) * 2000-10-19 2005-05-10 International Business Machines Corporation Layer transfer of low defect SiGe using an etch-back process
FR2840731B3 (fr) * 2002-06-11 2004-07-30 Soitec Silicon On Insulator Procede de fabrication d'un substrat comportant une couche utile en materiau semi-conducteur monocristallin de proprietes ameliorees
FR2817395B1 (fr) * 2000-11-27 2003-10-31 Soitec Silicon On Insulator Procede de fabrication d'un substrat notamment pour l'optique, l'electronique ou l'optoelectronique et substrat obtenu par ce procede
FR2823599B1 (fr) * 2001-04-13 2004-12-17 Commissariat Energie Atomique Substrat demomtable a tenue mecanique controlee et procede de realisation
FR2823596B1 (fr) 2001-04-13 2004-08-20 Commissariat Energie Atomique Substrat ou structure demontable et procede de realisation
US6759282B2 (en) * 2001-06-12 2004-07-06 International Business Machines Corporation Method and structure for buried circuits and devices
US6531753B1 (en) * 2001-06-18 2003-03-11 Advanced Micro Devices, Inc. Embedded conductor for SOI devices using a buried conductive layer/conductive plug combination
FR2830125B1 (fr) * 2001-09-24 2006-11-17 Commissariat Energie Atomique Procede de realisation d'une prise de contact en face arriere d'un composant a substrats empiles et composant equipe d'une telle prise de contact
FR2844634B1 (fr) * 2002-09-18 2005-05-27 Soitec Silicon On Insulator Formation d'une couche utile relaxee a partir d'une plaquette sans couche tampon
JP4693413B2 (ja) * 2003-01-08 2011-06-01 株式会社半導体エネルギー研究所 半導体装置の作製方法
US7436050B2 (en) * 2003-01-22 2008-10-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having a flexible printed circuit
US6911375B2 (en) * 2003-06-02 2005-06-28 International Business Machines Corporation Method of fabricating silicon devices on sapphire with wafer bonding at low temperature
FR2864336B1 (fr) * 2003-12-23 2006-04-28 Commissariat Energie Atomique Procede de scellement de deux plaques avec formation d'un contact ohmique entre celles-ci
FR2871291B1 (fr) * 2004-06-02 2006-12-08 Tracit Technologies Procede de transfert de plaques
FR2872625B1 (fr) * 2004-06-30 2006-09-22 Commissariat Energie Atomique Assemblage par adhesion moleculaire de deux substrats, l'un au moins supportant un film conducteur electrique
US7326629B2 (en) * 2004-09-10 2008-02-05 Agency For Science, Technology And Research Method of stacking thin substrates by transfer bonding
US7504277B2 (en) * 2005-10-12 2009-03-17 Raytheon Company Method for fabricating a high performance PIN focal plane structure using three handle wafers
JP4177876B2 (ja) 2007-06-11 2008-11-05 株式会社東芝 光ディスクと記録方法と再生方法と再生装置
FR2926747B1 (fr) * 2008-01-25 2011-01-14 Commissariat Energie Atomique Objet comportant un element graphique reporte sur un support et procede de realisation d'un tel objet.

Also Published As

Publication number Publication date
KR20070086316A (ko) 2007-08-27
US20080128868A1 (en) 2008-06-05
WO2006070167A1 (fr) 2006-07-06
CN100543962C (zh) 2009-09-23
JP2008526009A (ja) 2008-07-17
FR2880189A1 (fr) 2006-06-30
EP1829100A1 (fr) 2007-09-05
CN101088153A (zh) 2007-12-12
US8298915B2 (en) 2012-10-30

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