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FR2843827B1 - Recyclage mecanique d'une plaquette comprenant une couche tampon, apres y avoir preleve une couche mince - Google Patents

Recyclage mecanique d'une plaquette comprenant une couche tampon, apres y avoir preleve une couche mince

Info

Publication number
FR2843827B1
FR2843827B1 FR0210588A FR0210588A FR2843827B1 FR 2843827 B1 FR2843827 B1 FR 2843827B1 FR 0210588 A FR0210588 A FR 0210588A FR 0210588 A FR0210588 A FR 0210588A FR 2843827 B1 FR2843827 B1 FR 2843827B1
Authority
FR
France
Prior art keywords
layer
selecting
plate
stamp
mechanical recycling
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
FR0210588A
Other languages
English (en)
Other versions
FR2843827A1 (fr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to FR0210588A priority Critical patent/FR2843827B1/fr
Priority to TW92123246A priority patent/TWI322481B/zh
Priority to JP2005501224A priority patent/JP2005537685A/ja
Priority to KR1020057003368A priority patent/KR100854856B1/ko
Priority to CNB038200538A priority patent/CN100557785C/zh
Priority to EP03792598A priority patent/EP1532676A2/fr
Priority to PCT/IB2003/004029 priority patent/WO2004019403A2/fr
Priority to US10/726,039 priority patent/US7033905B2/en
Publication of FR2843827A1 publication Critical patent/FR2843827A1/fr
Application granted granted Critical
Publication of FR2843827B1 publication Critical patent/FR2843827B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02032—Preparing bulk and homogeneous wafers by reclaiming or re-processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76259—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
FR0210588A 2002-08-26 2002-08-26 Recyclage mecanique d'une plaquette comprenant une couche tampon, apres y avoir preleve une couche mince Expired - Lifetime FR2843827B1 (fr)

Priority Applications (8)

Application Number Priority Date Filing Date Title
FR0210588A FR2843827B1 (fr) 2002-08-26 2002-08-26 Recyclage mecanique d'une plaquette comprenant une couche tampon, apres y avoir preleve une couche mince
TW92123246A TWI322481B (en) 2002-08-26 2003-08-25 Mechanical recycling of a wafer comprising a buffer layer, after having taken a layer therefrom
KR1020057003368A KR100854856B1 (ko) 2002-08-26 2003-08-26 버퍼층을 포함하는 웨이퍼를 그것으로부터 층을 취한 후에기계적으로 재활용하는 방법
CNB038200538A CN100557785C (zh) 2002-08-26 2003-08-26 具有缓冲结构的晶片的再循环
JP2005501224A JP2005537685A (ja) 2002-08-26 2003-08-26 緩衝層を含むウェハから層を取り除いた後のウェハの機械的リサイクル
EP03792598A EP1532676A2 (fr) 2002-08-26 2003-08-26 Reutilisation mecanique d'une tranche comprenant une tranche tampon apres l'enlevement d'une couche de celle-ci
PCT/IB2003/004029 WO2004019403A2 (fr) 2002-08-26 2003-08-26 Reutilisation mecanique d'une tranche comprenant une tranche tampon apres l'enlevement d'une couche de celle-ci
US10/726,039 US7033905B2 (en) 2002-08-26 2003-12-01 Recycling of a wafer comprising a buffer layer after having separated a thin layer therefrom by mechanical means

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0210588A FR2843827B1 (fr) 2002-08-26 2002-08-26 Recyclage mecanique d'une plaquette comprenant une couche tampon, apres y avoir preleve une couche mince

Publications (2)

Publication Number Publication Date
FR2843827A1 FR2843827A1 (fr) 2004-02-27
FR2843827B1 true FR2843827B1 (fr) 2005-05-27

Family

ID=31198316

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0210588A Expired - Lifetime FR2843827B1 (fr) 2002-08-26 2002-08-26 Recyclage mecanique d'une plaquette comprenant une couche tampon, apres y avoir preleve une couche mince

Country Status (2)

Country Link
FR (1) FR2843827B1 (fr)
TW (1) TWI322481B (fr)

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0926709A3 (fr) * 1997-12-26 2000-08-30 Canon Kabushiki Kaisha Méthode de fabrication d'une structure SOI
JP3500063B2 (ja) * 1998-04-23 2004-02-23 信越半導体株式会社 剥離ウエーハを再利用する方法および再利用に供されるシリコンウエーハ
JP2000349266A (ja) * 1999-03-26 2000-12-15 Canon Inc 半導体部材の製造方法、半導体基体の利用方法、半導体部材の製造システム、半導体部材の生産管理方法及び堆積膜形成装置の利用方法
US6326279B1 (en) * 1999-03-26 2001-12-04 Canon Kabushiki Kaisha Process for producing semiconductor article
EP1212787B1 (fr) * 1999-08-10 2014-10-08 Silicon Genesis Corporation Procede de clivage permettant de fabriquer des substrats multicouche a l'aide de faibles doses d'implantation
JP2004507084A (ja) * 2000-08-16 2004-03-04 マサチューセッツ　インスティテュート　オブ　テクノロジー グレーデッドエピタキシャル成長を用いた半導体品の製造プロセス

Also Published As

Publication number Publication date
FR2843827A1 (fr) 2004-02-27
TW200411821A (en) 2004-07-01
TWI322481B (en) 2010-03-21

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Owner name: SOITEC, FR

Effective date: 20120423

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