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FR2842651B1 - Procede de lissage du contour d'une couche utile de materiau reportee sur un substrat support - Google Patents

Procede de lissage du contour d'une couche utile de materiau reportee sur un substrat support

Info

Publication number
FR2842651B1
FR2842651B1 FR0209022A FR0209022A FR2842651B1 FR 2842651 B1 FR2842651 B1 FR 2842651B1 FR 0209022 A FR0209022 A FR 0209022A FR 0209022 A FR0209022 A FR 0209022A FR 2842651 B1 FR2842651 B1 FR 2842651B1
Authority
FR
France
Prior art keywords
smoothing
contour
support substrate
useful layer
material reflected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
FR0209022A
Other languages
English (en)
Other versions
FR2842651A1 (fr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to FR0209022A priority Critical patent/FR2842651B1/fr
Priority to US10/617,521 priority patent/US6958284B2/en
Priority to EP09178890A priority patent/EP2164096B1/fr
Priority to PCT/EP2003/007852 priority patent/WO2004008525A1/fr
Priority to AT03763889T priority patent/ATE482468T1/de
Priority to DE60334300T priority patent/DE60334300D1/de
Priority to TW092119454A priority patent/TWI273645B/zh
Priority to EP09178893A priority patent/EP2164097B1/fr
Priority to AU2003250107A priority patent/AU2003250107A1/en
Priority to JP2005505072A priority patent/JP4368851B2/ja
Priority to EP03763889A priority patent/EP1523773B1/fr
Publication of FR2842651A1 publication Critical patent/FR2842651A1/fr
Priority to US11/153,955 priority patent/US20050233544A1/en
Application granted granted Critical
Publication of FR2842651B1 publication Critical patent/FR2842651B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76259—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Recrystallisation Techniques (AREA)
FR0209022A 2002-07-17 2002-07-17 Procede de lissage du contour d'une couche utile de materiau reportee sur un substrat support Expired - Lifetime FR2842651B1 (fr)

Priority Applications (12)

Application Number Priority Date Filing Date Title
FR0209022A FR2842651B1 (fr) 2002-07-17 2002-07-17 Procede de lissage du contour d'une couche utile de materiau reportee sur un substrat support
US10/617,521 US6958284B2 (en) 2002-07-17 2003-07-11 Method of smoothing the outline of a useful layer of material transferred onto a support substrate
JP2005505072A JP4368851B2 (ja) 2002-07-17 2003-07-16 支持基板へ転送される有用な材料層の輪郭を平坦にする方法
AT03763889T ATE482468T1 (de) 2002-07-17 2003-07-16 Verfahren zur glättung des umrisses einer auf ein stützsubstrat übertragenen nutschicht
DE60334300T DE60334300D1 (de) 2002-07-17 2003-07-16 Verfahren zur glättung des umrisses einer auf ein stützsubstrat übertragenen nutschicht
TW092119454A TWI273645B (en) 2002-07-17 2003-07-16 Method of smoothing the outline of a useful layer of material transferred onto a support substrate
EP09178890A EP2164096B1 (fr) 2002-07-17 2003-07-16 Procédé de lissage de la silhouette d'une couche de matériau utile transférée sur un substrat support
AU2003250107A AU2003250107A1 (en) 2002-07-17 2003-07-16 Method of smoothing the outline of a useful layer of material transferred onto a support substrate
PCT/EP2003/007852 WO2004008525A1 (fr) 2002-07-17 2003-07-16 Procede de lissage du contour d'une couche de materiau utile transferee sur un substrat de support
EP03763889A EP1523773B1 (fr) 2002-07-17 2003-07-16 Procede de lissage du contour d'une couche de materiau utile transferee sur un substrat de support
EP09178893A EP2164097B1 (fr) 2002-07-17 2003-07-16 Procédé de lissage de la silhouette d'une couche de matériau utile transférée sur un substrat support
US11/153,955 US20050233544A1 (en) 2002-07-17 2005-06-15 Method of smoothing the outline of a useful layer of material transferred onto a support substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0209022A FR2842651B1 (fr) 2002-07-17 2002-07-17 Procede de lissage du contour d'une couche utile de materiau reportee sur un substrat support

Publications (2)

Publication Number Publication Date
FR2842651A1 FR2842651A1 (fr) 2004-01-23
FR2842651B1 true FR2842651B1 (fr) 2005-07-08

Family

ID=29797487

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0209022A Expired - Lifetime FR2842651B1 (fr) 2002-07-17 2002-07-17 Procede de lissage du contour d'une couche utile de materiau reportee sur un substrat support

Country Status (2)

Country Link
US (2) US6958284B2 (fr)
FR (1) FR2842651B1 (fr)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6912330B2 (en) * 2001-05-17 2005-06-28 Sioptical Inc. Integrated optical/electronic circuits and associated methods of simultaneous generation thereof
FR2856192B1 (fr) * 2003-06-11 2005-07-29 Soitec Silicon On Insulator Procede de realisation de structure heterogene et structure obtenue par un tel procede
US7364432B2 (en) * 2004-03-31 2008-04-29 Drb Lit Ltd. Methods of selecting Lock-In Training courses and sessions
WO2007017763A2 (fr) * 2005-07-08 2007-02-15 S.O.I. Tec Silicon On Insulator Technologies Procede servant a produire une couche
FR2888400B1 (fr) * 2005-07-08 2007-10-19 Soitec Silicon On Insulator Procede de prelevement de couche
WO2007105405A1 (fr) * 2006-03-10 2007-09-20 Matsushita Electric Industrial Co., Ltd. Procede et dispositif de montage d'un organe de forme anisotrope, procede de fabrication d'un dispositif electronique, dispositif electronique, et affichage
US20070264796A1 (en) * 2006-05-12 2007-11-15 Stocker Mark A Method for forming a semiconductor on insulator structure
EP1993128A3 (fr) 2007-05-17 2010-03-24 Semiconductor Energy Laboratory Co., Ltd. Procédé de fabrication d'un substrat SOI
FR2917232B1 (fr) * 2007-06-06 2009-10-09 Soitec Silicon On Insulator Procede de fabrication d'une structure pour epitaxie sans zone d'exclusion.
CN101743616B (zh) * 2007-06-28 2012-02-22 株式会社半导体能源研究所 半导体装置的制造方法
US8431451B2 (en) 2007-06-29 2013-04-30 Semicondutor Energy Laboratory Co., Ltd. Display device and method for manufacturing the same
JP5507063B2 (ja) 2007-07-09 2014-05-28 株式会社半導体エネルギー研究所 半導体装置の作製方法
KR20090093074A (ko) * 2008-02-28 2009-09-02 삼성전자주식회사 Ｓｏｉ 웨이퍼의 제조 방법
US7927975B2 (en) 2009-02-04 2011-04-19 Micron Technology, Inc. Semiconductor material manufacture
FR3036223B1 (fr) * 2015-05-11 2018-05-25 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede de collage direct de substrats avec amincissement des bords d'au moins un des deux substrats
CN117133637B (zh) * 2023-10-26 2024-04-02 青禾晶元(天津)半导体材料有限公司 提升碳化硅复合衬底有效面积的方法及碳化硅复合衬底

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0636413B2 (ja) 1990-03-29 1994-05-11 信越半導体株式会社 半導体素子形成用基板の製造方法
US5597410A (en) 1994-09-15 1997-01-28 Yen; Yung C. Method to make a SOI wafer for IC manufacturing
EP0935280B1 (fr) * 1998-02-04 2004-06-09 Canon Kabushiki Kaisha Substrat SOI
US6093623A (en) 1998-08-04 2000-07-25 Micron Technology, Inc. Methods for making silicon-on-insulator structures
US6664169B1 (en) * 1999-06-08 2003-12-16 Canon Kabushiki Kaisha Process for producing semiconductor member, process for producing solar cell, and anodizing apparatus
JP4846915B2 (ja) * 2000-03-29 2011-12-28 信越半導体株式会社 貼り合わせウェーハの製造方法
EP1189266B1 (fr) * 2000-03-29 2017-04-05 Shin-Etsu Handotai Co., Ltd. Procede d'obtention de tranches de silicium ou de soi et tranches ainsi obtenues
JP2001284622A (ja) * 2000-03-31 2001-10-12 Canon Inc 半導体部材の製造方法及び太陽電池の製造方法

Also Published As

Publication number Publication date
US6958284B2 (en) 2005-10-25
US20050233544A1 (en) 2005-10-20
FR2842651A1 (fr) 2004-01-23
US20040121557A1 (en) 2004-06-24

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Owner name: SOITEC, FR

Effective date: 20120423

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