FR2786292A1 - Test and personalization of integrated circuits used in smart cards has memory accessible in reading to the test processor, a decoder, storage for personalization key and a device to encode - Google Patents

Abstract

The integrated circuit test station (STST) has a memory (SMEM) accessible in reading to the test processor, a decoder (DCD2) for a personalization key that has been encoded with a session key (RK), a storage (KREG1) for the personalization key, and a device (CD1) to encode, using the personalization key, personalization data (PDk) delivered by the test processor.

Description

TEST AND CUSTOMIZATION SYSTEM
INTEGRATED CIRCUITS
The present invention relates to a test and personalization system for integrated circuits, in particular integrated circuits for smart cards. The present invention relates more particularly to a test system comprising a test and personalization station for integrated circuits and a centralizer for test and personalization data.

 The manufacture of smart cards and more generally the manufacture of portable objects comprising an electronic chip is a complex process comprising various stages, among which a distinction is made: a stage of collective manufacture of integrated circuits on a silicon wafer ( "wafer"), -an electrical test step of the integrated circuits, -a first step of customizing the integrated circuits, -a step of cutting the silicon wafer, -a step of insertion on a support of the individualized integrated circuits, called inserting step in the case of smart cards, -a second step of personalizing the integrated circuits,-possibly, a third and last step of personalizing the integrated circuits, carried out by the client (client) before placing on the market for portable electronic objects.

 At the end of the production line, the stages of testing and first personalization of the integrated circuits are carried out simultaneously, by means of a test and personalization system of the type shown in FIG. 1, comprising a connected TST1 test station via an NTWK computer network to a TCT centralizer for test and personalization data.

 A general objective of the present invention is to improve such a system, the structure and operation of which will be recalled before describing the drawbacks thereof.

 Conventionally, the test station TST1 comprises a central unit CPU1 and a test processor TPR. The TPR processor is connected to a plurality of integrated circuits IC present on a silicon wafer, via a PCB tip card and a WFG interface circuit ensuring the shaping of the electrical signals applied to the circuits. integrated. In Figure 1, a single integrated circuit IC is shown for the sake of simplicity. It can be seen that the integrated circuit IC comprises a central unit ICPU, a random access memory RAM, a read-only memory ROM (programmed at the manufacturing stage) and an electrically erasable programmable EEPROM memory.

The central unit CPU1, connected to the network, is equipped with a unit HD1 for storing data in which a test program TPGa is recorded, and a memory MEM of RAM type which can be read by the test processor TPR, in which DTa application data are loaded. In addition, the TPR test processor is equipped with a VMEM program memory in which there is a VPGa test program, composed of test vectors and forming the operating system ("Operating
System ") of the test processor. The program VPGa is extracted from the program TPGa by the unit CPU1 and is loaded by the latter into the memory VMEM.

The program TPGa and the data DTa are supplied by the centralizer TCT, via the network, on receipt of a request from the unit CPU1 specifying the application and the type of integrated circuit to be tested and personalized. By "application" is meant the final destination of the integrated circuits IC, that is to say the use for which they are intended. The DTa data are for example program sequences, variables, codes, etc. specific to the intended application, which must be loaded into the memory.
EEPROM of integrated circuits. On the centralizer side
TCT, there is thus a central unit CPU2 connected to the network, and storage units HD2, HD3 respectively comprising a set DT of application data DTa, and a set TPG of test programs TPGa.

 The first stage of personalization of the integrated circuits mentioned above is carried out by the TPR processor in parallel with the electrical test of the integrated circuits.

This step consists in recording in the EEPROM memory of each integrated circuit: the application data DTa, common to all the integrated circuits of the same batch, a batch generally representing one or more silicon wafers, ie several hundreds or thousands of integrated circuits intended for the same application, -a personalization data PDk, for example a random data or a serial number calculated from various parameters such as the date and time of the test, the serial number of the batch, the test station number, integrated circuit number ...

a personalization code PCk of the type PCk = FPKa (PDk), obtained by coding the personalization data PDk by means of a cryptography function FpKa using as key cryptography a key PKa called "personalization key".

Typically, personalization data
PDk are issued by the TPR test processor while the PCk code calculation, for each PDk personalization data, is ensured by a BBX converter supplied by the client, including cryptography functions. It is generally a microcomputer without screen or keyboard connected to the CPU1 unit by a serial link SL. The BBX converter is connected to a smart card reader RD into which is introduced a CRDa card chosen, depending on the intended application, from a set of CRDi cards supplied by the customer. The CRDa card includes a PKa personalization key and can also include all or part of the cryptography functions used by the BBX converter.

Thus, the personalization stage proper is preceded by a preparatory stage during which the TPR processor delivers N personalization data PDk for N integrated circuits IC present on a silicon wafer, "k" being an index ranging from 1 to N. The data
PDk are loaded into the memory MEM then are read by the unit CPU1 which sends them to the converter BBX by specifying the application intended for the batch of integrated circuits to be personalized. The converter BBX calculates the codes PCk and sends them back to the unit CPU1 which stores them in the memory MEM.

 At the end of the preparatory step, the memory MEM comprises the application data DTa and a table comprising N pairs PDk / PCk of data PDk and codes PCk.

The processor TPR can then begin to test the integrated circuits, and loads into the EEPROM memory of each integrated circuit tested the common data DTa, a personalization data PDket the corresponding code PCk.

 As mentioned above, such a test and personalization system has various drawbacks. On the one hand, due to the large manufacturing volumes of integrated circuits, it is usual for a large number of test stations TST1, TST2, TST3 ... TSTn to be connected to the same network. Although these stations are located in premises with controlled access, many people are led to use them and it can be considered that the security conditions are not optimal. In particular, the application data DTa, the personalization data PDk and the personalization codes PCk temporarily stored in the memory MEM are confidential data exposed to a risk of computer hacking by violation of the integrity of the CPU unit from the network.

 Thus, a first objective of the present invention is to improve the security of a test station connected to a computer network.

On the other hand, the calculation of personalization codes
PCk by a customer-supplied converter is an impractical aspect of conventional test and personalization systems, which require as many converters as test stations and as many converters per test station as customers, which represents a large fleet converters and involves various maintenance issues.

In addition, a silicon wafer comprising several hundred integrated circuits, the calculation of a high number of personalization codes by the converter generally requires a fairly long time, of the order of several minutes, or a significant wait before d '' initiate the actual test and personalization operation.

 Thus, another objective of the present invention is to provide a test and personalization system for integrated circuits which is simpler and more rational than known systems while being faster and safer.

 These objectives are achieved by providing a test and personalization station comprising a central unit capable of being connected via a computer network to a data centralizer, a test and personalization processor for integrated circuits. arranged to record in at least one integrated circuit personalization data and a personalization code, the personalization code being a function of the personalization data and of a personalization key, a memory accessible in reading to the test processor and inaccessible by reading at the central unit, means for decoding, by means of a decoding key inaccessible to the central unit, at least one personalization key received in coded form via the network, storage means for the personalization key, inaccessible for reading from the central unit, means for coding by means of the personalization key n personalization data, and deliver a personalization code inaccessible to the central unit, and means for recording the personalization code in the memory.

 According to one embodiment, the test processor is arranged to record in an integrated circuit application data received via the network, and the station comprises means for decoding, by means of a decoding key inaccessible to the central unit, application data received in coded form, and recording the application data in the memory, the output of the means for decoding the application data being inaccessible to the central unit.

 According to one embodiment, the station comprises means for delivering a session key intended to be used as a coding key for data sent to the station, and means for sending the session key over the network.

 According to one embodiment, the session key is a private key and the station comprises means for coding the session key using a logon key, and sending the coded session key over the network, and means for storing the session key which cannot be read from the central unit.

 According to one embodiment, the station comprises a key memory inaccessible to the central unit, comprising a plurality of prerecorded logon keys, means for selecting and reading a logon key from the key memory according to a selection parameter, and means for sending the selection parameter of the logon key over the network.

 The present invention also relates to a centralizer for test and personalization data for integrated circuits, comprising a central unit capable of being connected via a computer network to at least one test and personalization station for integrated circuits, means for reading at least one personalization key for integrated circuits on a data carrier, and means for storing the personalization key.

 According to one embodiment, the centralizer comprises means for coding a personalization key using a session key and sending the coded personalization key over the network.

 According to one embodiment, the session key is a private key and the centralizer comprises means for storing the session key which are inaccessible for reading from the central unit.

 According to one embodiment, the centralizer comprises a first key memory inaccessible to the central unit, means for recording in the first key memory a plurality of personalization keys for integrated circuits delivered by the means for reading a medium. data, means for selecting and reading a personalization key in the first memory.

 According to one embodiment, the centralizer comprises a second key memory inaccessible to the central unit, comprising a plurality of prerecorded logon keys, means for selecting and reading a logon key from the second memory keys as a function of a selection parameter, and means for decoding, by means of a logon key, a session key received in an encoded form by the central unit.

These characteristics and the advantages of the present invention will be explained in more detail in the following description of a test system comprising a test station and a data centralizer according to the invention, in relation to the attached figures among which:
FIG. 1 previously described represents in the form of blocks the general architecture of a conventional test system,
FIG. 2 represents in the form of blocks the architecture of a test system according to the invention, comprising a data centralizer and a test and personalization station,
FIG. 3 represents a non-limiting example of an embodiment of two circuits represented in the form of a block in FIG. 2, and
FIG. 4 represents a non-limiting example of an embodiment of two other circuits represented in the form of a block in FIG. 2.

 FIG. 2 represents the general architecture of a test and personalization system according to the invention, comprising a secure test station STST connected by a computer network NTWK to a secure centralizer STCT.

We find in the station STST elements already described in the preamble, designated by the same references, namely a central unit CPU1, an HD1 unit for storing a test program TPGa supplied by the centralizer STCT, a test processor TPR, a VMEM program memory into which are loaded VPGa test vectors, an electrical interface WFG and a PCB tip card allowing access to integrated circuits IC present on a silicon wafer. Likewise, there is in the centralizer STCT a central unit CPU2, a unit HD2 for storing a set DT of application data DTa, and a unit HD3 for storing a set TPG of test programs TPGa.

According to the invention, the station STST comprises a secure memory SMEM of RAM type, inaccessible for reading from the CPU1 unit but accessible for reading from the processor
TPR. This memory SMEM is write-accessible to the processor TPR via a buffer circuit BUF1 comprising an encoder circuit CD1 of the cryptographic type, using as personalization key the personalization key PKa already described in the preamble, stored in an inaccessible register KREG1 to the CPUl unit. The coder CD1 is for example a cryptography circuit with a private key of the "3DES" type, capable of transforming personalization data PDk delivered by the TPR processor into a personalization code PCk of the type:
PCk = FpKa (PDk)
At the output of the encoder CD1, the code PCk is recorded in the memory SMEM and can then be read by the processor TPR. The coder CD1 thus advantageously replaces the conventional converters connected to the unit CPU1 by a serial link, which require, before the start of the test and personalization process, the development of a table containing personalization data PDket of the codes PCk customization.

In addition, the arrangement of the encoder CD1 at the input of the memory SMEM allows the determination in real time of a personalization code PCk, during the test of an integrated circuit. Thus, according to a preferred embodiment of the invention, the processor TPR sends to the coder CD1 a datum PDk for personalizing an integrated circuit when the integrated circuit is to be tested, reads the corresponding code PCk in the memory SMEM when the integrated circuit test is completed, and stores the data PDk and the PCk code in the integrated circuit before starting the next integrated circuit test. If several integrated circuits are tested simultaneously, the TPR processor sends several personalization data one after the other to the encoder CD1, during the test of the integrated circuits. Thanks to this real-time operating mode, the time for developing PCk personalization codes covers the test periods and does not cause any waiting or loss of time. Thus, in practice, the use of a 3DES coder having a calculation time of the order of 50 to 80 ms makes it possible to test 24 integrated circuits simultaneously while calculating 24 personalization codes PCk. In addition, the PCk codes temporarily stored in the memory
SMEM are inaccessible to the CPU1 unit, so that a violation of the CPU1 unit from the network cannot allow access to these codes.

Furthermore, according to an optional but advantageous aspect of the present invention, the personalization key PKa is sent by the centralizer STCT in a form coded by a session key RK, instead of being supplied by a smart card reader as in the prior art (see fig. 1). By "session key" RK, here is meant a cryptography key held by the station
STST and the STCT centralizer, making it possible to transfer data over the network in a secure manner during a session, that is to say a computer connection between the two elements. Thus, according to this aspect of the invention, the circuit BUF1 comprises a decoding circuit DCD2, for example a "3DES" decoder, using as decoding key the session key RK stored in a register KREG2 inaccessible to the unit CPU1. The CPU1 unit receives via the network the PKa personalization key in the following coded form: and transfers the coded PKa key to the input of the DCD2 decoder, the output of which is connected to the input of the KREG1 register.

The PKa key, once decoded, is stored in the registry
KREG1.

 Furthermore, according to yet another optional but advantageous aspect of the present invention, the application data DTa sent by the centralizer STCT are coded by means of the session key RK, and are recorded in the memory SMEM instead of being stored in a memory accessible to the CPU1 unit.

In this case, the unit CPU1 sends the encoded data DTa to the input of the decoder DCD2 and the output of the decoder DCD2 is applied to the input of the memory SMEM, for the recording of the decoded data DTa. Thus, here, the SMEM memory is used both as a data buffer for the temporary storage of the personalization codes
PCk, and as a means of transferring data DTa between the unit CPU1 and the processor TPR.

 FIG. 3 represents a non-limiting example of an embodiment of the buffer circuit BUF1 implementing the three aspects of the invention described above.

The circuit BUF1 has a data input INDT and a control input INCMD connected to the unit CPU1 and to the processor TPR. The data path inside the circuit BUF1 is controlled by switches Il, 12, I3 of the multiplexer or demultiplexer type, having an input E and two outputs Sl, S2 or two inputs El, E2 and an output S. The various elements of the circuit BUF1 are controlled by a sequencer SEQ1 synchronized by a clock signal H, receiving commands CMD via the input INCMD. These commands, of the type [CoP, ADR], include a Cop operation code and an ADR address. The sequencer delivers a switch control signal SI, a memory selection signal SEL
SMEM or of a register KREG1, KREG2, an R / W signal for reading / writing from the memory SMEM or writing of a register KREG1, KREG2, as well as a write or read address ADR. The switches Il to I3 are arranged to ensure the following connections: the connection of the input INDT to the input of the encoder CD1 and the connection of the output of the encoder CD1 to the input of the memory SMEM, for the transformation of '' PDk data into a PCk code and saving it in memory
SMEM, -connection of the input INDT to the input of the DCD2 decoder and the connection of the output of the DCD2 decoder to the input of the KREG1 register, for the decoding and storage of the PKa personalization key, -the connection from the input INDT to the input of the decoder DCD2 and the connection of the output of the decoder DCD2 to the input of the memory SMEM, for the decoding and the storage of the data DTa.

Furthermore, as illustrated in FIG. 2, the STCT centralizer is equipped with a smart card reader RD of the type arranged in the prior art near the test stations (cf. fig. 1). According to the invention, various CRD cards supplied by one or more customers are successively inserted into the RD reader, each containing a PKi personalization key. Personalization keys
PKi delivered by CRDi cards are stored in a KMEM key memory which cannot be read individually
CPU2. KMEM memory is arranged in a buffer circuit
BUF2 comprising an encoder CD10 using as cryptographic key the session key RK mentioned above, stored in a register KREG10. Memory output
KMEM is sent to the input of the CD10 encoder, and the output of the CD10 encoder forms the output of the BUF2 circuit.

 Thus, according to the invention, a plurality of personalization keys PKi is stored in the KMEM memory.

When a test station wishes to have a particular PKa key for the personalization of a batch of integrated circuits, the requested PKa key is selected by the unit CPU1 in the memory KMEM. The unit CPU1 receives the key PKa via the encoder CD10, that is to say in a form coded by the session key RK, and sends it over the network in this form. At the test station, the key PKa is decoded by the circuit BUF1 according to the invention, as described above. Thus, a spy on the network or a violation of the CPU2 unit cannot allow access to the personalization key PKa, as well as to the other PKi keys stored in the memory KMEM. In addition, PKi personalization keys can be sent to an unlimited number of test stations connected to the centralizer via the network. Ultimately, such an arrangement of the RD reader in combination with the elimination of conventional converters at the level of the test stations considerably simplifies the system according to the invention, and solves the maintenance problems encountered in the prior art while offering optimum security. against a possible attempt to breach the system.

Furthermore, optionally but advantageously, the application data DTa selected in the unit
HD2 are also sent to the CPU2 unit via the CD10 encoder, and transit over the network in a secure manner.

FIG. 4 illustrates, without limitation, an exemplary embodiment of the circuit BUF2, in which the personalization keys PKi delivered by the reader RD are stored in the memory KMEM in an encoded form, for security reasons. The BUF2 circuit includes a data input INDT1 connected to the reader RD, not accessible to the unit CPU2, a hardware data input
INHR not accessible to the CPU2 unit, a data entry
INDT2 connected to the HD2 unit and the CPU2 unit, one output
OUT connected to the CPU2 unit and a control input
INCMD also connected to the CPU2 unit. The BUF2 circuit also includes a CD11 coder and a DCD12 decoder using a master key as the coding or decoding key.
MK1 stored in a register KREG11, accessible in writing by the entry INHR. The data path inside the BUF2 circuit is controlled by various multiplexer or demultiplexer switches I10 to 115. The various elements of the BUF2 circuit are controlled by a sequencer
SEQ2, receiving from the CPU2 unit a clock signal H and CMD commands of the type [Cop, ADR], comprising an operation code and an address. The sequencer SEQ2 delivers a signal SEL for selecting one of the registers KREG10, KREG11 or from the memory KMEM, a signal R / W for writing the registers KREG10, KREG11 or for reading / writing from the memory KMEM, a signal SI switch control
I10 to 115, and an ADR address for reading or writing. The switches I10 to 115 are arranged to provide the following connections: the connection of the input INDT1 to the input of the encoder CD11 and the connection of the output of the encoder CD11 to the input of the memory KMEM, for the coding of the PKi personalization keys issued by the RD reader and their loading into the KMEM memory, the connection of the output of the KMEM memory to the input of the DCD12 decoder and the connection of the decoder output
DCD12 at the input of the CD10 encoder, for reading a key
PKa coded by the MK1 key to an ADRa address in the memory
KMEM given by a CMD command, the decoding of the PKa key and its coding by means of the RK key before it is sent to the network via the CPU2 unit, and the connection of the INDT2 input to the input of the encoder CD10, for the coding by means of the key RK of the application data DTa delivered by the unit HD2, before their sending on the network by the unit CPU2.

 We will now describe a method according to the invention allowing the station STST and the centralizer STCT to use a common session key RK, of random value, renewed at each new session.

According to the invention, the station STST comprises a session initialization circuit INIT1 arranged to generate a session key RK and deliver this key in an encoded form. The unit CPU1 is arranged to send the coded session key RK to the centralizer, and the centralizer STCT includes an initialization circuit
INIT2 designed to decode the RK session key and place it in the KREG10 register.

The circuit INIT1, shown in FIG. 3, is controlled by the sequencer SEQ1 of the circuit BUF1 and includes a hardware input INHR, an output OUT connected to the unit CPUl, a memory IMEM1 of the EEPROM type, encoders
CD3 and CD5 and a DCD4 decoder. The coder CD3 and the decoder DCD4 receive a coding or decoding key stored in a register KREG3, and the coder CD5 receives a coding key stored in a register KREG4. The circuit
INIT1 also includes a random key generator
RGEN, whose output is connected to the registry entries
KREG2 and the CD5 encoder. The INHR input is connected to the inputs of the KREG3 register and the CD3 encoder. The output of the encoder CD3 is connected to the input of the memory IMEM1, the output of which is connected to the input of the decoder DCD4.

The output of the DCD4 decoder is applied to the input of the KREG4 register. The output of the encoder CD5 forms the output OUT of the circuit INIT1.

 Before being put into service, the INIT1 circuit is previously configured from its INHR input, which is not accessible to the CPU1 unit. This step consists in loading into the register KREG3 a master key MK2, and in recording in the memory IMEM1, via the encoder CD3, a table of session initialization keys IKj comprising for example "m" keys, "j "being an index ranging from 1 to m. The IKj keys are thus stored in a form coded by the master key MK2, this for security reasons.

 When the unit CPU1 decides to establish a communication with the centralizer STCT, for example to request the sending of a test program TPGa, of application data DTa and of a personalization key PKa, the unit CPU1 randomly chooses a value "x" between 1 and m, and applies to the sequencer SEQ1 a command of the type [CINIT, ADRx], which means: "initialize a session with a key IKj = x of address ADRx present in the IMEM1 memory ". The sequencer SEQ1 then selects the key IKX in the memory IMEM1, decodes the key IKX by means of the decoder DCD4 and stores it in the register KREG4.

Then, the sequencer SEQ1 activates the random generator
RGEN which issues an RK session key. The key RK is, on the one hand, stored in the register KREG2 of the circuit BUF1 and, on the other hand, coded by the coder CD5 by means of the session opening key IKx. The FIKX coded session key (RK) is found on the OUT output of the circuit INIT1 and is read by the CPU1 unit. CPU1 sends a session initialization message to the STCT centralizer
IMESS of type:
IMESS = [INIT, FiKx (RK), ADRx] including an INIT session initialization request, the encoded RK session key as well as the ADDx address or equivalent "x" parameter giving the rank of the initialization key IKx in IMEM1 memory.

We now see with reference to FIG. 4 that the circuit INIT2 of the centralizer STCT comprises a memory IMEM2 similar to the memory IMEM1, as well as a decoder DCD13 receiving a decoding key contained in a register KREG12. Before commissioning the circuit
INIT2, IMEM2 memory is configured by means of the input
INHR of circuit BUF2. IKj session initialization keys, identical to the IKj keys of the circuit INIT1, are sent to the input of the coder COD11 via the switch Ill. The output of the encoder CD11 is applied to the input of the memory IMEM2 via the switch I12. At the end of the operation, the memory IMEM2 contains the session key table IKj already described, the keys IKj being here coded by the master key MK1.

Thus, when the unit CPU2 receives the message IMESS, it sends to the input INDT2 of the circuit BUF2 the coded session key FIKX (RK) and applies to the sequencer SEQ2 a CMD command of the type [CINIT, ADRx], which means: "decode the value presented on the INDT entry using the key
IKX of rank x ". The sequencer then selects the coded key IKx in the memory IMEM2, connects the output of the memory IMEM2 to the input of the decoder DCD12 by means of switch 113, connects the output of the decoder DCD12 to the input of the register KREG12 by means of the switch 114, and connects the input INDT2 of the circuit BUF2 to the input of the decoder DCD13, by means of the switches I10, 115. The output of the decoder DCD12 delivers the key IKx which is stored in the register KREG12 of the decoder DCD13 The decoder DCD13 decodes the coded session key FiKx (RK) The key RK is stored in the register KREG10, for the subsequent coding of the personalization key PKa and of the application data DTa .

 It will be clear to a person skilled in the art that the present invention is capable of various variants and embodiments. In particular, the coders or decoders present in the circuits BUF1, BUF2, INIT1, INIT2 have been presented as separate elements to facilitate understanding of the invention. In practice, it is conceivable to produce these coders or decoders by means of a single coder / decoder circuit arranged to receive several coding or decoding keys, provided that the conditions of non-accessibility of the data to be coded or of coding are respected.

 On the other hand, it has been proposed in the above to use cryptography circuits with a private key of the "3DES" type which have the advantage of being fast. However, it is within the scope of the invention to provide other cryptography circuits, in particular public key circuits of the RSA type. In this case, the transfer of secure data over the network does not require the provision of an RK session key known to the station and to the centralizer. Thus, according to one embodiment, the test station generates its own private key PRVK and provides the centralizer with a public key PUBK which acts as the session key RK. The PUBK public key allows the centralizer to encode the data it sends over the network. Only the station, which knows the private key PRVK, can decode this data. The private key PRVK is issued by an RSA type calculation block to be stored in the register KREG2 (FIGS. 2 and 3) and is not accessible to the central unit or to the user of the test station.

In this case, the station and the centralizer operate as master-slave, the centralizer not knowing the PRVK private key. Furthermore, according to a variant, the public key PUBK is used to encode the personalization keys PKi stored in the memory KMEM, and acts as the master key MK1. According to yet another variant, the personalization keys PKi are delivered directly by the cards CRDi in a form coded by the public key PUBK. In this case, the public key is previously communicated to the client or is defined by an agreement to be provided with the client.

Claims (17)

 1. Test station (STST) and personalization of integrated circuits (IC), comprising: -a central unit (CPUl) capable of being connected via a computer network (NTWK) to a data centralizer ( STCT), an integrated circuit (IC) test and personalization processor (TPR), arranged to store personalization data (PDk) and a personalization code (PCk), the personalization code, in at least one integrated circuit being a function of the personalization data and of a personalization key (PKa), characterized in that it comprises: a memory (SMEM) accessible in reading to the test processor and inaccessible in reading to the central unit, - means (DCD2, KREG2) for decoding, by means of a decoding key (RK, PRVK) inaccessible to the central unit (CPUl), at least one personalization key (PKa) received in a form encoded by the network intermediary (NTWK), -stock (KREG1) age of the personalization key (PKa), inaccessible for reading by the central unit (CPUl), means (CD1) for coding by means of the personalization key (PKa) personalization data (PDk), and delivering a personalization code (PCk) inaccessible to the central unit (CPUl), and means (SEQ1) for recording the personalization code (PCk) in the memory (SMEM).  2. Station according to claim 1, in which the test processor (TPR) is arranged to record in an integrated circuit (IC) application data (DTa) received via the network, characterized in that it comprises means (DCD2) for decoding, by means of a decoding key (RK, PRVK) inaccessible to the central unit (CPUl), application data (DTa) received in coded form, and recording the data application in the memory (SMEM), the output of the means for decoding the application data (DTa) being inaccessible to the central unit (CPU1).  3. Station according to one of claims 1 and 2, comprising: -means (RGEN) for delivering a session key (RK, PUBK) intended to be used as a coding key for data sent to the station, and means (CPU1, IMEM1, KREG4, CD5) for sending the session key over the network.  4. Station according to claim 3, wherein the session key is a private key (RK), characterized in that it comprises: means (CPUl, IMEM1, KREG4, CD5) for coding the session key (RK) ) by means of a logon key (IKx), and send the coded session key over the network, and - means (KREG2) for storing the session key (RK) which cannot be read by central unit (CPUl).  5. Station according to claim 4, comprising: -a key memory (IMEM1) inaccessible to the central unit (CPUl), comprising a plurality of pre-recorded session opening keys (IKj), -means (SEQ1) for select and read a logon key (IKx) in the key memory (IMEM1) according to a selection parameter ("x"), and - means (CPU1, IMESS) to send the parameter for selecting the logon key.  6. Station according to claim 5, comprising: means (KREG3, CD3) for storing said logon keys (IKj) in the key memory (IMEM1) in a form encoded by an inaccessible master key (MK2) to the central unit, and means (DCD4) for decoding by means of the master key (MK2) a session opening key (IKx) read in the key memory (IMEM1).  7. Station according to one of the preceding claims, in which the means (CD1) for coding by means of the personalization key (PKa) and the means (DCD2) for decoding by means of a decoding key (RK, PRVK) inaccessible to the central unit (CPU1) are arranged in a buffer circuit (BUF1) accessible at the input to the central unit (CPUl) and to the test processor (TPR), the output of the buffer circuit being connected to the memory input (SMEM) and not accessible to the central unit.  8. Centralizer (STCT) for test and personalization data of integrated circuits (IC), comprising a central unit (CPU2) capable of being connected via a computer network to at least one station (STST) of test and personalization of integrated circuits, characterized in that it comprises means (RD) for reading on a data carrier (CRDi) at least one key (PKi, PKa) for personalization of integrated circuits, and means (KMEM ) storage of the personalization key (PKi, PKa).  9. Centralizer according to claim 8, comprising means (CD10, CPU2) for coding a personalization key (PKa) by means of a session key (RK, PUBK) and send the coded personalization key over the network.  10. Centralizer according to claim 9, wherein said session key is a private key (RK), characterized in that it comprises means (KREG10, INDT1) for storing the session key (RK) that cannot be read from the central processing unit (CPU2)  11. Centralizer according to one of claims 9 and 10, comprising means (CD10) for coding by means of the session key (RK, PUBK) application data (DTa) intended to be recorded in integrated circuits, and send the encoded application data over the network.  12. Centralizer according to one of claims 8 to 11, comprising: -a first key memory (KMEM) inaccessible to the central unit (CPU2), -means (CD11, I11, I12) for recording in the first memory of keys a plurality of keys (PKi) for personalizing integrated circuits delivered by said means (RD) for reading a data carrier, means (SEQ2) for selecting and reading a personalization key (PKa) in the first memory.  13. Centralizer according to claim 12, comprising means (CD11, KREG11) for storing said personalization keys (PKi) in the first key memory (KMEM) in a form encoded by a master key (MK1, PUBK).  14. Centralizer according to claim 13, wherein the master key is a private key (MK1), characterized in that it comprises means (DCD12) for decoding by means of the master key (MK1) a personalization key (PKa ) read in the first key memory (KMEM).  15. Centralizer according to one of claims 8 to 14, comprising: a second key memory (IMEM2) inaccessible to the central unit, comprising a plurality of pre-recorded logon keys (IKj), means ( SEQ2) to select and read a logon key (IKX) in the second key memory (IMEM2) according to a selection parameter ("x"), and -means (KREG12, DCD13) to decode , by means of a session opening key (IKx), a session key (RK) received in an encoded form by the central unit (CPU2).  16. Centralizer according to claim 15, comprising means (KREG11, CD11) for storing said logon keys (IKj) in the second key memory (IMEM2) in a form coded by a master key (MK1) inaccessible to the central unit (CPU2), and means (KREG11, DCD12) for decoding by means of the master key (MK1) a logon key (IKx) read in the second key memory (IMEM2).  17. Test system comprising at least one station (STST) for testing and personalizing integrated circuits according to one of claims 1 to 7, and at least one centralizer (STCT) for test and personalization data according to one from claims 8 to 16.