FR2680262A1 - Integrated circuits for chip card and multichip card using these circuits - Google Patents

Abstract

The invention relates to integrated-circuit multichip cards (CI1, CI2, CI3, CI4), selection of one of which is required without resorting to additional external connection terminals. The input/output I/O of instructions for the chips is duplicated at two pins I/OA and I/OB which are normally short-circuited but which can be deshort-circuited in response to a designation instruction received by the card; a register cell is situated between the pins. The chips are cascaded with respect to these pins. The designation instruction deshort-circuits the pins firstly; data are entered into the shift register formed by the cells; at the end of the instruction, the contents of the register cell determine which chip will have to operate until the next designation instruction. Then the pins I/OA and I/OB are reshort-circuited. Application: chip cards with memory expansions.

Description

INTEGRATED CIRCUITS FOR CHIP CARD
AND MULTIPLE CHIP CARD USING THESE CIRCUITS
The invention relates to integrated circuits, and more particularly integrated circuits which can be associated with one another to be mounted in a common box capable of communicating with the outside via a small number of terminals.

 The main application is that of smart cards, but the invention can find applications elsewhere.

 As is known, current smart cards have a very small number of access contacts, most often between 6 and 8, and they only contain an integrated circuit chip.

 To increase their functional possibilities, we thought of placing several integrated circuit chips in a single card. But we are very quickly limited because of the constraint of the small number of external connection terminals. Each additional chip requires specific individual external connection terminals; certain terminals can without too much difficulty be common to all the chips: for example the supply terminals Vcc and Vss, or an external clock terminal CLK. But other terminals must be individualized for the different chips, otherwise we could not have different functions performed by the different chips or at least exchange different data with the different chips.

 For example, if we know how to make a smart card essentially comprising a chip with 256 kilobits of memory, it could be interesting to also make a card with 1 megabit of memory. This then requires four chips, but it is not possible to access each of them independently without increasing the number of external connection terminals on the card.

 The object of the present invention is to propose a trick allowing, among other advantages, to have several chips in the same card without increasing the number of connection terminals of the card.

 The invention relates on the one hand to the internal-original structure of the integrated circuit chips which make it possible to obtain this result, and on the other hand to the structure of the card which comprises these chips. Finally, it relates to the system in which the card is used; it is indeed this system (in particular the card reader in which the card will be inserted to be able to communicate with the outside) which will have the function of managing the electrical signals making it possible to use the various integrated circuit chips inside from the menu.

 First of all, the integrated circuit according to the invention it comprises an input / output pad for receiving data in the form of binary electrical signals in series, among which instructions executable by the chip, and it further comprises a second pad input / output, a shift register cell connected between the two pads, a memory means for storing in the chip the state of the cell at the end of a particular instruction called "designation", means for controlling the operation of the chip as a function of the memorized state, and means internal to the chip for short-circuiting and for short-circuiting the two pads.

 This constitution of chip is in other words characterized by the fact that it has two inputs / outputs where only one would suffice, these inputs / outputs being moreover short-circuited most of the time and not being short-circuited , to allow establishing a shift register with multiple chips cascaded, only during a designation instruction.

 The control means are in principle arranged to be able to simply inhibit or authorize the operation of the chip, but the same structure also makes it possible to choose an operating mode from among several possible operating modes of the chip.

 In practice, the means for short-circuiting and short-circuiting the two pads are controlled by an instruction decoder so as to short-circuit the pads in the general case and to short-circuit them for at least part of the duration of the designation instruction.

 The chip card according to the invention will comprise several chips, each having an upstream input / output and a downstream input / output. Fleas are likely to receive instructions on these entries. The chips are cascaded by these inputs, the downstream input / output of one being connected to the upstream input / output of the next. The chips include means for short-circuiting the upstream and downstream inputs / outputs and for short-circuiting them in response to a designation instruction received on the upstream input of the first chip.

 Thus, the smart card has the particularity of the fact that the chips have a split instruction input, the fact that the chips are connected in cascade relative to this split input / output, and the possibility that the split input / output either short-circuited into a single input / output in normal times.

 The upstream input of the first chip can be connected to an external connection terminal (I / O) on the card.

The designation instruction is then received from this terminal. But it can also be connected to an output pad of a microprocessor chip also forming part of the card, the microprocessor being able to provide on this output pad a designation instruction for one or more other chips from the menu. We will see the interest below.

 The chips may also include other connection pads which are all placed in parallel with the corresponding pads of the other chips.

 To facilitate the mounting of the chips in the chip card, provision is preferably made for the chips each to comprise, in addition to said upstream input / output and said downstream input / output, several connection pads each split into pad A and a pad B, the pad A and pad B each being located on a different side of the periphery of the chip and being short-circuited (permanently) inside the chip, and all of the connections between the external connection pins of the card and these pads of the chips being effected using a single level of interconnections on the card outside the chips.

 Finally, the smart card system according to the invention: its main characteristic is the fact that it is capable of producing on the upstream input of the first chip of the card a designation instruction which is constituted by a followed operating code of data. The operating code, received simultaneously by all the chips, is used to short-circuit the two short-circuited inputs of the chips, to establish a shift register with the short-circuited register cells of the different chips. The following data are entered into the shift register from the first chip. At the end of the instruction, the state of the different cells is memorized inside the chips and the data thus memorized determine the functioning of the chips. (and in particular the inhibition of the chips which must not function), this until the next instruction of designation.

 For this, the system according to the invention comprises a chip card with several chips, each chip comprising an upstream input / output and a downstream input / output with a register cell with shift between these two inputs / outputs and a means for short -circuit or short-circuit these two inputs / outputs, the chips being connected in cascade by their input and output upstream and downstream from an external connection terminal (I / O) of the card (or possibly from another internal card chip); the system also includes means for supplying instructions to the chips (from the outside of the card and / or from the inside), including a designation instruction, composed of an operating code followed by data to be entered into the cells the shift register formed by cascading the register cells; the chips include means for all simultaneously receiving the operating code and short-circuiting, in response to this code, the register cells, and finally the chips include means for modifying their operation as a function of the content of their shift register cell at the end of the designation instruction.

 Preferably, the chips comprise means for short-circuiting again the inputs / outputs upstream and downstream of the chips at the end of the designation instruction.

In the general case, only the chip works, the register cell of which had the appropriate value at the end of this instruction. The other chips are inhibited, and are transparent, that is to say that their presence in no way affects the connection between the selected chip and the external connection terminal of the card with which it will communicate in normal operation.

 It will be understood from the foregoing explanations that the invention is particularly advantageous in the case of chips normally having a single functional input / output, capable of receiving or supplying data in the form of bits in series. According to the invention, this input / output is split, but the supply and reception of data (which may be instructions) remains in series, both in operation and during the addressing instruction.

 There can be in each chip a single dual register shift cell containing either an authorization or inhibition bit or a choice of operating mode bit; but there can also be several binary cells in cascade between 11 upstream input and the downstream input, defining at the end of the designation instruction not only which of the chips should work but also a mode of operation for this chip . The word register cell thereafter generally designates either a binary cell or several cells in cascade.

Other characteristics and advantages of the invention will appear on reading the detailed description which follows and which is given with reference to the appended drawings in which
- Figure 1 shows a view of the general structure of a smart card according to the invention;
- Figure 2 shows a block diagram of the circuits of a chip according to the invention;
- Figure 3 shows a more detailed diagram of an embodiment of the circuitry placed between an upstream input and a downstream input;
- Figure 4 shows the connections between chips in a card, with an improvement to facilitate mounting.

 The general electrical structure of a chip card according to the ivention, visible in FIG. 1, comprises several integrated circuit chips CI1, CI2, etc., external connection terminals for communication between the card and a system of use of the card, and electrical conductors between these terminals and the chips.

The example given is that of memory cards for prepaid transactions, the external connections of which are standardized and in number at most equal to eight. These terminals are designated by letters which recall their function: VCC; VSS, VPP for power supplies, CLK for an external clock,
RST, FUSE and PROG for special functions, and an I / O input / output through which various data signals can flow, from the card to the chips or from the chips to the card, such as for example instructions to be executed by the menu. These instructions are transmitted in serial mode since there is only one terminal to receive them.

 All the external connection terminals except the I / O terminal are connected in parallel to all the chips; these have corresponding contact pads.

 In addition, while the chips of conventional smart cards include an I / O pad corresponding to the external I / O terminal, here we have two pads for each chip, respectively I / OA1 (input / output upstream) and I / OB1 (downstream input / output) for the first chip; I / OA2 and I / OB2 for the second chip, etc.

 The input / output pad of each chip is therefore split, but the card does not have more external connection terminals than in the prior art. It is essentially a duplication of the input / output pad and not an entirely different additional pad; indeed, in normal operation, the I / OA and I / OB pads of a chip are short-circuited inside the chip and therefore act as a single pad. It is only in a particular phase of designation of a chip that they will be disconnected from one another. Circuits are provided inside the chips to short-circuit or on the contrary disconnect the two studs from one another.

The chips are connected in cascade by their inputs
I / O, and not in parallel as for the other studs of the chips. This means that the downstream pad of each chip is connected to the upstream pad of a following chip, and the upstream pad of the first chip is connected to the external I / O connection terminal of the card. The downstream pad of the last chip can remain disconnected.

 This results in an original structure of a chip card with several chips.

 The internal structure of a chip, CIl for example, is shown in Figure 2.

 It obviously includes circuits represented by a block 10, performing the normal functions of the chip, which can be the same for the different chips or different depending on the chips; the chip also includes an instruction register 12 for receiving instructions by the upstream input / output terminal I / OA1 (or possibly downstream), and an instruction decoder 14 for controlling the circuit 10 according to the instruction received in the register.

 In addition, the chip includes a shift register cell CRD1 placed between the upstream input / output I / OA1 and the downstream input / output I / OB1. A similar cell is provided in each chip, so that when the chips are in cascade, these cells form a shift register whose input is the I / O terminal of the card.

 The cell CRD1 can be short-circuited or short-circuited, under the control of the decoder 14, which is represented by a switch 16. The cell CRD1 is in principle controlled by the external clock received by the terminal CLK; as this terminal is common to all integrated circuit chips, the connection of the cascade chips allows synchronized operation in shift register.

 Finally, the circuits 10 of the chip may or may not be inhibited by the content of the CRD1 cell at a given time. This moment is, in the preferred embodiment, the end of an instruction to designate a particular cell. A memory cell CRM1 is provided for this purpose, the input of which is connected for example to the downstream input I / OB1 to receive the content of the register cell CRD1; it could also be connected to the upstream input I / OA1. The memory cell is shown connected at its output to circuits 10 to indicate that it can inhibit or operate these circuits according to its content; it could also change the way they work.

Finally, the memory cell is represented controlled by the instruction decoder 14 to indicate that it is at a precise moment, controlled directly or indirectly by the instruction decoder, that the content of the register CRD1 must be loaded into the memory CRM1.

 The smart card is intended to be used in a system (including in particular a card reader) which functions in the following way: on the one hand, in a conventional manner, the system can provide instructions to a chip, by the external I / O connection terminal. If these instructions are received on the corresponding input / output terminal of the chip, they are decoded inside the chip and executed by the chip.

 On the other hand, the innovation according to the invention resides in the fact that the system is designed to be able to issue a particular instruction, which is an instruction for designating a particular chip from among the chips on the card. In principle, only one chip will be designated to operate, the others then being inhibited; but it can also be envisaged in particular applications, for example in tests, that two chips at the same time can be designated simultaneously. We can also consider, as will be seen below, that a chip, for example a microprocessor, operates continuously without needing to be designated, and that the designation instruction is used to designate another chip which will function in addition of the first.

 One can also then envisage an application of the invention in which the designation instruction is not issued by a member external to the card, but by one of the chips (a microprocessor chip for example) which operates continuously. The upstream terminal of the first chip (among the chips to be designated) is then connected not necessarily to an external terminal of the card but simply to an output terminal of the microprocessor chip.

 In all cases, the designation instruction will preferably comprise a first part which is an operating code and a second part consisting of designation data; the operating code is recognized simultaneously by the instruction decoders of all the chips which operate in parallel at the time when this code is received.

 The purpose of the operating code is to prepare the chips for the designation phase which will follow. The chips react to the operating code to short circuit their upstream and downstream inputs / outputs and therefore put the shift register cell in series between the upstream input and 11 downstream input.

 The designation instruction then comprises 11 transmissions on the I / O terminal of designation data.

The simplest way, for the designation of a single chip, is to send a series of bits comprising n-1 logical "zeros" and a logical "one", the position of 1 among the zeros used to designate a specific chip. n is the number of cascading chips.

 The bits enter the shift register formed by the cascading chips. At the end of the transmission of the n bits, only one of the chips has a logical "one" in its shift register cell; the rest have zeros.

 The contents of the register cells are then placed in the corresponding memory cell of the chip ("designation memory" CRM1 in FIG. 2).

Only the chip (possibly the) which will have a "one" in its designation memory will work thereafter. The others will remain disabled until the next designation instruction.

 The end of the execution of the designation instruction finally includes the short-circuiting of the upstream and downstream inputs of the chips, including that which is designated.

 Two interesting examples of application of the invention can be given.

 In the first example, the smart card is essentially a large capacity memory card and we want the smart card to have more memory than a single chip allows. We will then use for example four memory chips of 256 kilobits each and the card will be a 1 megabit card. The external system will have to designate the chip with which it wants to work.

 In another very interesting application, the card is a microprocessor card; it includes a microprocessor chip and several memory chips containing data addressable in write and / or read by the microprocessor. The microprocessor chip works continuously and does not need to be designated, but the memory chips work one at a time and you must designate the one with which the microprocessor must work. It is therefore these memory chips which comprise a split input pad, short-circuitable and provided with a shift register cell. It is the microprocessor which transmits the instructions in series on one of its input / output terminals, terminal to which the chips are connected in cascade by their I / OA and I / OB pads. The microprocessor can therefore in particular issue an instruction chip designation to designate the memory chip with which it will work during the following instruction (s).

 To increase the confidentiality of information processing, it can be provided that the data exchanges between the microprocessor and the memory chips are encrypted by the microprocessor.

This solution in which the chip designation instructions are issued in the card itself is also advantageous in the case where the microprocessor card only has two chips which are the microprocessor chip with memory internal to this chip, and a memory expansion chip. In this case, the designation instruction issued by the microprocessor consists
- either to designate the chip by placing a "1" in its register cell, then in its designation memory, in which case the microprocessor operates with the memory extension: the instructions for reading and writing from the memory are executed by the external memory chip;
- or not to designate the chip, by placing a "0" in its register cell and then in its designation memory, in which case the microprocessor chip works only with its internal memory.

 This solution is therefore entirely advantageous for producing a microprocessor circuit with a memory extension, whether in a smart card or not.

 Consequently, the invention also relates to a multi-chip chip card in which there is a microprocessor and only one other chip capable of being designated; this other chip is the only one to have an upstream input / output and a downstream input / output with a register cell short-circuitable between the two. The "cascade" of chips is therefore reduced to a single chip but the operating principle is the same. The designation instruction comes from the microprocessor.

 FIG. 3 represents an example of detailed circuitry at the I / O input of a chip according to the invention; this circuitry corresponds to the block diagram in FIG. 2. It operates under the control of two signals: the clock signal CLK and its complement CLK-; and a signal SEL and its complement SEL-, coming from the instruction decoder 14. The signal SEL is normally at zero, goes to 1 at the end of the reception of the operating code of the designation instruction, and returns to zero at the end of the designation instruction, when the designation data have been set up in the shift register formed by the cascading chips.

 The shift register cell CRD1 has two cascaded circuit elements.

The first element comprises a switch 20 actuated during CLK-, upstream of the entry of a door
NAND 22 which also receives on another input the selection signal SEL. An inverter 24, in series with a switch 26 controlled by CLK, loops the output of the NAND gate to the first input of the gate
NAND.

 The second circuit element, connected to the output of the NAND gate, comprises a switch 28, actuated by CLK, in series with an inverter 30, the output of which constitutes the output of the cell CRU1. The output of the inverter is also connected to a first input of a NAND gate 32, another input of which receives the signal SEL. Finally, the output of this NAND gate is looped back through a switch 34 actuated by CLK, on the input of the inverter 30.

 The output of the cell CRD1 is connected through a switch 36 (actuated by the signal SEL) to the downstream input / output I / OB1 of the chip.

 This cell only works while SEL is at level 1. A bit from I / OA1 is stored in the first part of the cell during CLK-; it goes into the second part during CLK.

 If SEL = 0, the I / OA1 and I / OB1 inputs are short-circuited. The CRD1 cell does not work.

 When SEL goes back from 1 to 0, the state present on the output of the cell CRD1 is memorized in the memory cell CRM1 which is essentially a flip-flop controlled by the output of the cell CRD1 but provided with an authorization input controlled by signal SEL. When SEL goes to 0, the cell can no longer switch and keeps the last state it had.

 The output of the flip-flop is a CE signal which is used to authorize or not the functioning of the chip (more precisely the circuits 10 of the chip) from this moment.

 The instruction decoder is simply constituted in a conventional manner by a programmable logic network (PLA). It will include, compared to that of a conventional chip, an additional line for processing the SEL signal upon reception of the operating code corresponding to the designation instruction.

 FIG. 4 finally represents an additional improvement.

 Again, although this improvement is more particularly interesting for smart cards of conventional credit card format, it must be understood that it can find other applications, and we must therefore take the word "card" in the broad sense .

 The improvement concerns the interconnection between the chips on the card. As there are several identical chips, they have identical pads which must be connected in parallel by printed connections forming part of the card.

 The idea is to split almost all of the pads by shorting them inside the chip, and to place one of the split pads on one side of the periphery of the chip (side facing an adjacent chip), and the other on the other side (facing another adjacent chip). Of course, the I / OA1 pad and the I / OB1 pad will follow a particular treatment: they are not permanently short-circuited like the other split pads since we must be able to short-circuit them.

But they are also placed each on one side of the periphery of the chip. The order of the studs on one side of the periphery is reversed from the order of the corresponding studs on the other side.

 With this duplication of the pads which are common to several chips, especially in the case of identical chips, we will be able to connect the chips together and connect the chips to the external terminals of the card with a single level of interconnections, that is to say ie without crossing of interconnections.

Figure 4 shows a possible example. The external terminals of the card are the eight VCC terminals,
VSS, RST, VPP, CLK, I / O, FUSE, PROG. All the chips have eight corresponding pads.

 Of these eight studs, VCC and VSS were not split because it was not useful. I / O is split in the specific manner described above. The other five pads are split and permanently short-circuited inside the chips. The problem of crossing the interconnections is therefore transferred to the interior of the chips which in any case include crossings.

Claims (16)

 1. Integrated circuit chip, comprising an input / output pad (I / OA1) for receiving data in the form of binary electrical signals in series, including instructions executable by the chip, characterized in that it comprises in addition to a second input / output pad (1 / OBi), a shift register cell (CRD1) connected between the two pads, a memory means (CRM1) for storing the state of the cell in the chip at the end of a particular instruction called "designation", means (16) for short-circuiting and short-circuiting the two pads inside the chip, and means (CE) for controlling the operation of the chip according to the memorized being.  2. Integrated circuit according to claim 1, characterized in that the control means (CE) are capable of inhibiting or at least partially authorizing the operation of the chip as a function of the memorized being of the binary cell.  3. Integrated circuit according to one of claims 1 and 2, characterized in that the chip is able to operate according to several operating modes and in that the control means (CE) are able to control the operating mode.  4. Integrated circuit according to one of claims 1 to 3, characterized in that the means (16) for short-circuiting and short-circuiting the two pads are controlled by an instruction decoder (14) so as to short- circuit the pads in the general case and short circuit them for at least part of the duration of execution of the designation instruction.  5. Card with several integrated circuit chips, characterized in that it comprises several chips (CI1, C12, ...) each having an upstream input / output (I / OA1) and a downstream input / output (I / OB1 ) and likely to receive instructions on these inputs, in that the chips are connected in cascade by these inputs, the downstream input of one being connected to the upstream input of the next, in that the chips include means internal to the chip for short-circuiting or short-circuiting the upstream input and the downstream input in response to a designation instruction received on the upstream input of the first chip.  6. Chip card according to claim 5, characterized in that the upstream input of the first chip is connected to an external connection terminal (I / O) of the card.  7. Chip card according to claim 5, characterized in that the upstream input of the first chip is connected to an output pad of a microprocessor chip also forming part of the card, the microprocessor being capable of providing on this output pad a designation instruction.  8. Chip card according to one of claims 5 to 7, characterized in that the chips comprising an upstream input and a downstream input capable of being short-circuited and short-circuited furthermore comprise other connection pads which are all put in parallel with the corresponding studs of the other chips.  9. Chip card according to one of claims 5 to 8, characterized in that the chips comprising an upstream input and an ayal input capable of being short-circuited and short-circuited are integrated circuit chips according to one of claims 1 to 4.  10. Chip card according to one of claims 5 to 9, characterized in that the chips each comprise, in addition to said upstream input / output and said downstream input / output, several connection pads each split in pad A and a pad B , the pad A and the pad B being each located on a different side of the chip and being short-circuited inside the chip, and all of the connections between the external connection pins of the card and these pads of the chips using only one level of interconnections on the card outside the chips.  11. System using smart cards, comprising a smart card with several chips (CI1, CI2 CI3, CI4), each chip comprising an upstream input / output (I / OA1) and a downstream input / output (I / OB1) with a shift register cell (CRD1) between these two inputs / outputs and a means (16 ) for short-circuiting or short-circuiting these two inputs / outputs, the chips being connected in cascade by their upstream and downstream inputs / outputs, in that the system also includes means for supplying instructions for the chips, including a designation instruction, composed of an operating code followed by data to be introduced into the cells of the shift register formed by cascading the register cells (CRD1), in that the chips include means for all simultaneously receiving the operating code and shortens circuit, in response to this code, the register cells, and in that the chips include means for modifying their operation as a function of the content of their shift register cell at the end of the instruction designation.  12. System according to claim 11, characterized in that the chips include means (16) so that the upstream and downstream inputs / outputs are short-circuited at the end of the execution of the designation instruction.  13. System according to one of claims 11 and 12, characterized in that the chips include means (CE) for inhibiting or authorizing their operation as a function of the content of their shift register cell (CRD1) at the end of the execution of the designation instruction, until further receipt of another designation instruction.  14. System according to one of claims 11 to 13, characterized in that certain chips include several possible operating modes, and in that they include means for changing operating mode according to the content of their register cell shift (CRD1) at the end of the designation instruction.  15. System according to one of claims 11 to 14, characterized in that the chip card comprises a microprocessor chip having an internal memory and at least one other chip constituting an external memory for the microprocessor, the latter chip having an input / upstream (I / OA1) and an input / downstream (I / OB1) with a register cell (CRD1) in between so as to be able to be designated by a designation instruction, in that the microprocessor is capable of providing this instruction of designation, and in that the memory read or write instructions supplied by the microprocessor after execution of the designation instruction are executed by the external memory or by the internal memory depending on whether or not the external memory chip has been designated by designation instruction.  16. System according to one of claims 11 to 15, characterized in that the smart cards are cards according to one of claims 5 to 10.