FR2666917A1 - Double-access memory-storage device - Google Patents

Abstract

The invention relates to a double-access memory-storage device. When the device, which includes a first (20, 22) and a second (30, 32) normal memory, carries out a transfer of data by means of a first and of a second transfer signal, and when one of the normal memories is defective, that one of the first and second transfer signals which corresponds to the defective normal memory is selected by a redundant generator (70) of transfer signals; the redundant transfer signal opens a redundant transfer gate (64) in order to transfer the data item between a redundant RAM component (60) and a redundant SAM component (62) and in order to replace the deficient part of the normal memory; hence, when one of the two parts of the memory-storage device becomes faulty during a subdivided transfer of data, it can be replaced by the redundant circuit provided, which makes it possible to reduce the size of the memory-storage device to the minimum.

Description

The present invention relates to a dual storage device

  access or dual port comprising accesses or ports of RAM memory (random access memory) and SAM (serial access memory), more particularly a dual access storage device which comprises

  also a redundant circuit The storage device

  dual access has one or more RAMI ports and

  SAM respectively formed from sets of memo cells

  The dual access memory device has been designed to be used as a VRAM memory (RAM

  Video) for graphic representations.

  In a DRA M memory (conventional dynamic RAM memory, when data is transferred from a processor to a peripheral device, the data is first transferred to memory and then the peripheral device establishes access to the transferred data. case, the processor cannot transfer the data in memory while the access to the data is carried out in

the peripheral device.

  However, in dual access memory, the

  peripheral device provides access to the transferred data

  stored in memory via a second port, while the data is transferred into memory via a first port The first and second

  ports represent the SAM and RAM ports respectively.

  The SAM port has a fast access time so that a VRAM memory can be used for high-resolution and high-speed graphic representation. For carrying out the split transfer with this dual-access storage device, a storage means normal is divided

  in upper and lower parts.

  When the lower part is a first normal memory and the upper part is a second normal memory, the SAM component of the second normal memory performs an RT read transfer operation or a

  write transfer operation I T while the composition

  sant SAM 'of the first normal memory performs an operation

  read ration or write operation In addition, the

  redundant circuit avoids a reduction in the

  under the effect of a failure of the memory means

  normal, which can be caused by integration

  this, if the failure is produced in a certain part of the normal storage means, the redundant circuit is

  connected in place of the normal storage means d Jfec-

  killer in order to maintain normal operation.

  For the application of the transfer mode fraction-

  born with the dual-access memory device convention-

  nel provided with the redundant circuit, the normal storage means is divided into a first and a second memory,

  the read operation or the write operation being carried out

  killed in a game while the RT operation or the opera-

  tion ^ T is performed in the other part Consequently,

  first and second transfer signals are required

  res in correspondence to the first and second memories

  normal for the fractional transfer in the memory medium

normal risation.

  In this case, a first and a second redundant circuit are also provided for the redundant storage means, respectively in the same manner as for the normal storage means, so that the first and second redundant circuits of the redundant storage means

  are connected in place of the first and second

  normal memory when the normal storage means is defective, in order to maintain operation

normal.

  There is, however, a drawback that

  the capacity of the memory device must be increased

  since the redundant storage means must be

  provided with first and second redundant circuits respectively

  dants for the compensation of failures of the first and

  second normal memories in split transfer mode

  tionné. Consequently, the object of the present invention is to create a dual-access storage device in which a single redundant circuit is provided to compensate for the defects of the normal storage means formed.

  of the first and second normal memory.

  In accordance with this invention, a dual-access storage device is created comprising: normal storage means comprising a part A 11 comprising a first zt a second RAM component, a SAII part comprising a Drerlier and a second SAM component, a door section having first and second doors for memory transfer, and a generator for applying first and second transfer signals to said first and second doors for memory transfer so that fractional data transfer can be performed with, in a first normal memory, transfer from the first RAIl component and the first SAM component and in a second normal memory,

  transfer from the second RAU component and the second component

  posing SAM; redundant storage means comprising a redundant RAM component, a redundant SAM component and a redundant transfer door so as to replace a

  certain defective part of one of said normal memories

  them during data transfer; and a redundant transfer signal generator receiving at the input the

  first and second transfer signals from the general

  memory transfer signal generator and transmitting

  selectively at said redundant gate the signal of trans-

  fert corresponding to said certain defective part of

normal memory.

  Other features and advantages of the

  vention will be highlighted in the following description

  tion, given by way of nonlimiting example, with reference to the accompanying drawings in which

  FIG. 1 is a block diagram of a memory device

  double access according to the present invention, Figure 2 is a detailed circuit diagram of the redundant transfer signal generator shown in Figure

  1 and according to the present invention.

  The invention will now be described in a manner

  more details with reference to the attached drawings.

  FIG. 1 shows the storage device

  double access according to the present invention In FIG. 1, the double access storage device comprises at least one normal storage means 10 and one

  redundant storage means 50 The storage means

  normal tion 10 comprises a RAM part comprising a first RAMI component 20 and a second RAM component, a SAM part comprising a first SAM component 22 and a second SAM component 32, a first and a second

  memory transfer door 24, 34 respectively inter-

  posed between the first component RA> I and the first component

  sant SAM as well as between the second component RAII and the second component S At M, and a generator 40 of transfer signals in memory for producing transfer signals and applying them to the first and to the second gate of

transfer to memory 22, 32.

  On the other hand, a redundant storage means comprises a redundant RAM component 60, a redundant SAM component 62, a redundant transfer gate 64

  interposed between the redundant RAM component 60 and the component

  sant SAM redundant 62, and a redundant generator 70 of transfer signals, interposed between the transfer door

  redundant 64 and the first and second trans doors

fert in memory 24 and 34.

  In operation, firstly if the first normal memory is formed of the first RAM component 20 and

?

  of the first SAMI 22 component and if the second memory nor-

  male is formed by the second component RAM 30 and the second component SAM 32, the first component S Al 22 is in the access state if the bit; l SD (most significant bit) of an address is "O" (low logic level), while the second component SAI'32 is in the access state if the said MSB of the address is "1" (high logic level) during the fractional transfer operation of the device

dual access memory.

  When the first SAM component 22 is in the access state, the data transfer is carried out in the second SAM component 32 On the contrary, if the second

  component SAM 32 is in the access state, the trans-

  data fert is performed in the first SAM component 22 Also, the first and second transfer signals generated by the generator 40 of memory transfer signals are applied respectively to the first and to the

  second memory transfer gate 24, 34.

  In this case, the first and second transfer signals are multiplexed with bit ll SB of the address and are applied to the first and second transfer gate in memory 24, 34 Consequently, the first and the second transfer signal transfer, respectively multiplexed with the MSB bit of the address, respectively produce an opening and a closing of the transfer doors in

memory 24 and 34.

  For example, if bit M 53 of the address is "1", the first transfer signal is multiplexed in order to

  open the first memory transfer door 24.

  Then the first normal memory, formed of the first component

  sant RAM 20 and the first SAM 22 component, performs the mo-

  RT or WT mode, while the second normal memory, formed by the second RAM component 30 and the second SAM component 32, performs the read mode or the write mode, and the signals which are applied to the first and to the second transfer gate in memory 24, 34 are transmitted

  to the redundant generator 70 of transfer signals.

  In the redundant transfer signal generator 70, the first transfer signal serving to open the redundant transfer door 64 is selected and transmitted Next, the redundant storage means 50, formed by the redundant component RA Ml 50 and the component S Al

  redundant 62, performs data transfer, replacing

  thus erasing the certain defective part of the first

normal memory.

  Figure 2 is a detailed circuit diagram of the

  redundant generator 70 of transfer signals, represented

  shown in Figure 1 and operating in accordance with this

  The invention In FIG. 2, the redundant generator 70 of transfer signals is formed of a fuse circuit

  72 and a circuit 74 for selecting transfer signals.

  The fuse circuit 72 fixes the MSB bit of a redundant address RC Am always it "thanks to the MSB bit of a fundamental address C Am, which is validated and applied by a redundant validation signal RE, which is" 1 "when the fault occurs in a certain part of the normal storage means 10. The transfer signal selection circuit 74 selects one or the other of the first and second transfer signals as redundant transfer signal by means of the MSB bit of the fundamental address C Am and of the MSB bit of the redundant address RC Am. We will now describe the operation of the redundant generator 70 of transfer signals. First, the first normal memory performs the data transfer if the MSB bit of the basic address C Am is "1" while the data transfer is interrupted

  and the RE signal is changed to "1" if the fault occurs.

  Then, the signal RE "1" is applied to each control electrode of two transistors lt IOS, designated by 11 and N 2, t while the signal RE 11011 which has been inverted by an inverter I 2 is applied to each electrode of control of an NMOS transistor designated by: I 5 and of two P 1 MOS transistors designated by Pl and P 2, so that the

  transistor NI, 10 S H 5 is blocked while the other trans-

  sistors 1 l, N 2, Pl and P 2 are made conductive for

blir an initial value.

  Consequently the bit 'IISB of the basic address-

  tale C Am provides the MSB bit of the redundant address

  dante RC Am at a node 77 via transistors N 1 and Pl and a first fuse F 1, or

  well through an inverter Il, transis-

  tors U 2 and P 2 and a second fuse F 2.

  In this case, since the MSB bit of the redundant address RC Am must always be "1", the second fuse F 2 is cut and the bit -ISB of the fundamental address C Am is transferred via the first fuse Fi The bit: ISD "1" of the redundant address PC Am is applied to each input terminal of a NAND gate N Al and a gate

OR GOLD.

  Also, bit M 53 "1" of the basic address

  tale C Am is applied to each other input terminal of the NAND gate NA 1 and the OR gate OR Consequently, the NAND gate NA 1 and the OR gate OR respectively apply a "O" bit and a bit "1" at the input terminals of a NAND gate NA 2 The NAND gate NA 2 applies an output signal of "1" to each control electrode of a PMOS transistor P 3

and an NMOS N 4 transistor.

  In addition, the output signal from the NAND gate NA 2 is inverted by an inverter I 3 and this inverted output signal is applied to each control electrode of a

  PMOS transistor P 4 and an NMOS transistor N 3.

  Consequently, the transistors P 4 and N 14 are made conductive so as to apply the first transfer signal to the redundant transfer door 64 Then the redundant transfer door 64 is made passable so that the redundant RA I component 60 and the redundant SAI 1 component 62 can perform data transfer in place of a certain defective part of the first

normal memory.

  On the other hand, when the second normal memory performs the data transfer, the basic bit MSB "'0" 1 of the address is C Am is applied Consequently, if the fault has occurred in a certain part of the second normal memory, the fuselage F 2 is cut in the redundant generator 70 of transfer signals Then the PMOS transistor P 3 and the transistor Lw 1 OOS Nj 3 are made conductive to apply the second transfer signal to the redundant transfer gate 54 The redundant transfer gate 64 is turned on so that the redundant RAM component 60 and the redundant SAM component 62 can perform data transfer in place of the certain party

  second normal memory faulty.

  As mentioned above, in the dual access storage device comprising the first and the

  second normal memory in accordance with this invention

  tion, if the fault occurs in a certain normal memory, that of the first and second transfer signals

  which corresponds to the faulty normal memory is selected

  operated by the redundant transfer signal generator.

  The transfer signal opens the redundant transfer door.

  dante to perform data transfer between the

  laying down redundant RAM and the redundant SAM component and for replacing the defective part of the normal memory Consequently, the present invention has the advantage that a single redundant circuit is provided to replace the defective part of the normal storage means during the fractional transfer reducing the size of the dual storage device

  access according to the present invention.

  Of course, the invention is not limited to the exemplary embodiments described above and reshaped, from which other modes and other embodiments can be provided, without thereby departing from the

part of the invention.

O

Claims (4)

  1 dual-access storage device, characterized in that it comprises: normal storage means (10) comprising a RAM part comprising a first (20) and a second (30) RAM component, a SAM part comprising a first (22) and a second (32) SAL component, a door part (24, 34) comprising a first (24) and a second (34) door for transfer into memory, and a generator (40) for applying a first and a second transfer signal   to said first and second doors (24, 34) for a trans-   fert in memory, so that the fractional transfer of data can be carried out with, in a first normal memory, transfer from the first component RAM (20) and the first component SA Ml (22) and, in a second normal memory , transfer from the second RAM component (30) and the second SAM component (32); redundant storage means (50) comprising a redundant RAM component (60), a redundant SAM component (62) and a redundant transfer gate (64) so as to replace a certain defective part of one of said normal memories during transfer of data; and a redundant transfer signal generator (70) receiving the first and second signal at the input   transfer from the signal generator (40)   fert in memory and selectively transmitting to said redundant door (64) the transfer signal corresponding to   said certain defective part of normal memory.   2 double access storage device according to claim 1, characterized in that said redundant generator (70) of transfer signals comprises a fuse circuit (72; F 1, F 2) fixing the most significant bit (MSB) d 'a redundant address at "1" independently of the MSB bit of an input address validated by a redundant validation signal when the fault has occurred in a certain part of normal memory during a data transfer; and a redundant signal selector (74) for selecting either the first or the second transfer signal, corresponding to the bit Mi SB of the input address and that of the redundant address and for delivering it as a redundant transfer signal.   3 dual access storage device according to claim 2, characterized in that said redundant validation signal is always "1", if the fault occurs in a certain part of a normal memory during data transfer.   4 dual access storage device according to claim 2, characterized in that the IMSB bit of   the input address is "O" or "1".   Dual access storage device according to claim 4, characterized in that the MSB bit of the redundant address is defined by a cut-off of a fuse (F 1) which is connected to an inverter (I) when the MSB bit of the input address is "1" and is defined by a cut-off of another fuse (F 2) which is not connected to said inverter (Il) when the bit M SB of the entry address is "O".