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FR2607323B1 - Procede de formation d'un motif consistant en une pellicule metallique a deux couches - Google Patents

Procede de formation d'un motif consistant en une pellicule metallique a deux couches

Info

Publication number
FR2607323B1
FR2607323B1 FR8716264A FR8716264A FR2607323B1 FR 2607323 B1 FR2607323 B1 FR 2607323B1 FR 8716264 A FR8716264 A FR 8716264A FR 8716264 A FR8716264 A FR 8716264A FR 2607323 B1 FR2607323 B1 FR 2607323B1
Authority
FR
France
Prior art keywords
forming
metal film
pattern consisting
layered metal
layered
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR8716264A
Other languages
English (en)
Other versions
FR2607323A1 (fr
Inventor
Hirofumi Nakano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of FR2607323A1 publication Critical patent/FR2607323A1/fr
Application granted granted Critical
Publication of FR2607323B1 publication Critical patent/FR2607323B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/061Manufacture or treatment of FETs having Schottky gates
    • H10D30/0612Manufacture or treatment of FETs having Schottky gates of lateral single-gate Schottky FETs
    • H10D30/0616Manufacture or treatment of FETs having Schottky gates of lateral single-gate Schottky FETs using processes wherein the final gate is made before the completion of the source and drain regions, e.g. gate-first processes
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/04Coating on selected surface areas, e.g. using masks
    • C23C14/042Coating on selected surface areas, e.g. using masks using masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/942Masking
    • Y10S438/948Radiation resist
    • Y10S438/951Lift-off

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • General Physics & Mathematics (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Metallurgy (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Organic Chemistry (AREA)
  • Mechanical Engineering (AREA)
  • Materials Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)
FR8716264A 1986-11-24 1987-11-24 Procede de formation d'un motif consistant en une pellicule metallique a deux couches Expired - Fee Related FR2607323B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61280396A JPS63132452A (ja) 1986-11-24 1986-11-24 パタ−ン形成方法

Publications (2)

Publication Number Publication Date
FR2607323A1 FR2607323A1 (fr) 1988-05-27
FR2607323B1 true FR2607323B1 (fr) 1995-03-10

Family

ID=17624444

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8716264A Expired - Fee Related FR2607323B1 (fr) 1986-11-24 1987-11-24 Procede de formation d'un motif consistant en une pellicule metallique a deux couches

Country Status (4)

Country Link
US (1) US4871419A (fr)
JP (1) JPS63132452A (fr)
FR (1) FR2607323B1 (fr)
GB (1) GB2198149B (fr)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01109770A (ja) * 1987-10-22 1989-04-26 Mitsubishi Electric Corp 半導体装置の製造方法
FR2643508B1 (fr) * 1988-08-24 1995-10-27 Mitsubishi Electric Corp Procede de fabrication d'un dispositif semiconducteur comprenant une electrode en metal refractaire sur un substrat semi-isolant
US5168071A (en) * 1991-04-05 1992-12-01 At&T Bell Laboratories Method of making semiconductor devices
JPH06120211A (ja) * 1992-10-06 1994-04-28 Nec Corp 半導体装置の製造方法
US5858843A (en) * 1996-09-27 1999-01-12 Intel Corporation Low temperature method of forming gate electrode and gate dielectric
KR100258803B1 (ko) 1997-11-28 2000-06-15 전주범 반도체 소자의 미세 패턴 형성방법
WO2004097914A1 (fr) * 2003-04-25 2004-11-11 Sumitomo Electric Industries, Ltd. Procede de production d'un dispositif a semi-conducteur

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4028149A (en) * 1976-06-30 1977-06-07 Ibm Corporation Process for forming monocrystalline silicon carbide on silicon substrates
US4377899A (en) * 1979-11-19 1983-03-29 Sumitomo Electric Industries, Ltd. Method of manufacturing Schottky field-effect transistors utilizing shadow masking
US4415606A (en) * 1983-01-10 1983-11-15 Ncr Corporation Method of reworking upper metal in multilayer metal integrated circuits
US4420365A (en) * 1983-03-14 1983-12-13 Fairchild Camera And Instrument Corporation Formation of patterned film over semiconductor structure
JPS59229876A (ja) * 1983-06-13 1984-12-24 Toshiba Corp シヨツトキ−ゲ−ト型電界効果トランジスタの製造方法
US4577392A (en) * 1984-08-03 1986-03-25 Advanced Micro Devices, Inc. Fabrication technique for integrated circuits
US4670091A (en) * 1984-08-23 1987-06-02 Fairchild Semiconductor Corporation Process for forming vias on integrated circuits
US4631806A (en) * 1985-05-22 1986-12-30 Gte Laboratories Incorporated Method of producing integrated circuit structures
JPS62172755A (ja) * 1986-01-27 1987-07-29 Canon Inc フオトセンサの作製方法
US4680085A (en) * 1986-04-14 1987-07-14 Ovonic Imaging Systems, Inc. Method of forming thin film semiconductor devices
US4678542A (en) * 1986-07-25 1987-07-07 Energy Conversion Devices, Inc. Self-alignment process for thin film diode array fabrication
US4690728A (en) * 1986-10-23 1987-09-01 Intel Corporation Pattern delineation of vertical load resistor

Also Published As

Publication number Publication date
GB2198149A (en) 1988-06-08
JPS63132452A (ja) 1988-06-04
GB8723519D0 (en) 1987-11-11
FR2607323A1 (fr) 1988-05-27
GB2198149B (en) 1990-10-24
US4871419A (en) 1989-10-03

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Legal Events

Date Code Title Description
ST Notification of lapse

Effective date: 20070731