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FR2569494B1 - Procede de fabrication de dessins d'interconnexion pour dispositif a semi-conducteur, et dispositifs formes par sa mise en oeuvre - Google Patents

Procede de fabrication de dessins d'interconnexion pour dispositif a semi-conducteur, et dispositifs formes par sa mise en oeuvre

Info

Publication number
FR2569494B1
FR2569494B1 FR8512682A FR8512682A FR2569494B1 FR 2569494 B1 FR2569494 B1 FR 2569494B1 FR 8512682 A FR8512682 A FR 8512682A FR 8512682 A FR8512682 A FR 8512682A FR 2569494 B1 FR2569494 B1 FR 2569494B1
Authority
FR
France
Prior art keywords
semiconductor device
drawings
formed therefrom
devices formed
manufacturing interconnection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR8512682A
Other languages
English (en)
Other versions
FR2569494A1 (fr
Inventor
Masahiro Kameda
Yojiro Kamei
Kenichi Kurihara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP17583084A external-priority patent/JPS6154644A/ja
Priority claimed from JP21125584A external-priority patent/JPS6190444A/ja
Priority claimed from JP25846784A external-priority patent/JPS61137342A/ja
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Publication of FR2569494A1 publication Critical patent/FR2569494A1/fr
Application granted granted Critical
Publication of FR2569494B1 publication Critical patent/FR2569494B1/fr
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3215—Doping the layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3215—Doping the layers
    • H01L21/32155—Doping polycristalline - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
FR8512682A 1984-08-25 1985-08-23 Procede de fabrication de dessins d'interconnexion pour dispositif a semi-conducteur, et dispositifs formes par sa mise en oeuvre Expired FR2569494B1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP17583084A JPS6154644A (ja) 1984-08-25 1984-08-25 薄膜及びその製造方法
JP21125584A JPS6190444A (ja) 1984-10-11 1984-10-11 薄膜の製造方法
JP25846784A JPS61137342A (ja) 1984-12-08 1984-12-08 薄膜製造方法

Publications (2)

Publication Number Publication Date
FR2569494A1 FR2569494A1 (fr) 1986-02-28
FR2569494B1 true FR2569494B1 (fr) 1988-08-12

Family

ID=27324168

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8512682A Expired FR2569494B1 (fr) 1984-08-25 1985-08-23 Procede de fabrication de dessins d'interconnexion pour dispositif a semi-conducteur, et dispositifs formes par sa mise en oeuvre

Country Status (3)

Country Link
DE (1) DE3530419A1 (fr)
FR (1) FR2569494B1 (fr)
GB (2) GB2165692B (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5330629A (en) * 1992-12-15 1994-07-19 At&T Bell Laboratories Method for depositing aluminum layers on insulating oxide substrates
JPH09260374A (ja) * 1995-09-27 1997-10-03 Texas Instr Inc <Ti> 集積回路の相互接続および方法
US6391754B1 (en) 1996-09-27 2002-05-21 Texas Instruments Incorporated Method of making an integrated circuit interconnect

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3903324A (en) * 1969-12-30 1975-09-02 Ibm Method of changing the physical properties of a metallic film by ion beam formation
US3682729A (en) * 1969-12-30 1972-08-08 Ibm Method of changing the physical properties of a metallic film by ion beam formation and devices produced thereby
US4012756A (en) * 1969-12-30 1977-03-15 International Business Machines Corporation Method of inhibiting hillock formation in films and film thereby and multilayer structure therewith
US3887994A (en) * 1973-06-29 1975-06-10 Ibm Method of manufacturing a semiconductor device
DE2554638A1 (de) * 1975-12-04 1977-06-16 Siemens Ag Verfahren zur erzeugung definierter boeschungswinkel bei einer aetzkante
DD136670A1 (de) * 1976-02-04 1979-07-18 Rudolf Sacher Verfahren und vorrichtung zur herstellung von halbleiterstrukturen
US4111775A (en) * 1977-07-08 1978-09-05 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Multilevel metallization method for fabricating a metal oxide semiconductor device
US4267011A (en) * 1978-09-29 1981-05-12 Tokyo Shibaura Denki Kabushiki Kaisha Method for manufacturing a semiconductor device
DE3003285A1 (de) * 1980-01-30 1981-08-06 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen niederohmiger, einkristalliner metall- oder legierungsschichten auf substraten
DE3217026A1 (de) * 1981-05-06 1982-12-30 Mitsubishi Denki K.K., Tokyo Halbleitervorrichtung
US4450041A (en) * 1982-06-21 1984-05-22 The United States Of America As Represented By The Secretary Of The Navy Chemical etching of transformed structures
US4502207A (en) * 1982-12-21 1985-03-05 Toshiba Shibaura Denki Kabushiki Kaisha Wiring material for semiconductor device and method for forming wiring pattern therewith
US4489482A (en) * 1983-06-06 1984-12-25 Fairchild Camera & Instrument Corp. Impregnation of aluminum interconnects with copper

Also Published As

Publication number Publication date
GB2171251B (en) 1989-05-10
GB2165692B (en) 1989-05-04
GB8520956D0 (en) 1985-09-25
GB2165692A (en) 1986-04-16
DE3530419A1 (de) 1986-03-06
GB2171251A (en) 1986-08-20
GB8602637D0 (en) 1986-03-12
FR2569494A1 (fr) 1986-02-28

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Legal Events

Date Code Title Description
ST Notification of lapse