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FR2469060A1 - CIRCUIT ARRANGEMENT SUITABLE FOR SYNCHRONIZING A DEMULTIPLEXING UNIT, PARTICULARLY APPLICABLE TO THE RECEIVING SECTION OF A DIGITAL SIGNAL MULTIPLEXER - Google Patents

CIRCUIT ARRANGEMENT SUITABLE FOR SYNCHRONIZING A DEMULTIPLEXING UNIT, PARTICULARLY APPLICABLE TO THE RECEIVING SECTION OF A DIGITAL SIGNAL MULTIPLEXER

Info

Publication number
FR2469060A1
FR2469060A1 FR8019411A FR8019411A FR2469060A1 FR 2469060 A1 FR2469060 A1 FR 2469060A1 FR 8019411 A FR8019411 A FR 8019411A FR 8019411 A FR8019411 A FR 8019411A FR 2469060 A1 FR2469060 A1 FR 2469060A1
Authority
FR
France
Prior art keywords
output
digital signal
circuit arrangement
receiving section
signal multiplexer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
FR8019411A
Other languages
French (fr)
Inventor
Giovanni Pennoni
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Italtel SpA
Original Assignee
Societa Italiana Telecomunicazioni Siemens SpA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Societa Italiana Telecomunicazioni Siemens SpA filed Critical Societa Italiana Telecomunicazioni Siemens SpA
Publication of FR2469060A1 publication Critical patent/FR2469060A1/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0079—Receiver details
    • H04L7/0083—Receiver details taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0602—Systems characterised by the synchronising information used
    • H04J3/0605—Special codes used as synchronising signal
    • H04J3/0608—Detectors therefor, e.g. correlators, state machines

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

Une disposition de circuit apte à synchroniser une unité de démultiplexage, s'appliquant à la section réceptrice d'un multiplexeur de signaux numériques, et destinée à être utilisée en combinaison avec une unité de décodage apte à exciter sa propre sortie en réponse au relèvement d'une configuration binaire coïncidant avec la parole d'alignement Elle comprend un réseau logique apte à émettre une impulsion en réponse au relèvement de l'excitation de l'unité de décodage et apte à relever si la sortie de l'unité de décodage est excitée. Un registre est connecté à la sortie d'une memoire limitée à la lecture, apte à mémoriser un nombre de codes caractéristiques d'autant de phases du programme opératif, à l'entrée des adresses de laquelle sont connectées les cellules du registre ainsi que la sortie du réseau logique.A circuit arrangement adapted to synchronize a demultiplexing unit, applying to the receiving section of a digital signal multiplexer, and intended for use in combination with a decoding unit adapted to drive its own output in response to the raising of d 'a binary configuration coinciding with the alignment speech It comprises a logic network capable of emitting a pulse in response to the raising of the excitation of the decoding unit and capable of detecting whether the output of the decoding unit is energized . A register is connected to the output of a memory limited to reading, capable of memorizing a number of characteristic codes of as many phases of the operating program, to the input of the addresses to which the cells of the register are connected as well as the logic network output.

FR8019411A 1979-10-29 1980-09-09 CIRCUIT ARRANGEMENT SUITABLE FOR SYNCHRONIZING A DEMULTIPLEXING UNIT, PARTICULARLY APPLICABLE TO THE RECEIVING SECTION OF A DIGITAL SIGNAL MULTIPLEXER Pending FR2469060A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT7926859A IT1207280B (en) 1979-10-29 1979-10-29 CIRCUIT PROVISION SUITABLE FOR SYNCHRONIZING A DEMULTIPLATION UNIT, FOR PARTICULAR APPLICATION IN THE RECEIVING SECTION OF A MULTIPLATOR DIGITAL SIGNALS.

Publications (1)

Publication Number Publication Date
FR2469060A1 true FR2469060A1 (en) 1981-05-08

Family

ID=11220392

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8019411A Pending FR2469060A1 (en) 1979-10-29 1980-09-09 CIRCUIT ARRANGEMENT SUITABLE FOR SYNCHRONIZING A DEMULTIPLEXING UNIT, PARTICULARLY APPLICABLE TO THE RECEIVING SECTION OF A DIGITAL SIGNAL MULTIPLEXER

Country Status (6)

Country Link
AR (1) AR225323A1 (en)
BR (1) BR8005706A (en)
DE (1) DE3040787A1 (en)
FR (1) FR2469060A1 (en)
GB (1) GB2062417A (en)
IT (1) IT1207280B (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4016368A (en) * 1975-12-12 1977-04-05 North Electric Company Framing circuit for digital receiver

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2612324A1 (en) * 1976-03-23 1977-10-06 Siemens Ag CIRCUIT ARRANGEMENT FOR DERIVING SYNCHRONIZING SIGNALS IN PCM RECEIVING DEVICES FROM THE RECEPTION OF PULSE FRAME IDENTIFICATION WORDS
DE2740997C2 (en) * 1977-09-12 1979-09-13 Siemens Ag, 1000 Berlin Und 8000 Muenchen Method for time-division multiplex frame synchronization with the aid of variable synchronization words
NL176420C (en) * 1977-09-29 1985-04-01 Nederlanden Staat SYNCHRONIZER FOR DELIVERING A SYNCHRONIZATION SIGNAL MATCHING WITH A SYNCHRONIZATION SIGN PRESENT IN AN INCOMING DIGITAL SIGNAL.
DE2802975C2 (en) * 1978-01-24 1979-10-18 Siemens Ag, 1000 Berlin Und 8000 Muenchen Method for time division multiplex frame synchronization
DE2811851C2 (en) * 1978-03-17 1980-03-27 Siemens Ag, 1000 Berlin Und 8000 Muenchen Method for frame synchronization of a time division multiplex system
DE2814000C3 (en) * 1978-03-31 1988-02-11 Siemens AG, 1000 Berlin und 8000 München Demultiplex arrangement
DE2826322C2 (en) * 1978-06-15 1987-01-08 Siemens AG, 1000 Berlin und 8000 München Method and circuit arrangement for recognizing special characters of a data signal
DE2842371A1 (en) * 1978-09-28 1980-04-10 Siemens Ag METHOD FOR SYNCHRONIZING TRANSMITTER AND RECEIVER DEVICES
DE2920809A1 (en) * 1979-05-22 1980-11-27 Siemens Ag PCM time multiplex data transmission system - uses synchronisation system with shift register and equaliser with AND=gates and OR=gate
IT1207258B (en) * 1979-10-11 1989-05-17 Sits Soc It Telecom Siemens CIRCUIT PROVISION SUITABLE FOR RECOGNIZING THE WORD OF ALIGNMENT, FOR PARTICULAR APPLICATION IN THE RECEIVING SECTION OF A MULTIPLATOR DIGITAL SIGNALS.

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4016368A (en) * 1975-12-12 1977-04-05 North Electric Company Framing circuit for digital receiver

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
EXBK/68 *

Also Published As

Publication number Publication date
GB2062417A (en) 1981-05-20
IT1207280B (en) 1989-05-17
DE3040787A1 (en) 1981-09-24
BR8005706A (en) 1981-05-19
AR225323A1 (en) 1982-03-15
IT7926859A0 (en) 1979-10-29

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