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FR2428915A1 - METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - Google Patents

METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE

Info

Publication number
FR2428915A1
FR2428915A1 FR7817760A FR7817760A FR2428915A1 FR 2428915 A1 FR2428915 A1 FR 2428915A1 FR 7817760 A FR7817760 A FR 7817760A FR 7817760 A FR7817760 A FR 7817760A FR 2428915 A1 FR2428915 A1 FR 2428915A1
Authority
FR
France
Prior art keywords
interconnection layer
manufacturing
semiconductor device
manufacture
layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7817760A
Other languages
French (fr)
Other versions
FR2428915B1 (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to FR7817760A priority Critical patent/FR2428915A1/en
Publication of FR2428915A1 publication Critical patent/FR2428915A1/en
Application granted granted Critical
Publication of FR2428915B1 publication Critical patent/FR2428915B1/fr
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
    • H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

L'invention concerne la fabrication des circuits intégrés. Dans un circuit intégré à deux couches d'interconnexion, des trous de contact 3 relient la couche d'interconnexion inférieure 1 à la couche d'interconnexion supérieure 2. Pour assurer un bon contact entre les deux couches, on dépose dans les trous de contact un métal capable de réagir avec le métal de la couche d'interconnexion inférieure, ce qui fait disparaître la couche d'oxyde qui est susceptible de se former à la surface de la couche d'interconnexion inférieure. Application à la fabrication des circuits intégrés complexes.The invention relates to the manufacture of integrated circuits. In an integrated circuit with two interconnection layers, contact holes 3 connect the lower interconnection layer 1 to the upper interconnection layer 2. To ensure good contact between the two layers, the contact holes are deposited. a metal capable of reacting with the metal of the lower interconnection layer, thereby removing the oxide layer which is liable to form on the surface of the lower interconnection layer. Application to the manufacture of complex integrated circuits.

FR7817760A 1978-06-14 1978-06-14 METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE Granted FR2428915A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR7817760A FR2428915A1 (en) 1978-06-14 1978-06-14 METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7817760A FR2428915A1 (en) 1978-06-14 1978-06-14 METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE

Publications (2)

Publication Number Publication Date
FR2428915A1 true FR2428915A1 (en) 1980-01-11
FR2428915B1 FR2428915B1 (en) 1982-12-31

Family

ID=9209488

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7817760A Granted FR2428915A1 (en) 1978-06-14 1978-06-14 METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE

Country Status (1)

Country Link
FR (1) FR2428915A1 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0042926A1 (en) * 1980-07-01 1982-01-06 Rockwell International Corporation Aluminum to aluminum ohmic contacts, multilevel interconnections
EP0091870A1 (en) * 1982-04-14 1983-10-19 Commissariat à l'Energie Atomique Method of positioning interconnecting lines at an electrical contact hole of an integrated circuit
FR2542922A1 (en) * 1983-03-18 1984-09-21 Efcis Method of manufacturing integrated circuits with several metallic interconnection layers and circuit produced by this method
FR2550660A2 (en) * 1982-04-14 1985-02-15 Commissariat Energie Atomique Improvement to the method for positioning an interconnection line on an electrical contact hole of an integrated circuit.
EP0139549A1 (en) * 1983-08-12 1985-05-02 Commissariat A L'energie Atomique Method for aligning a connecting line above an electrical contact hole of an integrated circuit

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1806980A1 (en) * 1967-11-15 1969-06-19 Fairchild Camera Instr Co Semiconductor component
US3801880A (en) * 1971-09-09 1974-04-02 Hitachi Ltd Multilayer interconnected structure for semiconductor integrated circuit and process for manufacturing the same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1806980A1 (en) * 1967-11-15 1969-06-19 Fairchild Camera Instr Co Semiconductor component
US3801880A (en) * 1971-09-09 1974-04-02 Hitachi Ltd Multilayer interconnected structure for semiconductor integrated circuit and process for manufacturing the same

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
EXBK/73 *

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0042926A1 (en) * 1980-07-01 1982-01-06 Rockwell International Corporation Aluminum to aluminum ohmic contacts, multilevel interconnections
EP0091870A1 (en) * 1982-04-14 1983-10-19 Commissariat à l'Energie Atomique Method of positioning interconnecting lines at an electrical contact hole of an integrated circuit
FR2525389A1 (en) * 1982-04-14 1983-10-21 Commissariat Energie Atomique METHOD FOR POSITIONING AN INTERCONNECTION LINE ON AN ELECTRIC CONTACT HOLE IN AN INTEGRATED CIRCUIT
FR2550660A2 (en) * 1982-04-14 1985-02-15 Commissariat Energie Atomique Improvement to the method for positioning an interconnection line on an electrical contact hole of an integrated circuit.
US4505030A (en) * 1982-04-14 1985-03-19 Commissariat A L'energie Atomique Process for positioning an interconnection line on an electrical contact hole of an integrated circuit
FR2542922A1 (en) * 1983-03-18 1984-09-21 Efcis Method of manufacturing integrated circuits with several metallic interconnection layers and circuit produced by this method
EP0139549A1 (en) * 1983-08-12 1985-05-02 Commissariat A L'energie Atomique Method for aligning a connecting line above an electrical contact hole of an integrated circuit
US4541892A (en) * 1983-08-12 1985-09-17 Commissariat A L'energie Atomique Process for the positioning of an interconnection line on an electrical contact hole of an integrated circuit

Also Published As

Publication number Publication date
FR2428915B1 (en) 1982-12-31

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Legal Events

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