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FR2428324A1 - Circuits integres a tres grande echelle et leur procede de realisation par alignement automatique de contacts - Google Patents

Circuits integres a tres grande echelle et leur procede de realisation par alignement automatique de contacts

Info

Publication number
FR2428324A1
FR2428324A1 FR7914302A FR7914302A FR2428324A1 FR 2428324 A1 FR2428324 A1 FR 2428324A1 FR 7914302 A FR7914302 A FR 7914302A FR 7914302 A FR7914302 A FR 7914302A FR 2428324 A1 FR2428324 A1 FR 2428324A1
Authority
FR
France
Prior art keywords
integrated circuits
making
scale integrated
automatic contact
contact alignment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7914302A
Other languages
English (en)
Other versions
FR2428324B1 (fr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Boeing North American Inc
Original Assignee
Rockwell International Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rockwell International Corp filed Critical Rockwell International Corp
Publication of FR2428324A1 publication Critical patent/FR2428324A1/fr
Application granted granted Critical
Publication of FR2428324B1 publication Critical patent/FR2428324B1/fr
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/117—Oxidation, selective
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/141—Self-alignment coat gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

L'invention concerne la fabrication de circuits intégrés à très grande échelle Différentes couches sont formées avec des matières ayant des caractéristiques différentes d'attaque chimique si bien qu'une oxydation sélective peut être realisée uniquement sur des parties voulues de la structure, sans que la disposition de caches et le retrait de matière à des emplacements choisis soient nécessaires. Les circuits formés ont une densité et une fiabilité très élevées. Deux ou plusieurs régions peuvent être dopées simultanément Application à la fabrication des mémoires à accès direct et passives.
FR7914302A 1978-06-06 1979-06-05 Circuits integres a tres grande echelle et leur procede de realisation par alignement automatique de contacts Granted FR2428324A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/913,182 US4221044A (en) 1978-06-06 1978-06-06 Self-alignment of gate contacts at local or remote sites

Publications (2)

Publication Number Publication Date
FR2428324A1 true FR2428324A1 (fr) 1980-01-04
FR2428324B1 FR2428324B1 (fr) 1983-12-09

Family

ID=25433011

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7914302A Granted FR2428324A1 (fr) 1978-06-06 1979-06-05 Circuits integres a tres grande echelle et leur procede de realisation par alignement automatique de contacts

Country Status (4)

Country Link
US (1) US4221044A (fr)
JP (1) JPS54162480A (fr)
DE (1) DE2922015A1 (fr)
FR (1) FR2428324A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2533370A1 (fr) * 1982-09-22 1984-03-23 American Micro Syst Procede de fabrication d'un dispositif mos a contacts auto-alignes
EP0087462A4 (fr) * 1981-09-08 1986-03-18 Ncr Corp Procede de fabrication d'une structure de circuits integres.

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4455737A (en) * 1978-05-26 1984-06-26 Rockwell International Corporation Process for and structure of high density VLSI circuits, having self-aligned gates and contacts for FET devices and conducting lines
US4506437A (en) * 1978-05-26 1985-03-26 Rockwell International Corporation Process for and structure of high density VLSI circuits, having self-aligned gates and contacts for FET devices and conducting lines
US4373248A (en) * 1978-07-12 1983-02-15 Texas Instruments Incorporated Method of making high density semiconductor device such as floating gate electrically programmable ROM or the like
US4466172A (en) * 1979-01-08 1984-08-21 American Microsystems, Inc. Method for fabricating MOS device with self-aligned contacts
US4329186A (en) * 1979-12-20 1982-05-11 Ibm Corporation Simultaneously forming fully implanted DMOS together with enhancement and depletion mode MOSFET devices
US4622735A (en) * 1980-12-12 1986-11-18 Tokyo Shibaura Denki Kabushiki Kaisha Method for manufacturing a semiconductor device utilizing self-aligned silicide regions
US4380866A (en) * 1981-05-04 1983-04-26 Motorola, Inc. Method of programming ROM by offset masking of selected gates
JP2812388B2 (ja) * 1988-01-18 1998-10-22 富士通株式会社 Ｓｏｉ半導体装置の製造方法
US4847517A (en) * 1988-02-16 1989-07-11 Ltv Aerospace & Defense Co. Microwave tube modulator
JPH0637317A (ja) * 1990-04-11 1994-02-10 General Motors Corp <Gm> 薄膜トランジスタおよびその製造方法
JP3483644B2 (ja) * 1995-03-07 2004-01-06 松下電器産業株式会社 プロトン伝導体およびプロトン伝導体を用いた電気化学素子
US5907779A (en) * 1996-10-15 1999-05-25 Samsung Electronics Co., Ltd. Selective landing pad fabricating methods for integrated circuits
DE19845792A1 (de) * 1998-09-21 2000-03-23 Inst Halbleiterphysik Gmbh Verfahren zur Erzeugung einer amorphen oder polykristallinen Schicht auf einem Isolatorgebiet
WO2000039858A2 (fr) 1998-12-28 2000-07-06 Fairchild Semiconductor Corporation Transistor mos a effet de champ a portee isolee, a double diffusion et grille metallique, a vitesse de commutation accrue et fuite de courant tunnel de grille reduite
US7078296B2 (en) 2002-01-16 2006-07-18 Fairchild Semiconductor Corporation Self-aligned trench MOSFETs and methods for making the same
US7338888B2 (en) * 2004-03-26 2008-03-04 Texas Instruments Incorporated Method for manufacturing a semiconductor device having a silicided gate electrode and a method for manufacturing an integrated circuit including the same
JP4747262B2 (ja) * 2004-12-27 2011-08-17 東洋製罐株式会社 注出容器及びその詰替用の袋状容器
JP2006339343A (ja) 2005-06-01 2006-12-14 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
JP5451813B2 (ja) * 2012-05-08 2014-03-26 サーモス株式会社 液体容器の注ぎ口

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2125462A1 (fr) * 1971-02-16 1972-09-29 Texas Instruments Inc
US3913211A (en) * 1973-01-15 1975-10-21 Fairchild Camera Instr Co Method of MOS transistor manufacture
US3958323A (en) * 1975-04-29 1976-05-25 International Business Machines Corporation Three mask self aligned IGFET fabrication process
FR2340619A1 (fr) * 1976-02-04 1977-09-02 Radiotechnique Compelec Perfectionnement au procede de fabrication de dispositifs semiconducteurs et dispositifs ainsi obtenus
FR2351502A1 (fr) * 1976-05-14 1977-12-09 Ibm Procede de fabrication de transistors a effet de champ a porte en silicium polycristallin auto-alignee avec les regions source et drain ainsi qu'avec les regions d'isolation de champ encastrees
US4110776A (en) * 1976-09-27 1978-08-29 Texas Instruments Incorporated Semiconductor integrated circuit with implanted resistor element in polycrystalline silicon layer

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51112187A (en) * 1975-03-28 1976-10-04 Matsushita Electric Ind Co Ltd Processing method of semiconductor equipment

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2125462A1 (fr) * 1971-02-16 1972-09-29 Texas Instruments Inc
US3921282A (en) * 1971-02-16 1975-11-25 Texas Instruments Inc Insulated gate field effect transistor circuits and their method of fabrication
US3913211A (en) * 1973-01-15 1975-10-21 Fairchild Camera Instr Co Method of MOS transistor manufacture
US3936858A (en) * 1973-01-15 1976-02-03 Fairchild Camera And Instrument Corporation MOS transistor structure
FR2325186A1 (fr) * 1973-01-15 1977-04-15 Fairchild Camera Instr Co Procede de fabrication de transistor mos et structure de transistor resultante
US3958323A (en) * 1975-04-29 1976-05-25 International Business Machines Corporation Three mask self aligned IGFET fabrication process
FR2340619A1 (fr) * 1976-02-04 1977-09-02 Radiotechnique Compelec Perfectionnement au procede de fabrication de dispositifs semiconducteurs et dispositifs ainsi obtenus
FR2351502A1 (fr) * 1976-05-14 1977-12-09 Ibm Procede de fabrication de transistors a effet de champ a porte en silicium polycristallin auto-alignee avec les regions source et drain ainsi qu'avec les regions d'isolation de champ encastrees
US4110776A (en) * 1976-09-27 1978-08-29 Texas Instruments Incorporated Semiconductor integrated circuit with implanted resistor element in polycrystalline silicon layer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0087462A4 (fr) * 1981-09-08 1986-03-18 Ncr Corp Procede de fabrication d'une structure de circuits integres.
FR2533370A1 (fr) * 1982-09-22 1984-03-23 American Micro Syst Procede de fabrication d'un dispositif mos a contacts auto-alignes

Also Published As

Publication number Publication date
FR2428324B1 (fr) 1983-12-09
DE2922015A1 (de) 1979-12-13
JPS54162480A (en) 1979-12-24
US4221044A (en) 1980-09-09

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