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FR2041471A5 - Multi-layer circuits with thermosetting - dielectric - Google Patents

Multi-layer circuits with thermosetting - dielectric

Info

Publication number
FR2041471A5
FR2041471A5 FR6913191A FR6913191A FR2041471A5 FR 2041471 A5 FR2041471 A5 FR 2041471A5 FR 6913191 A FR6913191 A FR 6913191A FR 6913191 A FR6913191 A FR 6913191A FR 2041471 A5 FR2041471 A5 FR 2041471A5
Authority
FR
France
Prior art keywords
dielectric
thermosetting
layer
circuits
connections
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR6913191A
Other languages
French (fr)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
INFORMATIQUE CIE INTERNA
Original Assignee
INFORMATIQUE CIE INTERNA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by INFORMATIQUE CIE INTERNA filed Critical INFORMATIQUE CIE INTERNA
Priority to FR6913191A priority Critical patent/FR2041471A5/en
Application granted granted Critical
Publication of FR2041471A5 publication Critical patent/FR2041471A5/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/002—Etching of the substrate by chemical or physical means by liquid chemical etching
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0023—Etching of the substrate by chemical or physical means by exposure and development of a photosensitive insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0137—Materials
    • H05K2201/0166—Polymeric layer used for special processing, e.g. resist for etching insulating material or photoresist used as a mask during plasma etching
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/06—Lamination
    • H05K2203/068—Features of the lamination press or of the lamination process, e.g. using special separator sheets
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

Circuits are prepd. by applying to each conducting layer with the exception of the final layer a thin film of a gelled thermosetting dielectric leaving holes for connecting the conductors, and heating the assembly to harden the dielectric in situ. After depositing the metallic layers, a layer of a thermosetting gel is applied to each. The dielectric may be of epoxy resin and the connections formed by gravure, removing exposed parts of the resin before final hardening. Connections between the metallic circuits are more, simply formed.
FR6913191A 1969-04-25 1969-04-25 Multi-layer circuits with thermosetting - dielectric Expired FR2041471A5 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR6913191A FR2041471A5 (en) 1969-04-25 1969-04-25 Multi-layer circuits with thermosetting - dielectric

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR6913191A FR2041471A5 (en) 1969-04-25 1969-04-25 Multi-layer circuits with thermosetting - dielectric

Publications (1)

Publication Number Publication Date
FR2041471A5 true FR2041471A5 (en) 1971-01-29

Family

ID=9033068

Family Applications (1)

Application Number Title Priority Date Filing Date
FR6913191A Expired FR2041471A5 (en) 1969-04-25 1969-04-25 Multi-layer circuits with thermosetting - dielectric

Country Status (1)

Country Link
FR (1) FR2041471A5 (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2342407A1 (en) * 1972-08-25 1974-03-07 Ciba Geigy Ag PROCESS FOR MANUFACTURING PRINTED MULTI-LAYER CIRCUITS
EP0077546A3 (en) * 1981-10-19 1984-05-16 Tokyo Shibaura Denki Kabushiki Kaisha Thermal recording device
EP0275686A1 (en) * 1986-12-19 1988-07-27 Prestwick Circuits Limited Improved multi-layer printed circuit boards, and methods of manufacturing such boards
WO2004004430A1 (en) * 2002-06-27 2004-01-08 Ppg Industries Ohio, Inc. Process for creating holes in polymeric substrates
WO2004004433A1 (en) * 2002-06-27 2004-01-08 Ppg Industries Ohio, Inc. Process for creating vias for circuit assemblies
US7000313B2 (en) 2001-03-08 2006-02-21 Ppg Industries Ohio, Inc. Process for fabricating circuit assemblies using electrodepositable dielectric coating compositions
US7002081B2 (en) 2002-06-27 2006-02-21 Ppg Industries Ohio, Inc. Single or multi-layer printed circuit board with recessed or extended breakaway tabs and method of manufacture thereof

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2342407A1 (en) * 1972-08-25 1974-03-07 Ciba Geigy Ag PROCESS FOR MANUFACTURING PRINTED MULTI-LAYER CIRCUITS
FR2197301A1 (en) * 1972-08-25 1974-03-22 Ciba Geigy Ag
EP0077546A3 (en) * 1981-10-19 1984-05-16 Tokyo Shibaura Denki Kabushiki Kaisha Thermal recording device
EP0275686A1 (en) * 1986-12-19 1988-07-27 Prestwick Circuits Limited Improved multi-layer printed circuit boards, and methods of manufacturing such boards
US7000313B2 (en) 2001-03-08 2006-02-21 Ppg Industries Ohio, Inc. Process for fabricating circuit assemblies using electrodepositable dielectric coating compositions
WO2004004430A1 (en) * 2002-06-27 2004-01-08 Ppg Industries Ohio, Inc. Process for creating holes in polymeric substrates
WO2004004433A1 (en) * 2002-06-27 2004-01-08 Ppg Industries Ohio, Inc. Process for creating vias for circuit assemblies
US6824959B2 (en) 2002-06-27 2004-11-30 Ppg Industries Ohio, Inc. Process for creating holes in polymeric substrates
US7002081B2 (en) 2002-06-27 2006-02-21 Ppg Industries Ohio, Inc. Single or multi-layer printed circuit board with recessed or extended breakaway tabs and method of manufacture thereof
US7159308B2 (en) 2002-06-27 2007-01-09 Ppg Industries Ohio, Inc. Method of making a circuit board

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Legal Events

Date Code Title Description
CD Change of name or company name
TP Transmission of property
ST Notification of lapse