FI98665C - Signal program - Google Patents

Abstract

The programmer producing binary output signals (5) in response to a clock signal (R) identifying time intervals, each output signal starting and terminating within distinct time intervals, comprises a memory (1) provided with a start location having an allocated address and an end location having an allocated address for each output signal (S), means of reading making it possible to read the digital values in these locations, means of control (2, 5) determining the operation of the means of reading with the aid of an address generator in such a way that all the locations are read during each of the time intervals, means of comparison (3) producing an equality signal (E) when a first field of a location has the same value as a first field of the time interval in which the reading takes place, and means of decoding (4) producing or interrupting the output signal (S) which corresponds to the location for which the said equality signal is produced according to whether the latter is respectively a start location or an end location. <IMAGE>

Description

. 98665

Signal programmer

The present invention is directed to a software device that generates binary output signals under the control of a synchronous signal.

5 Software devices are devices whose output signals control the operation of different hardware according to a certain sequence. This sequence is usually stored in the program device itself and the sequence proceeds according to the rate determined by the external clock signal.

In the first known solution, in which the clock signal is a clock signal, a first subtraction counter preloaded with a pre-loaded value and a second subtraction counter preloaded with a final value are used for each controlled device, all counters receiving this clock signal. The relevant output signal starts when the first counter reaches zero and ends when the second counter reaches zero.

In another known solution, in which the synchronous signal is a digital signal provided by a counter which is itself incremented by a clock signal, there are first and second comparators for each controlled device, which compare the initial value and the final value with the value of the synchronous signal. The corresponding output signal starts when the first comparator detects a similarity at its inputs, and the signal ends when the second comparator detects a similarity, respectively.

These two solutions are well suited when the programmer generates a few output signals. As the number of devices to be controlled increases, the number of modules associated with the output signals (comparator, counter) increases as a result, and a large number of embryonic cells, such as logic ports, are required to implement the program device. The result is an increase in the silicon area required for its integration, an increase in its energy consumption and thus an increase in its cost.

The object of the present invention is thus a program device for generating output signals controlled by a synchronous signal, which has 5 fewer embryonic cells, already when the number of output signals is a few units larger.

The software according to the invention, which generates binary output signals under the control of a time-varying synchronous signal so that each output signal starts and ends during certain time slots, is characterized by a memory with an address-indicated start memory location and address-indicated end memory location for each output signal. reading the digital values 15 in these memory locations, control means for determining the operation of the reading means by the address generator so that all memory locations are read during each time slot, comparison means giving an equality signal when the first field of the memory location has the same value as the time slot 20 in the first field, and decoding means for generating or interrupting an output signal corresponding to the memory location for which the identity signal is Ann depending on whether the memory location is an initial memory location or an end memory location.

In one embodiment of a program that generates binary output signals under the control of a clock signal, the comparison means generates an equality signal if, in addition, a second value called periodicity value is specified in the second field of this memory location.

In a program device which generates binary output signals under the control of a synchronous signal, the decoding means preferably further comprises a synchronization register so that all output signals which are changing state in said. 98665 3 term, do it synchronously.

In a special form of a program device that generates binary output signals under the control of a clock signal, the clock signal comes from the first counter.

5 When a program that generates binary output signals controlled by a synchronous signal is a read-write memory, the device further includes writing means for writing digital values to this memory and control means for generating a control signal for controlling the writing means or reading means.

In a program that generates binary output signals controlled by a synchronous signal, the control means further includes an address selector that sets the memory to either the address or write address indicated by the address generator 15 depending on whether the control signal controls readers or writers.

In one embodiment of a program that generates binary output signals under the control of a clock signal, the control means receives the clock signal, the address generator including a second counter that receives this clock signal and addresses the first field of the value indicated by this second counter.

In a program device which generates binary output signals 25 controlled by a synchronous signal, the control means further determines the value of the control signal as a function of the value of the second field of the second counter.

In a program that generates binary output signals under the control of a clock signal, the frequency of the clock signal and the capacity of the second counter are further adapted so that the second counter can perform a complete cycle 98665 4 during each time slot.

According to a further feature of the software device which generates the binary output signals under the control of the synchronous signal, the decoding means comprise a validity register which gives the output signal only if the qualification information for it exists.

Various objects and features of the invention will now become more apparent from the description of non-limiting embodiments of the invention with reference to the accompanying drawings, in which: Fig. 1 is a diagram of a program device generating binary output signals controlled by a synchronous signal, Fig. 2 is a diagram of a program memory reference means, Fig. 4 is a diagram of software decoding means.

The same parts which may appear in the different figures are denoted by the same reference numerals.

The software device of the invention shown in Fig. 1 is adapted to receive a clock signal R of a digital nature, which identifies the time slots in an agreed manner. The programmer generates two-mode output signals S.

The software device mainly comprises a memory 1 in which information related to different output signals is stored, control means 2 for this memory, comparison means 3 for detecting similarity between the memory information and the time slot, and decoding means 4 for generating or disconnecting the output signal S when 98665 5. the comparison means has identified the information about the output signal.

Memory 1 is can be of any type. It can be, in particular, a ROM-type read-only memory or a PROM-type 5 programmable memory. In the following embodiment, the memory is a RAM-type read-write memory. It is thus adapted to receive a read signal RD, which sets it to read mode, and a write signal WR, which sets it to read mode. These two signals are generated by the analysis unit 5, which receives the control signal C, the nature of which will be explained in detail later.

The memory contains the memory locations identified by the address, the number of which is defined here as 2n. The memory locations are adapted to contain digital values consisting of k 15 bits. The memory is thus arranged to receive the input signal Di on the conductor of the address signal A and k on n conductors and to output the output information Do on the same conductor k.

In the read mode, the memory outputs the digital value stored in the memory location identified by the address signal A as the output data Do, while in the write mode, the memory writes the input data Di to this memory location.

Each output signal is associated with two memory locations, the first corresponding to the beginning of this signal and the second to its end. Thus, it can be assumed that all 25 memory locations in the memory are associated with an output signal. The assumption intended to clarify this explanation is not to be construed as limiting the invention, which is entirely useful in the opposite case.

The synchronous signal R sequentially identifies time slots that each 30 can Touch a change in the state of one output signal if the time slot value is the same as the value contained in one of the two memory locations assigned to that signal. The control means 2 of this memory 98665 6, shown in Fig. 2, are arranged so that the digital values written to all memory locations can be assigned during each time interval. The control means include an address generator 21, 5 which generates a read address signal Ar which successively receives all values between 0 and 2 "-1 corresponding to the addresses of all memory locations in the memory. The generator may be, for example, a counter incremented by the clock signal Ck.

The control means 2 are likewise adapted to allow digital values to be written to memory during each time interval. To do this, the counter capacity is greater than the number of addresses.

For example, the counter capacity may be set equal to 2n + 2 "'1, which requires the counter to have n + 1 bit output. The most significant bit, i.e., the bit indicating values greater than or equal to 2n, is used to generate the control signal C, which when it is one or zero, determines the write mode and the read mode, respectively, 20. The memory control means 2 further includes a multiplexer 22 which generates an address signal A having the same value as the read address signal Ar or the write address signal Aw received by the software, control signal C zero or one.

Thus, during the full period of the counter 21, all memory locations of the memory 1 are selected in read mode by their addresses determined by the field corresponding to the least significant bit of the counter n, and then when the most significant bit is one, the input data Di is written to the memory locations identified by the write address signal. If the clock signal Ck is periodic and its frequency is such that the counter period lasts exactly one time slot, two-thirds of this time slot is used for reading and the remaining third for writing.

98665 7

The memory 1 control means 2 described above are shown by way of example and the invention does not exclude other embodiments.

In particular, the means enabling writing during the time slot are not absolutely necessary for the operation of the invention, especially if the memory is a read-only memory. It is also possible to use other means for writing digital values either during time intervals or during periods when the program device is not performing its control function of the output signal S.

The software device further comprises comparison means 3 which receive the synchronous signal R consisting of k bits and likewise the output data Do of the memory 1 consisting of k bits. In the first form, the comparison means generates an equality signal E when the time slot and the output data are identical, and the comparison means thus consists of a simple equality comparator. The values to be compared can be divided into fields, in which case the fields to be examined consist of the values as a whole. In a more advanced form, shown in Figure 3, the comparator means form the identity data Do and the time slot in the case of partial identity, i.e. one field identity of these values. In the example shown, they comprise 16 bits (k = 16). The output information and the time slot each contain a first field consisting of the 11 least significant bits (top in the figure) and a second field consisting of the 5 most significant bits (bottom in the figure). The equality signal is generated if the first fields are equal and if the periodicity signal P exists. This signal 30 is generated by the periodicity detector 31 when the second fields are equal or when the second field of the output data has a certain special value called the periodicity value. The periodicity detector includes five EXCLUSIVE OR-NOT gates 32, each of which receives one bit of the second field of the time slot and output information 35 and then outputs one in the case of parity. The outputs of these five gates are fed to the inputs of the first AND-NO gate 33, which then gives zero in the case where the second fields are equal. The detector further includes a second AND-NOT gate 34, which 5 gives zero if and only if the five bits of the second field of the output data are ones, that is, if the periodicity value P consists of five ones. The periodicity signal P is provided by a third AND-NO gate 35, which receives the outputs of two other gates 33, 34 of the same type.

10 The comparison of the first fields of the output data and the time slot is done in the same way, the bits of both are compared in pairs by means of EXCLUSIVE OR-NOT gates 32. The three AND-NO gates 36 each receive a portion of the outputs of the previous ports, with one of these JA-E1 gates receiving an additional periodicity signal P. If the first fields are identical and if the periodicity signal P also exists and only in this case, the three AND-NO the outputs of gate 36 are then zero. The OR gate 37 generates an equality signal E from these three outputs 20.

The synchronous signal is preferably provided by a counter, although this is not necessary according to the invention. In this case, the counter incremented by the clock clock triggers the generation of an equality signal E for each memory location selected by the periodicity value of the second field 25 at a repetition frequency corresponding to the pulse 211 of the clock clock f2. In a preferred solution, the frequency fj of the counter 21 of the control means 2 is set to correspond to the capacity of this same counter as well.

The comparison means 3 described above, and in particular the means for generating the similarity signal repeatedly using the periodicity value, are shown by way of example and are not to be construed as limiting the invention.

98665 9

The decoding means 4 forming the last member of the program device will be explained below with reference to Fig. 4. The decoding means comprise a decoder 40 controlled by the similarity signal E, which is connected on the first connection 5 to a first register 41 having one bit for each memory location of the memory 1, for example 2n. Decoder 40 sets the bit of the first register corresponding to the memory location to be read to one when an equality signal exists.

The first register 41 is connected by a second connection L2 to a second register 42 with 2n_1 bits. Each bit of this register associated with the output signal is set to one when the 41 bits of the first register corresponding to the start memory location of this output signal are one, and the 15 bits are set to zero when the 41 bits of the first register corresponding to the end memory location of this output signal are one. The second register 42 may optionally be synchronized to the synchronous signal R and is therefore referred to as a synchronization register.

The means for resetting the first register 41, not shown in the figure, are adapted to reset to zero all the bits of this register when the second register 42 has taken them into account. These means are periodically controlled by the frequency of the synchronous signal, for example at the beginning or end of each time slot.

In an optional implementation, a third register 43 with 2n_1 bits, each associated with one output signal, receives information from the second register 42 via the third connection L3.

The output signal S is generated if the bits corresponding to it in the second register 42 and the third register 43 are ones. This third register can advantageously be used to determine the validity of each output signal individually and is therefore called a validity register.

98665 10

For example, when memory 1 is set to voltage, the digital values it contains are vague. Therefore, it makes sense to make the output signal valid only when it is actually written to this memory.

When using a memory with 2n k-bit words, the described program device can control the 2n_1 output signal according to a sequence of 2k steps. It also allows certain signals to be controlled periodically during this sequence 10.

In a slightly different form of the program device, the same address indicates the start and end memory locations of the output signal. The comparison means 3 are constructed to compare the two memory locations and to generate two signals for the decoding means 15 so that they can determine whether this is the beginning or the end of the output signal identified by this address. This modification, which can be easily carried out by a person skilled in the art, is not explained in detail.

Claims (10)

98665 11 A program device which generates binary output signals (S) under the control of a time-varying synchronous signal (R) such that each output signal begins and ends during predetermined time slots, characterized in that it has a memory (1) with each output signal (S). ), the address-indicated initial memory location and the address-indicated final memory location, reading means for reading the digital values 10 in these memory locations, control means (2, 5) for determining the operation of the reading means by the address generator so that all memory locations are read during each time interval, reference means (3 ), which provide an equivalence signal (E) when the first field of the memory location has the same value 15 as the first field of the time slot in which the reading occurs, and decoding means (4) which generates or interrupts an output signal (S) corresponding to the memory location for which your equivalence the signal is given according to whether the memory location is an initial memory location or an end memory location. Program device according to claim 1, which generates binary output signals under the control of a synchronous signal (R), characterized in that the comparison means (3) generate an equivalence signal (E) if a second field of this memory location also has a value called periodicity value. Program device according to claim 1 or 2, which generates binary output signals under the control of a synchronous signal, characterized in that the decoding means (4) preferably further comprise a synchronization register (42) such that all output signals (S) changing state in said time slot do so synchronously. Program device according to one of the preceding claims, which generates binary output signals 98665 12 under the control of a synchronous signal (R), characterized in that the synchronous signal (R) comes from a first counter. Program device according to one of the preceding claims, which generates binary output signals 5 under the control of a synchronous signal (R), characterized in that when the memory (1) is a read-write memory, the device further comprises writing means enabling digital values to be written to this memory. the means (2) generate a control signal (C) for controlling the writing means or the reading means. A program device generating binary output signals controlled by a synchronous signal (R) according to claim 5, characterized in that the control means further comprises an address selector (22) which sets the memory to either the address (Ar) or the write address (Aw) indicated by the address generator (21), depending on whether the control signal (C) controls the reading means or the writing means. Program device according to claim 6, generating binary output signals under the control of a synchronous signal (R) 20, characterized in that when the control means (2) receive a clock signal (Ck), the address generator (21) includes a second counter which receives this clock signal and assigns an address (Ar) the first field of the value indicated by this second counter. Program device according to claim 7, which generates binary output signals controlled by a synchronous signal (R), characterized in that the control means (2) further determine the value of the control signal (C) as a function of the value of the second field of the second counter. A program device according to claim 8, which generates binary output signals controlled by a synchronous signal (R), characterized in that the frequency of the clock signal (Ck) 98665 13 and the capacity of the second counter (21) are further arranged so that the second counter can perform a complete cycle during each time slot. . Program device according to one of the preceding claims, which generates binary output signals under the control of a synchronous signal (R), characterized in that the decoding means (4) comprise a validation register (43) which provides an output signal only if valid qualifying information exists. 15