SU746488A1 - Interface - Google Patents

Description

(54) DEVICE FOR PAIRING

one

The invention relates to the field. computing technology and can be used to match data rates.

There are known devices for interfacing U, containing memory on shift registers, switches, distributors, registers, adder, comparison circuits and a control node and performing functions of matching data rates.

However, such devices are complex, and it is also impossible to use standard integrated memory modules as storage elements.

The closest to the invention to the technical essence is a device for interface 2, which contains a memory, a ring marker register connected to the outputs of the corresponding inputs of the decoder, the first and second groups of outputs of which are connected respectively to the first and second groups of memory control inputs, the information inputs and outputs of which are the corresponding information inputs and outputs of the device, and the AND element connected by the inputs with the corresponding

the outputs of the first group of the decoder, and the output with the first control output of the device.

The disadvantage of this device is low speed due to the fact that the reading of the next word from the memory cannot be performed immediately by the output clock, but only some time after the next synchronization pulse, which clocks the recording. In this case, the speed of reading information. Information can not be higher than the write frequency.

15 In addition, the restriction on the type of storage elements on which a memory can be built, which is expressed in the impossibility of using standard cheap integral memory elements with random sampling, limits the scope of application of the device.

The aim of the invention is to improve the speed of the device.

The goal is achieved by

25 that two counters are introduced into the proposed device, switches according to the number of memory address inputs and an OR element, the output of each switch is connected to the corresponding address input

30 memories, the first and second inputs of the switches are connected respectively to the outputs of the first and second counters whose overflow outputs are connected to the first and second control inputs of the ring marker register respectively, and the inputs to the first and second control inputs of the device, respectively. . The outputs of the second group of outputs of the decoder are connected to the corresponding inputs of the OR element, the output of which is the second control output of the device, In addition, the memory contains n IL elements and a matrix of n rows and K columns: e, g. commemorating M-paired elements, tf than informational output and input of the memorizing element of the i-th row (i, connect, respectively, via the OR element to the i-th output and the memory, address, first and second inputs of the storage element of the Jth column (, K) are connected respectively to - th address and control inputs from the first and second groups of control memory inputs. The drawing shows the structural diagram of the device. It contains memory 1, decoder 2, ring marker register 3, switches 4 / first counter 5, second counter b, element And 7, and elements OR 8, group 9 of memory adres bus 1, first group 10 decoder outputs (zipissi preparation), second group 11 decoder outputs (read preparation), group 12 address buses of counter 5, group 13 address buses of counter b, first 14 control input of the device (write gating), second 15 control input of the device (reading gating), overflow output 16 of the counter 5 (write offset), counter 17 overflow of the output b (read offset), first control output of the device 18 (blocking source), information inputs 19 and out rows 20 and second device councils l yuschy input device 21. Memory 1 contains the matrix of the dyno-typeNI storage modules with random access (for example, Mx.1 bits with embedded decoders). In,. , and n elements OR, denoted by 1, - In Decoder 2 contains two groups of logical three-input elements AND, and is intended to decipher the location of the two borders between a group of nui groups of units. located in register 3, as well as for switching switches and memory modules from write to read mode, the control input of the ring marker register 3 is connected to the overflow output 16 of counter 5, is used to enter the unit to the right of boundary 1-O, and The input input connected to the overflow output 17 of the counter b is for entering zero to the right of the border in register 3. The device works as follows. In the initial state, all bits of register 3 are set to O, with the exception of one. At the same time, the combination of the units of the one unit and two zeros located in the register is decrypted by the corresponding three-input element AND of the decoder 2 as a signal to prepare the record (for example, at output 10, -3) into the cells of the 1 pin modules 1: i. The same signal connects to the address inputs of these output counter modules 5. The first word arriving at information input 19 and gated by the clock input of control input 14 is entered into the first cell of the selected modules Switched by the same Synchronous pulse som next state counter 5 prepares the entry of the second input word to the second cell, etc. before filling all. x M cells of the third column storage modules,. . . At the moment when the modules are filled, the counter 5 will overflow and will be in the zero state, and the overflow signal from output 16 will go to register 3, will cause another unit to be inserted into the next bit to the first one from the one that was initially in register 3 there will be two subunits located. The combination of the newly recorded unit and the two following zeros is decrypted by another three-element element of the decoder 2 as a signal for preparing the recording on output 10 to the modules of the fourth memory column 1. ... X As the signal preparing the recording passed from output 10 to the output 10 of the decoder 2, the output of the counter 5 is connected to the address inputs of the modules of the fourth line through the switch 4 and the words that come to the information input 19 again will be sequentially written into the cells of these modules until the next overflow of the counter 5 and the first Signals at the outputs of the first group 10 of the decoder 2, the recording of information in other neighboring modules is similar. Immediately after filling in the modules of the third column, one zero and two decoding units located in register 3 are cozied with the corresponding three-input element And decoder 2 at the third output of the second group of outputs 11J as a read-ready signal from these modules. Since the reading address counter 6 is in zero position, the first word will be read into the information receiver at the first module address of the third column, and each reading clock received from the receiver at the second control input 15 prepares the address of the next cell of these modules the moment of reading all the words of the overflow of the counter 6,

The overflow impulse of counter b from output 17 enters the input of register 3 and writes a zero to the right of the group of zeros to the place of the original unit. The space zero and two units located in this register are interpreted by -decoding 2 as a read preparation signal from the previously filled modules of the fourth line as described above.

For a more reliable operation of the device when the memory is full, the And 7 element generates a signal issued to the first control output 15. and serving to block the input of information from the source.

To avoid loss of information, memory 1 is read only if there is a signal at the second control output 21, which is produced by the element OR 8,

Thus, the device allows independent recording and reading of information from the memory, which improves its speed.

In addition, the storage capacity of a device can be quite simply changed without changing its structure by eliminating or adding storage modules together with the corresponding switch, part of the decoder, and part of the ring marker register.

Claims (1)

1. An interface device containing a memory, a ring marker register connected to the outputs with the corresponding inputs of the decoder, the first and second groups of outputs of which are connected respectively to the first and second group of control inputs of the memory, whose information inputs and outputs are the corresponding Ivl and information inputs 5 and the device outputs, and the element And connected to the inputs with the corresponding outputs of the first group of the decoder, and the output with the first control output of the device, distinguish it from the fact that The purpose of improving the speed of the device is that two counters are introduced into it, switches according to the number of address inputs of the device and the OR element, and the output of each switch is connected to the corresponding 5 address memory input, the first and second inputs of the switches are connected respectively to the outputs of the first and second counters, the overflow outputs of which are connected respectively to the first and second control inputs of the ring marker register, and the inputs to the first and second control inputs of the device , the outputs of the second group of outputs of the decoder are connected to the corresponding inputs of the OR element, the output of which is the second control output of the device, 2, The device according to claim 1, in the case where the memory contains n OR elements and a matrix of n rows and K columns of storing M-bit elements, the information output and the input for remembering 5 i-source elements (, n) are connected respectively via the i-th element OR to the x-th output and 1st memory input, address, first and second inputs of the storage element of the j-ro column Q (, K) are connected respectively to the j-th address and control inputs from the first and second groups of control memory inputs. Sources of information taken into account in the examination 1, USSR Copyright Certificate No. 2166167 / 18-24, Cl, G 06 F 3/04, 1975, 2, USSR author's certificate No. 488202, class G 06 F 3/04, 1973 (prototype),