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FI974020A0 - Optimization of the resource and the packet processor system - Google Patents

Optimization of the resource and the packet processor system

Info

Publication number
FI974020A0
FI974020A0 FI974020A FI974020A FI974020A0 FI 974020 A0 FI974020 A0 FI 974020A0 FI 974020 A FI974020 A FI 974020A FI 974020 A FI974020 A FI 974020A FI 974020 A0 FI974020 A0 FI 974020A0
Authority
FI
Finland
Prior art keywords
optimization
resource
processor system
packet processor
packet
Prior art date
Application number
FI974020A
Other languages
Finnish (fi)
Inventor
Jari Korhonen
Jyri Suvanen
Matti Lehtimaeki
Original Assignee
Nokia Telecommunications Oy
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nokia Telecommunications Oy filed Critical Nokia Telecommunications Oy
Priority to FI974020A priority Critical patent/FI974020A0/en
Publication of FI974020A0 publication Critical patent/FI974020A0/en
Priority to AU95439/98A priority patent/AU9543998A/en
Priority to PCT/FI1998/000816 priority patent/WO1999021326A2/en

Links

FI974020A 1997-10-21 1997-10-21 Optimization of the resource and the packet processor system FI974020A0 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
FI974020A FI974020A0 (en) 1997-10-21 1997-10-21 Optimization of the resource and the packet processor system
AU95439/98A AU9543998A (en) 1997-10-21 1998-10-20 Resource optimization in a multiprocessor system for a packet network
PCT/FI1998/000816 WO1999021326A2 (en) 1997-10-21 1998-10-20 Resource optimization in a multiprocessor system for a packet network

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FI974020A FI974020A0 (en) 1997-10-21 1997-10-21 Optimization of the resource and the packet processor system

Publications (1)

Publication Number Publication Date
FI974020A0 true FI974020A0 (en) 1997-10-21

Family

ID=8549773

Family Applications (1)

Application Number Title Priority Date Filing Date
FI974020A FI974020A0 (en) 1997-10-21 1997-10-21 Optimization of the resource and the packet processor system

Country Status (3)

Country Link
AU (1) AU9543998A (en)
FI (1) FI974020A0 (en)
WO (1) WO1999021326A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8782287B2 (en) 2001-12-21 2014-07-15 Agere Systems Llc Methods and apparatus for using multiple reassembly memories for performing multiple functions

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06132974A (en) * 1992-10-20 1994-05-13 Toshiba Corp Buffer for packet disassemble
US5428609A (en) * 1994-01-03 1995-06-27 At&T Corp. STM-to-ATM converters
EP0763915B1 (en) * 1995-09-18 2006-03-08 Kabushiki Kaisha Toshiba Packet transfer device and method adaptive to a large number of input ports
US5838994A (en) * 1996-01-11 1998-11-17 Cisco Technology, Inc. Method and apparatus for the dynamic allocation of buffers in a digital communications network
US5765032A (en) * 1996-01-11 1998-06-09 Cisco Technology, Inc. Per channel frame queuing and servicing in the egress direction of a communications network

Also Published As

Publication number Publication date
WO1999021326A3 (en) 1999-07-29
AU9543998A (en) 1999-05-10
WO1999021326A2 (en) 1999-04-29

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Legal Events

Date Code Title Description
FD Application lapsed