AU9543998A - Resource optimization in a multiprocessor system for a packet network - Google Patents

Resource optimization in a multiprocessor system for a packet network

Info

Publication number: AU9543998A
Authority: AU; Australia
Prior art keywords: packet network; multiprocessor system; resource optimization; optimization; resource
Prior art date: 1997-10-21
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Abandoned

Application number

AU95439/98A

Inventor

Jari Korhonen

Matti Lehtimaki

Jyri Suvanen

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

Nokia Oyj

Original Assignee

Nokia Telecommunications Oy

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

1997-10-21

Filing date

1998-10-20

Publication date

1999-05-10

1998-10-20 Application filed by Nokia Telecommunications Oy filed Critical Nokia Telecommunications Oy

1999-05-10 Publication of AU9543998A publication Critical patent/AU9543998A/en

Status Abandoned legal-status Critical Current

Classifications

- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
- H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
- H04Q11/0478—Provisions for broadband connections
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5629—Admission control
- H04L2012/5631—Resource management and allocation
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5638—Services, e.g. multimedia, GOS, QOS
- H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
- H04L2012/5652—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly

Landscapes

Engineering & Computer Science (AREA)
Computer Networks & Wireless Communication (AREA)
Data Exchanges In Wide-Area Networks (AREA)

AU95439/98A 1997-10-21 1998-10-20 Resource optimization in a multiprocessor system for a packet network Abandoned AU9543998A (en)

Applications Claiming Priority (3)

Application Number	Priority Date	Filing Date	Title
FI974020A FI974020A0 (en)	1997-10-21	1997-10-21	Optimization of the resource and the packet processor system
FI974020		1997-10-21
PCT/FI1998/000816 WO1999021326A2 (en)	1997-10-21	1998-10-20	Resource optimization in a multiprocessor system for a packet network

Publications (1)

Publication Number	Publication Date
AU9543998A true AU9543998A (en)	1999-05-10

Family

ID=8549773

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
AU95439/98A Abandoned AU9543998A (en)	1997-10-21	1998-10-20	Resource optimization in a multiprocessor system for a packet network

Country Status (3)

Country	Link
AU (1)	AU9543998A (en)
FI (1)	FI974020A0 (en)
WO (1)	WO1999021326A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US8782287B2 (en)	2001-12-21	2014-07-15	Agere Systems Llc	Methods and apparatus for using multiple reassembly memories for performing multiple functions

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
JPH06132974A (en) *	1992-10-20	1994-05-13	Toshiba Corp	Buffer for packet disassemble
US5428609A (en) *	1994-01-03	1995-06-27	At&T Corp.	STM-to-ATM converters
EP0763915B1 (en) *	1995-09-18	2006-03-08	Kabushiki Kaisha Toshiba	Packet transfer device and method adaptive to a large number of input ports
US5838994A (en) *	1996-01-11	1998-11-17	Cisco Technology, Inc.	Method and apparatus for the dynamic allocation of buffers in a digital communications network
US5765032A (en) *	1996-01-11	1998-06-09	Cisco Technology, Inc.	Per channel frame queuing and servicing in the egress direction of a communications network

1997
- 1997-10-21 FI FI974020A patent/FI974020A0/en not_active Application Discontinuation
1998
- 1998-10-20 AU AU95439/98A patent/AU9543998A/en not_active Abandoned
- 1998-10-20 WO PCT/FI1998/000816 patent/WO1999021326A2/en active Application Filing

Also Published As

Publication number	Publication date
WO1999021326A3 (en)	1999-07-29
FI974020A0 (en)	1997-10-21
WO1999021326A2 (en)	1999-04-29

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Legal Events

Date	Code	Title	Description
2000-07-06	MK6	Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase