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ES8405177A1 - Sistema de control de traduccion de direcciones en un sistema de proceso de datos. - Google Patents

Sistema de control de traduccion de direcciones en un sistema de proceso de datos.

Info

Publication number
ES8405177A1
ES8405177A1 ES523748A ES523748A ES8405177A1 ES 8405177 A1 ES8405177 A1 ES 8405177A1 ES 523748 A ES523748 A ES 523748A ES 523748 A ES523748 A ES 523748A ES 8405177 A1 ES8405177 A1 ES 8405177A1
Authority
ES
Spain
Prior art keywords
address translation
control system
buffer control
translation buffer
verification
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES523748A
Other languages
English (en)
Other versions
ES523748A0 (es
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of ES523748A0 publication Critical patent/ES523748A0/es
Publication of ES8405177A1 publication Critical patent/ES8405177A1/es
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1458—Protection against unauthorised use of memory or access to memory by checking the subject access rights
    • G06F12/1466—Key-lock mechanism
    • G06F12/1475—Key-lock mechanism in a virtual system, e.g. with translation means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1036—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] for multiple virtual address spaces, e.g. segmentation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Security & Cryptography (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Storage Device Security (AREA)

Abstract

SISTEMA DE CONTROL DE TRADUCCION DE DIRECCIONES EN UN SISTEMA DE PROCESO DE DATOS.EL SISTEMA DE CONTROL OPERA SOBRE UN SISTEMA DE PROCESO DE DATOS EN EL CUAL SE HA PREVISTO UN SISTEMA DE TRADUCCION DE DIRECCIONES EFECTIVAS EN DIRECCIONES FISICAS, Y EN EL QUE UNA ETAPA INTERMEDIA ALMACENA PARES DE TRADUCCIONES DE LOS RESULTADOS TRADUCIDOS PERTINENTES, Y SE ALMACENA LA CLAVE DE PROCESO DE ALMACENAMIENTO EN DICHA ETAPA INTERMEDIA. SE HAN PREVISTO MODALIDADES DE VERIFICACION Y DE NO VERIFICACION DE PROTECCION DE ALMACENAMIENTO PARA REALIZAR EL CONTROL DE TRADUCCION DEDIRECCIONES.
ES523748A 1982-06-30 1983-06-30 Sistema de control de traduccion de direcciones en un sistema de proceso de datos. Expired ES8405177A1 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57113310A JPS6047624B2 (ja) 1982-06-30 1982-06-30 アドレス変換制御方式

Publications (2)

Publication Number Publication Date
ES523748A0 ES523748A0 (es) 1984-05-16
ES8405177A1 true ES8405177A1 (es) 1984-05-16

Family

ID=14608990

Family Applications (1)

Application Number Title Priority Date Filing Date
ES523748A Expired ES8405177A1 (es) 1982-06-30 1983-06-30 Sistema de control de traduccion de direcciones en un sistema de proceso de datos.

Country Status (9)

Country Link
US (1) US4604688A (es)
EP (1) EP0098168B1 (es)
JP (1) JPS6047624B2 (es)
KR (1) KR890000102B1 (es)
AU (1) AU543336B2 (es)
BR (1) BR8303526A (es)
CA (1) CA1195010A (es)
DE (1) DE3377948D1 (es)
ES (1) ES8405177A1 (es)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0658646B2 (ja) * 1982-12-30 1994-08-03 インタ−ナショナル・ビジネス・マシ−ンズ・コ−ポレ−ション デ−タ持続性が制御される仮想記憶アドレス変換機構
US4731740A (en) * 1984-06-30 1988-03-15 Kabushiki Kaisha Toshiba Translation lookaside buffer control system in computer or virtual memory control scheme
IN165278B (es) * 1984-09-21 1989-09-09 Digital Equipment Corp
JPS61166653A (ja) * 1985-01-19 1986-07-28 Panafacom Ltd アドレス変換エラー処理方法
US4860192A (en) * 1985-02-22 1989-08-22 Intergraph Corporation Quadword boundary cache system
US4933835A (en) * 1985-02-22 1990-06-12 Intergraph Corporation Apparatus for maintaining consistency of a cache memory with a primary memory
US4884197A (en) * 1985-02-22 1989-11-28 Intergraph Corporation Method and apparatus for addressing a cache memory
US5255384A (en) * 1985-02-22 1993-10-19 Intergraph Corporation Memory address translation system having modifiable and non-modifiable translation mechanisms
US4899275A (en) * 1985-02-22 1990-02-06 Intergraph Corporation Cache-MMU system
US5060137A (en) * 1985-06-28 1991-10-22 Hewlett-Packard Company Explicit instructions for control of translation lookaside buffers
US4777589A (en) * 1985-06-28 1988-10-11 Hewlett-Packard Company Direct input/output in a virtual memory system
JPS62117001A (ja) * 1985-11-16 1987-05-28 Hitachi Ltd プログラマブルシ−ケンスコントロ−ラの入出力処理方法
US5091846A (en) * 1986-10-03 1992-02-25 Intergraph Corporation Cache providing caching/non-caching write-through and copyback modes for virtual addresses and including bus snooping to maintain coherency
US5249276A (en) * 1987-06-22 1993-09-28 Hitachi, Ltd. Address translation apparatus having a memory access privilege check capability data which uses mask data to select bit positions of priviledge
US5226132A (en) * 1988-09-30 1993-07-06 Hitachi, Ltd. Multiple virtual addressing using/comparing translation pairs of addresses comprising a space address and an origin address (sto) while using space registers as storage devices for a data processing system
US4926481A (en) * 1988-12-05 1990-05-15 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Computer access security code system
US5237668A (en) * 1989-10-20 1993-08-17 International Business Machines Corporation Process using virtual addressing in a non-privileged instruction to control the copying of a page of data in or between multiple media
EP0690386A1 (en) * 1994-04-04 1996-01-03 International Business Machines Corporation Address translator and method of operation
US5787309A (en) * 1996-05-23 1998-07-28 International Business Machines Corporation Apparatus for protecting storage blocks from being accessed by unwanted I/O programs using I/O program keys and I/O storage keys having M number of bits
US5802397A (en) * 1996-05-23 1998-09-01 International Business Machines Corporation System for storage protection from unintended I/O access using I/O protection key by providing no control by I/O key entries over access by CP entity
US5900019A (en) * 1996-05-23 1999-05-04 International Business Machines Corporation Apparatus for protecting memory storage blocks from I/O accesses
US5809546A (en) * 1996-05-23 1998-09-15 International Business Machines Corporation Method for managing I/O buffers in shared storage by structuring buffer table having entries including storage keys for controlling accesses to the buffers
US5724551A (en) * 1996-05-23 1998-03-03 International Business Machines Corporation Method for managing I/O buffers in shared storage by structuring buffer table having entries include storage keys for controlling accesses to the buffers
US6442664B1 (en) * 1999-06-01 2002-08-27 International Business Machines Corporation Computer memory address translation system
US20030115476A1 (en) * 2001-10-31 2003-06-19 Mckee Bret Hardware-enforced control of access to memory within a computer using hardware-enforced semaphores and other similar, hardware-enforced serialization and sequencing mechanisms
US7155726B2 (en) * 2003-10-29 2006-12-26 Qualcomm Inc. System for dynamic registration of privileged mode hooks in a device
US9384144B1 (en) * 2014-03-25 2016-07-05 SK Hynix Inc. Error detection using a logical address key
US10255202B2 (en) * 2016-09-30 2019-04-09 Intel Corporation Multi-tenant encryption for storage class memory
US20220091764A1 (en) * 2021-12-02 2022-03-24 Intel Corporation Detection of data corruption in memory address decode circuitry

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4038645A (en) * 1976-04-30 1977-07-26 International Business Machines Corporation Non-translatable storage protection control system
US4096573A (en) * 1977-04-25 1978-06-20 International Business Machines Corporation DLAT Synonym control means for common portions of all address spaces
US4241401A (en) * 1977-12-19 1980-12-23 Sperry Corporation Virtual address translator utilizing interrupt level code
CA1123964A (en) * 1978-10-26 1982-05-18 Anthony J. Capozzi Integrated multilevel storage hierarchy for a data processing system
US4500952A (en) * 1980-05-23 1985-02-19 International Business Machines Corporation Mechanism for control of address translation by a program using a plurality of translation tables
US4430705A (en) * 1980-05-23 1984-02-07 International Business Machines Corp. Authorization mechanism for establishing addressability to information in another address space
US4481573A (en) * 1980-11-17 1984-11-06 Hitachi, Ltd. Shared virtual address translation unit for a multiprocessor system
US4410941A (en) * 1980-12-29 1983-10-18 Wang Laboratories, Inc. Computer having an indexed local ram to store previously translated virtual addresses
US4439830A (en) * 1981-11-09 1984-03-27 Control Data Corporation Computer system key and lock protection mechanism

Also Published As

Publication number Publication date
KR890000102B1 (ko) 1989-03-07
ES523748A0 (es) 1984-05-16
JPS6047624B2 (ja) 1985-10-22
KR840005234A (ko) 1984-11-05
JPS595479A (ja) 1984-01-12
EP0098168A3 (en) 1985-11-06
DE3377948D1 (en) 1988-10-13
CA1195010A (en) 1985-10-08
EP0098168B1 (en) 1988-09-07
US4604688A (en) 1986-08-05
BR8303526A (pt) 1984-02-07
EP0098168A2 (en) 1984-01-11
AU543336B2 (en) 1985-04-18
AU1641083A (en) 1984-01-05

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Legal Events

Date Code Title Description
FD1A Patent lapsed

Effective date: 20020401