ES337433A1 - Metodo de fabricacion de un dispositivo semiconductor. - Google Patents
Metodo de fabricacion de un dispositivo semiconductor.Info
- Publication number
- ES337433A1 ES337433A1 ES337433A ES337433A ES337433A1 ES 337433 A1 ES337433 A1 ES 337433A1 ES 337433 A ES337433 A ES 337433A ES 337433 A ES337433 A ES 337433A ES 337433 A1 ES337433 A1 ES 337433A1
- Authority
- ES
- Spain
- Prior art keywords
- oxide
- regions
- heating
- layer
- fet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/40—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
- H10D84/401—Combinations of FETs or IGBTs with BJTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D99/00—Subject matter not provided for in other groups of this subclass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/053—Field effect transistors fets
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/106—Masks, special
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/117—Oxidation, selective
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Formation Of Insulating Films (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
NL656507231A NL149640B (nl) | 1965-06-05 | 1965-06-05 | Halfgeleiderinrichting met meer dan een schakelelement in een halfgeleiderlichaam en werkwijze voor het vervaardigen daarvan. |
Publications (1)
Publication Number | Publication Date |
---|---|
ES337433A1 true ES337433A1 (es) | 1968-02-16 |
Family
ID=19793311
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ES0327508A Expired ES327508A1 (es) | 1965-06-05 | 1966-06-03 | Dispositivo semiconductor que tiene una pluralidad de elementos de circuito formados sobre el mismo cuerpo semiconductor. |
ES337433A Expired ES337433A1 (es) | 1965-06-05 | 1967-03-01 | Metodo de fabricacion de un dispositivo semiconductor. |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ES0327508A Expired ES327508A1 (es) | 1965-06-05 | 1966-06-03 | Dispositivo semiconductor que tiene una pluralidad de elementos de circuito formados sobre el mismo cuerpo semiconductor. |
Country Status (9)
Country | Link |
---|---|
US (1) | US3580745A (es) |
AT (1) | AT299309B (es) |
BE (1) | BE682092A (es) |
CH (1) | CH509669A (es) |
DE (1) | DE1564406C3 (es) |
ES (2) | ES327508A1 (es) |
GB (1) | GB1147205A (es) |
NL (1) | NL149640B (es) |
SE (1) | SE344657B (es) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4015281A (en) * | 1970-03-30 | 1977-03-29 | Hitachi, Ltd. | MIS-FETs isolated on common substrate |
US3861969A (en) * | 1970-03-31 | 1975-01-21 | Hitachi Ltd | Method for making III{14 V compound semiconductor devices |
US4003071A (en) * | 1971-09-18 | 1977-01-11 | Fujitsu Ltd. | Method of manufacturing an insulated gate field effect transistor |
US4116721A (en) * | 1977-11-25 | 1978-09-26 | International Business Machines Corporation | Gate charge neutralization for insulated gate field-effect transistors |
US4140548A (en) * | 1978-05-19 | 1979-02-20 | Maruman Integrated Circuits Inc. | MOS Semiconductor process utilizing a two-layer oxide forming technique |
IT1217323B (it) * | 1987-12-22 | 1990-03-22 | Sgs Microelettronica Spa | Struttura integrata di transistor bipolare di potenza di alta tensione e di transistor mos di potenza di bassa tensione nella configurazione"emitter switching"e relativo processo di fabbricazione |
-
1965
- 1965-06-05 NL NL656507231A patent/NL149640B/xx not_active IP Right Cessation
-
1966
- 1966-05-27 US US553409A patent/US3580745A/en not_active Expired - Lifetime
- 1966-06-02 GB GB24575/66A patent/GB1147205A/en not_active Expired
- 1966-06-02 SE SE7577/66A patent/SE344657B/xx unknown
- 1966-06-02 DE DE1564406A patent/DE1564406C3/de not_active Expired
- 1966-06-02 CH CH797766A patent/CH509669A/de not_active IP Right Cessation
- 1966-06-02 AT AT524666A patent/AT299309B/de not_active IP Right Cessation
- 1966-06-03 ES ES0327508A patent/ES327508A1/es not_active Expired
- 1966-06-03 BE BE682092D patent/BE682092A/xx unknown
-
1967
- 1967-03-01 ES ES337433A patent/ES337433A1/es not_active Expired
Also Published As
Publication number | Publication date |
---|---|
CH509669A (de) | 1971-06-30 |
AT299309B (de) | 1972-06-12 |
BE682092A (es) | 1966-12-05 |
NL6507231A (es) | 1966-12-06 |
NL149640B (nl) | 1976-05-17 |
GB1147205A (en) | 1969-04-02 |
SE344657B (es) | 1972-04-24 |
DE1564406A1 (de) | 1969-09-25 |
DE1564406C3 (de) | 1978-10-12 |
DE1564406B2 (de) | 1978-02-09 |
US3580745A (en) | 1971-05-25 |
ES327508A1 (es) | 1967-07-16 |
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