ES2577291T3 - Enlaces unidireccionales seguros desde y hacia un motor de seguridad - Google Patents
Enlaces unidireccionales seguros desde y hacia un motor de seguridad Download PDFInfo
- Publication number
- ES2577291T3 ES2577291T3 ES06832267.6T ES06832267T ES2577291T3 ES 2577291 T3 ES2577291 T3 ES 2577291T3 ES 06832267 T ES06832267 T ES 06832267T ES 2577291 T3 ES2577291 T3 ES 2577291T3
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L63/00—Network architectures or network communication protocols for network security
- H04L63/02—Network architectures or network communication protocols for network security for separating internal from external traffic, e.g. firewalls
- H04L63/0227—Filtering policies
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/30—Authentication, i.e. establishing the identity or authorisation of security principals
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
- G06F21/51—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems at application loading time, e.g. accepting, rejecting, starting or inhibiting executable software based on integrity or source reliability
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
- G06F21/55—Detecting local intrusion or implementing counter-measures
- G06F21/56—Computer malware detection or handling, e.g. anti-virus arrangements
- G06F21/567—Computer malware detection or handling, e.g. anti-virus arrangements using dedicated hardware
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L63/00—Network architectures or network communication protocols for network security
- H04L63/02—Network architectures or network communication protocols for network security for separating internal from external traffic, e.g. firewalls
- H04L63/0209—Architectural arrangements, e.g. perimeter networks or demilitarized zones
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L63/00—Network architectures or network communication protocols for network security
- H04L63/08—Network architectures or network communication protocols for network security for authentication of entities
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2221/00—Indexing scheme relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F2221/21—Indexing scheme relating to G06F21/00 and subgroups addressing additional information or applications relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F2221/2137—Time limited access, e.g. to a computer or data
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2221/00—Indexing scheme relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F2221/21—Indexing scheme relating to G06F21/00 and subgroups addressing additional information or applications relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F2221/2151—Time stamp
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- Engineering & Computer Science (AREA)
- Computer Security & Cryptography (AREA)
- Computer Hardware Design (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Computing Systems (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Virology (AREA)
- General Health & Medical Sciences (AREA)
- Health & Medical Sciences (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
- Computer And Data Communications (AREA)
- Communication Control (AREA)
Abstract
Un procedimiento para comunicaciones seguras entre un ordenador transmisor (24) y un ordenador receptor (22), comprendiendo el procedimiento: transmitir datos desde el ordenador transmisor (24) sobre un primer enlace (28) a un motor (26) de seguridad de los datos; recibir y validar los datos en el interior del motor (26) de seguridad de los datos; y después de validar los datos, transmitir los datos del motor (24) de seguridad de los datos al ordenador receptor (22) sobre un segundo enlace (30), estando el procedimiento caracterizado por que tanto la transmisión desde el ordenador transmisor (24) al motor de seguridad (26) por medio del primer enlace (28) como desde el motor de seguridad (26) al ordenador receptor (22) por medio del segundo enlace (30) se llevan a cabo sobre enlaces unidireccionales de un medio de transmisión unidireccional, que no tienen ningún camino inverso.
Description
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La figura 5 es un diagrama de flujo de un proceso 100 para transmitir datos en el sistema 80 al ordenador receptor 22, de acuerdo con una realización de la presente invención. Cuando el controlador 82 de conmutadores funciona en modo temporizado, se inicia entonces una etapa 104 cuando se alcanza un tiempo designado inicial, que provoca que el controlador 82 de conmutadores cierre el conmutador 90, abriendo al mismo tiempo el conmutador 92. Alternativamente, cuando el controlador de conmutadores funciona en modo de control externo, la etapa 104 se inicia cuando se recibe una señal de control mediante el controlador 82 de conmutadores desde el ordenador intermedio 26. El cierre del conmutador 90 conecta el enlace unidireccional del lado anterior entre el ordenador transmisor 24 y el ordenador intermedio 26.
El ordenador transmisor 24 está configurado habitualmente para comenzar la transmisión en un tiempo que está sincronizado con el cierre del conmutador 90. Esta transmisión se produce tal como se indica en la etapa 106. Durante la transmisión, el ordenador transmisor 24 puede enviar asimismo un mensaje de modo de conmutación al ordenador intermedio 26, que establece la duración temporal de la transmisión.
En paralelo o con posterioridad a la transmisión de la etapa 106, el ordenador intermedio 26 lleva a cabo, en la etapa 108, operaciones para validar el contenido de los datos transferidos. Estas operaciones, descritas anteriormente haciendo referencia a la figura 1, se pueden llevar a cabo mediante un procesador 50 o mediante un procesador auxiliar, interno o externo al ordenador intermedio. Si se determina que el contenido no es válido, al comprender, por ejemplo, software malicioso, entonces el ordenador intermedio no lleva a cabo operaciones subsiguientes asociadas con la transmisión de los datos al ordenador receptor 22 y, en lugar de esto, puede rechazar los datos no válidos o eliminar la parte no válida de los datos en la etapa 110. Alternativamente, el ordenador intermedio 26 puede archivar los datos no válidos para un análisis posterior. El ordenador intermedio 26 puede asimismo grabar en un registro la ocurrencia de datos no válidos y puede emitir una alarma.
Si el contenido de los datos es validado, entonces, en la etapa 114, el controlador 82 de conmutadores conecta el enlace unidireccional del lado posterior cerrando el conmutador 92, en la etapa 114. Para asegurar que la transmisión no se produce simultáneamente en ambos enlaces unidireccionales, el controlador de conmutadores abre asimismo el conmutador 90.
Si el controlador 82 de conmutadores funciona en modo temporizado, entonces la etapa 114 se inicia cuando se alcanza el tiempo designado. Alternativamente, cuando el controlador de conmutadores funciona en modo de control externo, la etapa 114 se inicia cuando se recibe una señal de control mediante el controlador 82 de conmutadores desde el ordenador intermedio 26.
A continuación, en la etapa 116, el ordenador intermedio 26 transmite los datos validados al ordenador receptor 22. Cuando ha transcurrido el periodo de tiempo designado para la transmisión (ya sea según un modo temporizado o un modo de control externo), el controlador de conmutadores abre el conmutador 92 en la etapa 118. En modo de control externo, la señal de control para abrir el conmutador 90 y el conmutador 92 se envía en la etapa 118. Alternativamente, se puede omitir la etapa 118, y el proceso 100 puede continuar en la etapa 104, con el cierre del conmutador 90 y la apertura simultánea del conmutador 92.
Aunque las realizaciones descritas anteriormente utilizan dos enlaces unidireccionales con un único ordenador intermedio, en realizaciones alternativas (no mostradas en las figuras), se pueden conectar en serie tres o más enlaces unidireccionales con múltiples ordenadores intermedios.
Además, aunque las realizaciones descritas anteriormente se refieren específicamente a ciertos tipos de funciones de seguridad que se aplican a contenido transmitido sobre un enlace unidireccional, se pueden llevar a cabo otros tipos de procesamiento de datos en un punto intermedio sobre un enlace unidireccional, de acuerdo con los principios de la presente invención. Los principios de la presente invención pueden ser aplicados análogamente en el contexto de otros entornos y otras tecnologías de comunicaciones.
Por lo tanto, se apreciará que las realizaciones descritas anteriormente se indican a modo de ejemplo, y que la presente invención no se limita a lo que se ha mostrado y descrito particularmente en lo anterior.
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Claims (1)
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imagen1 imagen2
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US81692406P | 2006-06-27 | 2006-06-27 | |
US816924P | 2006-06-27 | ||
PCT/IL2006/001499 WO2008001344A2 (en) | 2006-06-27 | 2006-12-28 | One way secure link |
Publications (1)
Publication Number | Publication Date |
---|---|
ES2577291T3 true ES2577291T3 (es) | 2016-07-14 |
Family
ID=38846081
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ES06832267.6T Active ES2577291T3 (es) | 2006-06-27 | 2006-12-28 | Enlaces unidireccionales seguros desde y hacia un motor de seguridad |
Country Status (6)
Country | Link |
---|---|
US (3) | US9762536B2 (es) |
EP (1) | EP2035948B1 (es) |
ES (1) | ES2577291T3 (es) |
HU (1) | HUE030535T2 (es) |
IL (1) | IL196088A (es) |
WO (1) | WO2008001344A2 (es) |
Families Citing this family (37)
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ES2577291T3 (es) | 2006-06-27 | 2016-07-14 | Waterfall Security Solutions Ltd. | Enlaces unidireccionales seguros desde y hacia un motor de seguridad |
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US9847972B2 (en) | 2017-12-19 |
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