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ES2103671B1 - MANUFACTURE METHOD OF VDMOS TRANSISTORS. - Google Patents

MANUFACTURE METHOD OF VDMOS TRANSISTORS.

Info

Publication number
ES2103671B1
ES2103671B1 ES9402670A ES9402670A ES2103671B1 ES 2103671 B1 ES2103671 B1 ES 2103671B1 ES 9402670 A ES9402670 A ES 9402670A ES 9402670 A ES9402670 A ES 9402670A ES 2103671 B1 ES2103671 B1 ES 2103671B1
Authority
ES
Spain
Prior art keywords
vdmos
diffusion
well
manufacture method
followed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES9402670A
Other languages
Spanish (es)
Other versions
ES2103671A1 (en
Inventor
Garcia Juan Fernandez
Marti Josep Montserrat
Hernandez Miquel Vellvehi
Casas Enric Cabruja
Berenguer Esteve Farres
Palacios Jose Andres Rebollo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nokia Spain SA
Original Assignee
Alcatel Standard Electrics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel Standard Electrics SA filed Critical Alcatel Standard Electrics SA
Priority to ES9402670A priority Critical patent/ES2103671B1/en
Publication of ES2103671A1 publication Critical patent/ES2103671A1/en
Application granted granted Critical
Publication of ES2103671B1 publication Critical patent/ES2103671B1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)

Abstract

METODO DE FABRICACION DE TRANSISTORES VDMOS. SE PRESENTAN LAS ETAPAS BASICAS DEL PROCESO DE FABRICACION DE UN DISPOSITIVO VDMOS DE POTENCIA DE BAJA TENSION Y BAJA RESISTENCIA EN CONDUCCION. ESTE COMPORTAMIENTO ELECTRICO SE CON SIGUE MEDIANTE UNA TRIPLE IMPLANTACION JONICA PARA LA FORMACION DE LAS REGIONES DE FUENTE (108), POZO (106) Y DIFUSION P+ (107) DE CORTOCIRCUITO ENTRE AMBOS, SEGUIDAS DE LOS CORRESPONDIENTES TRATAMIENTOS TERMICOS POSTERIORES. LA DIFUSION DE BORO EN LA REGLON DE POZO (106) SE REALIZA CON UN NIVEL TAL QUE, MANTENIENDO LA MAYOR RESISTIVIDAD POSIBLE DE LA MISMA, LA TENSION DE RUPTURA DEL DISPOSITIVO NO DECREZCA SUBSTANCIALMENTE. ADEMAS, CON OBJETO DE EVITAR LA ACTIVACION DEL TRANSISTOR BIPOLAR PARASITO INHERENTE A LA ESTRUCTURA DEL TRANSISTOR VDMOS, LA DIFUSION P+ (107) ENTRE FUENTE (108) Y POZO (106) ES TIPO SUPERFICIAL, LO CUAL NO DEGRADA LA TENSION DE RUPTURA DEL DISPOSITIVO PARA UN MISMO ESPESOR DE LA CAPA EPITAXIAL (102), POR LO QUE LA RESISTENCIA DEL DISPOSITIVO NOSE MODIFICA.MANUFACTURE METHOD OF VDMOS TRANSISTORS. THE BASIC STAGES OF THE MANUFACTURING PROCESS OF A VDMOS DEVICE WITH LOW VOLTAGE POWER AND LOW CONDUCTION RESISTANCE ARE PRESENTED. THIS ELECTRICAL BEHAVIOR IS FOLLOWED THROUGH A TRIPLE ION IMPLEMENTATION FOR THE FORMATION OF THE SOURCE (108), WELL (106) AND DIFFUSION P + (107) OF SHORT CIRCUIT BETWEEN, FOLLOWED BY THE CORRESPONDING SUBSEQUENT THERMAL TREATMENTS. THE DIFFUSION OF BORUS IN THE WELL REGULATION (106) IS CARRIED OUT AT A LEVEL SUCH THAT, MAINTAINING THE GREATEST POSSIBLE RESISTIVITY, THE BREAKDOWN VOLTAGE OF THE DEVICE DOES NOT DECREASE SUBSTANTIALLY. IN ADDITION, IN ORDER TO AVOID THE ACTIVATION OF THE PARASITE BIPOLAR TRANSISTOR INHERENT TO THE STRUCTURE OF THE VDMOS TRANSISTOR, THE DIFFUSION P + (107) BETWEEN SOURCE (108) AND WELL (106) IS A SURFACE TYPE, WHICH DOES NOT DEGRADE THE RUPTURE TENSION OF THE DISPOSAL FOR THE SAME THICKNESS OF THE EPITAXIAL LAYER (102), THEREFORE THE RESISTANCE OF THE DEVICE DOES NOT MODIFY.

ES9402670A 1994-12-29 1994-12-29 MANUFACTURE METHOD OF VDMOS TRANSISTORS. Expired - Lifetime ES2103671B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
ES9402670A ES2103671B1 (en) 1994-12-29 1994-12-29 MANUFACTURE METHOD OF VDMOS TRANSISTORS.

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
ES9402670A ES2103671B1 (en) 1994-12-29 1994-12-29 MANUFACTURE METHOD OF VDMOS TRANSISTORS.

Publications (2)

Publication Number Publication Date
ES2103671A1 ES2103671A1 (en) 1997-09-16
ES2103671B1 true ES2103671B1 (en) 1998-05-01

Family

ID=8288420

Family Applications (1)

Application Number Title Priority Date Filing Date
ES9402670A Expired - Lifetime ES2103671B1 (en) 1994-12-29 1994-12-29 MANUFACTURE METHOD OF VDMOS TRANSISTORS.

Country Status (1)

Country Link
ES (1) ES2103671B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102709191A (en) * 2012-06-07 2012-10-03 无锡市晶源微电子有限公司 Process for manufacturing series of intermediate-voltage N-type vertical conduction double-diffused metal oxide semiconductor transistors by using composite epitaxy

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4055444A (en) * 1976-01-12 1977-10-25 Texas Instruments Incorporated Method of making N-channel MOS integrated circuits
US4417385A (en) * 1982-08-09 1983-11-29 General Electric Company Processes for manufacturing insulated-gate semiconductor devices with integral shorts
US4716126A (en) * 1986-06-05 1987-12-29 Siliconix Incorporated Fabrication of double diffused metal oxide semiconductor transistor
JPH077750B2 (en) * 1989-05-15 1995-01-30 株式会社東芝 Method for manufacturing semiconductor device

Also Published As

Publication number Publication date
ES2103671A1 (en) 1997-09-16

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