EP2973657B1 - Surface roughening to reduce adhesion in an integrated mems device - Google Patents
Surface roughening to reduce adhesion in an integrated mems device Download PDFInfo
- Publication number
- EP2973657B1 EP2973657B1 EP14779860.7A EP14779860A EP2973657B1 EP 2973657 B1 EP2973657 B1 EP 2973657B1 EP 14779860 A EP14779860 A EP 14779860A EP 2973657 B1 EP2973657 B1 EP 2973657B1
- Authority
- EP
- European Patent Office
- Prior art keywords
- mems
- contacting surface
- substrate
- base substrate
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000007788 roughening Methods 0.000 title description 4
- 239000000758 substrate Substances 0.000 claims description 72
- 238000000034 method Methods 0.000 claims description 28
- 238000005530 etching Methods 0.000 claims description 18
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 claims description 9
- WMFOQBRAJBCJND-UHFFFAOYSA-M Lithium hydroxide Chemical compound [Li+].[OH-] WMFOQBRAJBCJND-UHFFFAOYSA-M 0.000 claims description 7
- 238000001020 plasma etching Methods 0.000 claims description 6
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 claims description 6
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims description 4
- 229910052724 xenon Inorganic materials 0.000 claims description 3
- FHNFHKCVQCLJFQ-UHFFFAOYSA-N xenon atom Chemical compound [Xe] FHNFHKCVQCLJFQ-UHFFFAOYSA-N 0.000 claims description 3
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 claims description 2
- OEYIOHPDSNJKLS-UHFFFAOYSA-N choline Chemical compound C[N+](C)(C)CCO OEYIOHPDSNJKLS-UHFFFAOYSA-N 0.000 claims description 2
- 229960001231 choline Drugs 0.000 claims description 2
- 239000004020 conductor Substances 0.000 claims description 2
- 229910052731 fluorine Inorganic materials 0.000 claims description 2
- 239000011737 fluorine Substances 0.000 claims description 2
- 239000003989 dielectric material Substances 0.000 claims 1
- 239000010408 film Substances 0.000 description 24
- 229910052581 Si3N4 Inorganic materials 0.000 description 14
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 12
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 229910052814 silicon oxide Inorganic materials 0.000 description 7
- 239000007789 gas Substances 0.000 description 5
- 238000000059 patterning Methods 0.000 description 5
- 229910018503 SF6 Inorganic materials 0.000 description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 3
- 239000002131 composite material Substances 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- WRQGPGZATPOHHX-UHFFFAOYSA-N ethyl 2-oxohexanoate Chemical compound CCCCC(=O)C(=O)OCC WRQGPGZATPOHHX-UHFFFAOYSA-N 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 229910010271 silicon carbide Inorganic materials 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- TVVNZBSLUREFJN-UHFFFAOYSA-N 2-(4-chlorophenyl)sulfanyl-5-nitrobenzaldehyde Chemical compound O=CC1=CC([N+](=O)[O-])=CC=C1SC1=CC=C(Cl)C=C1 TVVNZBSLUREFJN-UHFFFAOYSA-N 0.000 description 2
- CEBDXRXVGUQZJK-UHFFFAOYSA-N 2-methyl-1-benzofuran-7-carboxylic acid Chemical compound C1=CC(C(O)=O)=C2OC(C)=CC2=C1 CEBDXRXVGUQZJK-UHFFFAOYSA-N 0.000 description 2
- YCIMNLLNPGFGHC-UHFFFAOYSA-N catechol Chemical compound OC1=CC=CC=C1O YCIMNLLNPGFGHC-UHFFFAOYSA-N 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- PIICEJLVQHRZGT-UHFFFAOYSA-N Ethylenediamine Chemical compound NCCN PIICEJLVQHRZGT-UHFFFAOYSA-N 0.000 description 1
- LHNWMULAKLZVHJ-UHFFFAOYSA-N FBrF Chemical compound FBrF LHNWMULAKLZVHJ-UHFFFAOYSA-N 0.000 description 1
- CPELXLSAUQHCOX-UHFFFAOYSA-N Hydrogen bromide Chemical compound Br CPELXLSAUQHCOX-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- 229910000042 hydrogen bromide Inorganic materials 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052743 krypton Inorganic materials 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910052754 neon Inorganic materials 0.000 description 1
- -1 plasma Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 description 1
- 229960000909 sulfur hexafluoride Drugs 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Images
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B3/00—Devices comprising flexible or deformable elements, e.g. comprising elastic tongues or membranes
- B81B3/0002—Arrangements for avoiding sticking of the flexible or moving parts
- B81B3/001—Structures having a reduced contact area, e.g. with bumps or with a textured surface
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C2201/00—Manufacture or treatment of microstructural devices or systems
- B81C2201/11—Treatments for avoiding stiction of elastic or moving parts of MEMS
- B81C2201/115—Roughening a surface
Definitions
- the present invention relates generally to integrated MEMS devices and more particularly to a system and method for reducing adhesion in such devices.
- Integrated MEMS devices (with dimensions from 0.01 to 1000 um) have moving MEMS parts with smooth surfaces. When the surfaces come into contact, they can adhere or stick together (often referred to as "stiction").
- the adhesion force which must be overcome in order to separate the parts from each other, originates from the surface adhesion energy that is proportional to the area of atomic contact. Accordingly what is needed is a system and method to reduce the adhesion force in such devices. The present invention addresses such a need.
- US 2008/0081391 discloses a MEMS device with roughened surface and method of producing the same.
- a method of producing a MEMS device provides a MEMS apparatus having released structure.
- the MEMS apparatus is formed at least in part from an SOI wafer having a first layer, a second layer spaced from the first layer, and an insulator layer between the first layer and second layer.
- US 2006/0278942 discloses an antistiction MEMS substrate and method of manufacture.
- a composite wafer for fabricating MEMS devices is provided with a plurality of antistiction bumps, buried under a device layer of the composite wafer.
- the antistiction bumps are prepared lithographically, by patterning an antistiction material prior to the assembly of the composite wafer.
- an integrated MEMS device comprises a MEMS substrate having a first contacting surface; a base substrate coupled to the MEMS substrate having a second contacting surface of the MEMS device. At least one of the first contacting surface and the second contacting surface is roughened in a predetermined manner.
- the MEMS substrate faces one or more fixed bump stops on the base substrate and the surface of the one or more fixed bump stops is roughened.
- a method to reduce surface adhesion forces in an integrated MEMS device including a MEMS substrate having a first contacting surface and a base substrate coupled to the MEMS substrate having a second contacting surface and one or more fixed bump stops on the base substrate, the method comprises etching at least one of the first contacting surface and the second contacting surface to roughen at least one of the first contacting surface and the second contacting surface and etching the surface of the one or more fixed bump stops to roughen the surface of the one or more fixed bump stops.
- a method to reduce surface adhesion forces in an integrated MEMS device including a MEMS substrate having a first contacting surface and a base substrate coupled to the MEMS substrate having a second contacting surface.
- the method comprises depositing a rough film onto one of the first contacting surface and the second contacting surface; and plasma etching the rough film through and into the one of the first contacting surface and the second contacting surface. The roughness on the rough film will be transferred into the one of the first contacting surface and the second contacting surface.
- the present invention relates generally to integrated MEMS devices and more particularly to a system and method for reducing adhesion in such devices.
- Micro-Electro-Mechanical Systems refers to a class of structures or devices fabricated using semiconductor-like processes and exhibiting mechanical characteristics such as the ability to move or deform. MEMS often, but not always, interact with electrical signals. MEMS devices include but not limited to gyroscopes, accelerometers, magnetometers, microphones, and pressure sensors.
- MEMS device may refer to a semiconductor device implemented as a micro-electro-mechanical system.
- MEMS structure may refer to any feature that may be part of a larger MEMS device.
- device layer may refer to the silicon substrate in which the MEMS structure is formed.
- An Engineered silicon-on-insulator (ESOI) wafer may refer to a SOI wafer with cavities underneath the device wafer.
- Base substrate may include CMOS substrate or any other semiconductor substrate.
- base substrate may include electrical circuits.
- Handle wafer typically refers to a thicker semiconductor substrate used as a carrier for the MEMS substrate.
- the handle wafer is the base of a silicon-on-insulator wafer. Handle substrate, handle layer, and handle wafer can be interchanged.
- the MEMS substrate includes the device layer and the handle layer.
- a cavity may refer to an opening in a substrate wafer and enclosure may refer to a fully enclosed space.
- Standoff may be a vertical structure providing electrical contact.
- a MEMS device with one or both contacting surfaces being roughened, and fabrication methods to achieve rough surfaces for one or both surfaces of the two contacting parts are disclosed.
- the roughness of the contacting surfaces reduces the surface adhesion energy, therefore the sticking force, preventing the contacting surfaces stick to each other.
- FIG. 1A shows a cross section drawing of a bonded base substrate-MEMS device 100 with movable structure 106a which can come in contact with the bump stop 110a on base substrate 107.
- the MEMS substrate 111 includes a handle substrate 101 with cavities etched into it and a device layer 103, bonded together with a thin dielectric film 102 (such as silicon oxide) in between.
- the device layer 103 is made of single crystal silicon.
- Standoff 104 is formed with a germanium (Ge) film 105 on top of the standoff 104.
- the MEMS substrate 111 is completed after the device layer 103 is patterned and etched to form movable structure 106a.
- the MEMS device 100 includes a base substrate 107.
- a layer of conductive material 108 is deposited on the base substrate to provide electrical connection from the device layer 103 to the base substrate 107.
- the base substrate-MEMS integration is achieved by eutectic bonding of Ge 105 on the MEMS substrate 111 with the aluminum 108 of the base substrate 107.
- the bump stop 110a on base substrate 107 is a stationary structure that limits the motion of the moveable structure 106a.
- the MEMS substrate 111 and the base substrate 107 are bonded to form the base substrate-MEMS device 100.
- bump stop 110a has a layer of silicon nitride (SiN) 112 over a layer of silicon oxide 109. Both Si and SiN surfaces are smooth with a roughness of about 0.5 to 2.5 nm (rms) without a surface treatment or etch.
- Figure 1B shows a cross section drawing of the bonded base-substrate MEMS device 100 with movable structure 106b which can move and touch the bump stops 110b on the base substrate.
- movable structure 106b surface and bump stop 110b surfaces can be roughened.
- the area of atomic contact is reduced and hence the adhesion energy or stiction force is reduced.
- Surface roughening can be done by etching the surfaces of the movable structure 106b or the surfaces of stationary bump stops 110b in a gas, plasma, or liquid with locally non-uniform etch rate.
- the surface of the movable structure 106b or the surface of the bump stop 110b, or both surfaces can be roughened by various processing techniques to reduce the area of atomic surface contact, and thus the adhesion force when the movable structure 106b comes in contact with bump stop 110b.
- the movable structure 106b can be made of silicon and the bump stop 110b can be made of SiN.
- Other embodiments can have bump stop 110bsurfaces made of any other material such as silicon oxide, aluminum or, titanium nitride (TiN).
- Figures 2A - 2E show a series of cross section drawings of base substrate processing steps to complete a base substrate with bump stops having a rough surface.
- Figure 2A shows the cross-section of a base substrate 107 with a conductive layer 108 such as aluminum (Al) deposited, patterned and etched.
- a conductive layer 108 such as aluminum (Al) deposited, patterned and etched.
- an Inter-Metal Dielectric (IMD) silicon oxide layer 109 is deposited on patterned conductive layer 108 and chemical mechanical polished (CMPed) to planarize the IMD silicon oxide layer 109.
- Figure 2C shows a blanket passivation SiN film 112 deposited on the planarized IMD silicon oxide layer 109.
- IMD Inter-Metal Dielectric
- the SiN film 112 has a smooth surface with a root-mean-square (RMS) roughness in the order of 1 - 3 nm (nanometers).
- RMS root-mean-square
- SiC silicon carbide
- amorphous Si not shown
- Figure 2D shows the cross section of a base substrate 107 with a roughened SiN surface 112a achieved by local non-uniform etching with wet chemical, gas, or plasma processing.
- roughness can be obtained from oxygen-free plasma etching of SiN film 112 using a mixture of CF 4 /H 2 or SF 6 /CH 4 /N 2 gas combinations.
- the SiC or amorphous Si film can be etched with a plasma etch followed by further SiN etch for rougher surface.
- Figure 2E shows the cross section of the completed base substrate 107 after passivation SiN, and patterning and etching IMD silicon oxide layer 109a to form bump stop 110b, with a top layer of SiN 112a with a rough surface on bump stop 110b.
- Figures 3A - 3D show a series of cross section drawings of MEMS substrate 300 processing steps to complete the MEMS device with moveable structures having a rough surface in an embodiment.
- Figure 3A shows a cross-section of an engineered SOI (ESOI)) wafer 310 comprised of a device layer 307 and a handle substrate 301 with cavities. The device layer 307 and a handle substrate 301 are bonded with a thin dielectric film 102 in between. In an embodiment, the device layer 307 can be thinned before subsequent bonding to a base substrate.
- a Ge film 305 is deposited onto the device layer 307 followed by coating and patterning photoresist 302 to define a standoff.
- a wet etching step can be performed on the Ge film 305 and a dry etching can be performed on a portion of the device layer 307 to expose a surface 303a of the device layer 307 to form standoff 304 with a Ge film 305 on top.
- the standoff 304 is etched after depositing and patterning the Ge film 305. As shown in Figure 3C exposed surface 303a is etched to form a rough surface 303b, followed by the removal of the patterned photoresist 302 and cleaning of the wafer. In different embodiment, the standoff 304 is patterned and etched before depositing and patterning Ge film 305.
- the surface 303a of the device layer 307 can be roughened by a plasma-less process such as isotropic silicon wet etch or isotropic silicon dry etch processes.
- a plasma-less process such as isotropic silicon wet etch or isotropic silicon dry etch processes.
- Xenon diflouride (XeF2) dry chemical etch is an example of isotropic etch processes.
- the wet etchant contains choline (C 5 H 14 NO), potassium hydroxide (KOH), sodium hydroxide (NaOH), lithium hydroxide (LiOH), ethylene diamine pyrocatechol (EDP), tetramethylammonium hydroxide (TMAH), or TMEH.
- plasma-less etching gases examples include xenon diflouride (XeF 2 ), bromine difluoride (BrF 2 ), iodine pentafluoride (IF 5 ), bromine pentafluoride (BrF 5 ), chlorine triflouride (ClF 3 ), or fluorine (F 2 ).
- the surface 303a of the device layer 307 can be roughened by a plasma etch.
- Sulfur hexafluoride (SF 6 ) plasma dry etch processes is an example of plasma etching process.
- the plasma etching gas contains at least one of SF 6 , CF 4 , Cl 2 , HBr, He, Ne, Ar, Kr, or Xe.
- the roughness of the etched surface 303a could be in the order of 5 - 20 nm.
- Figure 3D shows a completed MEMS substrate 300.
- the rough device layer 307 is patterned, and etched to release the MEMS structure 306, Later, MEMS structure 306 is cleaned.
- Figures 4A-4D show a series of cross-section drawings of a second embodiment of the processing steps of providing a rough surface on a silicon substrate.
- Fig 4A shows a silicon substrate 402 with a smooth surface.
- Figure 4B shows a thin layer of a film 404 with a rough surface deposited onto the smooth surface of the silicon substrate 402 to initiate the roughness.
- the rough film 404 can be made of poly silicon or silicon carbide.
- the rough film 404 provides a rough surface on the silicon substrate 402 and no further etching is required, steps shown in Fig 4C and Fig 4D are optional. Other embodiments include further etching of the rough surface.
- Figure 4C shows an intermediate step of etching the rough film 404, resulting in a thinner film 404a.
- the etching step can be performed by wet etching or dry etching.
- Figure 4D shows the final step, where further etching transfers the roughness of the rough film 404a to the silicon substrate 402a.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Micromachines (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Analytical Chemistry (AREA)
Description
- The present invention relates generally to integrated MEMS devices and more particularly to a system and method for reducing adhesion in such devices.
- Integrated MEMS devices (with dimensions from 0.01 to 1000 um) have moving MEMS parts with smooth surfaces. When the surfaces come into contact, they can adhere or stick together (often referred to as "stiction"). The adhesion force, which must be overcome in order to separate the parts from each other, originates from the surface adhesion energy that is proportional to the area of atomic contact. Accordingly what is needed is a system and method to reduce the adhesion force in such devices. The present invention addresses such a need.
-
US 2008/0081391 discloses a MEMS device with roughened surface and method of producing the same. A method of producing a MEMS device provides a MEMS apparatus having released structure. The MEMS apparatus is formed at least in part from an SOI wafer having a first layer, a second layer spaced from the first layer, and an insulator layer between the first layer and second layer. -
US 2006/0278942 discloses an antistiction MEMS substrate and method of manufacture. A composite wafer for fabricating MEMS devices is provided with a plurality of antistiction bumps, buried under a device layer of the composite wafer. The antistiction bumps are prepared lithographically, by patterning an antistiction material prior to the assembly of the composite wafer. - Methods and systems for reducing adhesion in an integrated MEMS device are disclosed. In a first aspect, an integrated MEMS device comprises a MEMS substrate having a first contacting surface; a base substrate coupled to the MEMS substrate having a second contacting surface of the MEMS device. At least one of the first contacting surface and the second contacting surface is roughened in a predetermined manner. The MEMS substrate faces one or more fixed bump stops on the base substrate and the surface of the one or more fixed bump stops is roughened.
- In a second aspect, a method to reduce surface adhesion forces in an integrated MEMS device is disclosed. The integrated MEMS device including a MEMS substrate having a first contacting surface and a base substrate coupled to the MEMS substrate having a second contacting surface and one or more fixed bump stops on the base substrate, the method comprises etching at least one of the first contacting surface and the second contacting surface to roughen at least one of the first contacting surface and the second contacting surface and etching the surface of the one or more fixed bump stops to roughen the surface of the one or more fixed bump stops.
- In an example, a method to reduce surface adhesion forces in an integrated MEMS device is disclosed. The integrated MEMS device including a MEMS substrate having a first contacting surface and a base substrate coupled to the MEMS substrate having a second contacting surface. The method comprises depositing a rough film onto one of the first contacting surface and the second contacting surface; and plasma etching the rough film through and into the one of the first contacting surface and the second contacting surface. The roughness on the rough film will be transferred into the one of the first contacting surface and the second contacting surface.
-
-
Figure 1A shows a cross section drawing of a bonded base substrate-MEMS device with moving MEMS silicon parts which can move and touch the bump stops on base substrate. -
Figure 1B shows a cross section drawing of a bonded base substrate-MEMS device with moving MEMS silicon parts which can move and touch the bump stops on the base substrate and at least one of the contacting surfaces are roughened. -
Figures 2A - 2E show a series of cross section drawings of base substrate processing steps to complete the base substrate with bump stops having a rough surface. -
Figures 3A - 3D show a series of cross section drawings of a first embodiment of MEMS substrate processing steps to complete a MEMS wafer with silicon structures having a rough surface. -
Figures 4A-4D show a series of cross-section drawings of a second embodiment of a MEMS substrate processing steps to provide a rough surface on the MEMS substrate. - The present invention relates generally to integrated MEMS devices and more particularly to a system and method for reducing adhesion in such devices.
- In the described embodiments Micro-Electro-Mechanical Systems (MEMS) refers to a class of structures or devices fabricated using semiconductor-like processes and exhibiting mechanical characteristics such as the ability to move or deform. MEMS often, but not always, interact with electrical signals. MEMS devices include but not limited to gyroscopes, accelerometers, magnetometers, microphones, and pressure sensors.
- In the described embodiments, MEMS device may refer to a semiconductor device implemented as a micro-electro-mechanical system. MEMS structure may refer to any feature that may be part of a larger MEMS device. In the described embodiments, device layer may refer to the silicon substrate in which the MEMS structure is formed. An Engineered silicon-on-insulator (ESOI) wafer may refer to a SOI wafer with cavities underneath the device wafer. Base substrate may include CMOS substrate or any other semiconductor substrate. In certain embodiments, base substrate may include electrical circuits. Handle wafer typically refers to a thicker semiconductor substrate used as a carrier for the MEMS substrate. In certain embodiments, the handle wafer is the base of a silicon-on-insulator wafer. Handle substrate, handle layer, and handle wafer can be interchanged. The MEMS substrate includes the device layer and the handle layer.
- In the described embodiments, a cavity may refer to an opening in a substrate wafer and enclosure may refer to a fully enclosed space. Standoff may be a vertical structure providing electrical contact.
- A MEMS device with one or both contacting surfaces being roughened, and fabrication methods to achieve rough surfaces for one or both surfaces of the two contacting parts are disclosed. The roughness of the contacting surfaces reduces the surface adhesion energy, therefore the sticking force, preventing the contacting surfaces stick to each other.
-
Figure 1A shows a cross section drawing of a bonded base substrate-MEMS device 100 withmovable structure 106a which can come in contact with thebump stop 110a onbase substrate 107. TheMEMS substrate 111 includes ahandle substrate 101 with cavities etched into it and adevice layer 103, bonded together with a thin dielectric film 102 (such as silicon oxide) in between. In some embodiments, thedevice layer 103 is made of single crystal silicon.Standoff 104 is formed with a germanium (Ge)film 105 on top of thestandoff 104. TheMEMS substrate 111 is completed after thedevice layer 103 is patterned and etched to formmovable structure 106a. - The
MEMS device 100 includes abase substrate 107. A layer ofconductive material 108 is deposited on the base substrate to provide electrical connection from thedevice layer 103 to thebase substrate 107. In an embodiment, the base substrate-MEMS integration is achieved by eutectic bonding ofGe 105 on theMEMS substrate 111 with thealuminum 108 of thebase substrate 107. Thebump stop 110a onbase substrate 107 is a stationary structure that limits the motion of themoveable structure 106a. In an embodiment, theMEMS substrate 111 and thebase substrate 107 are bonded to form the base substrate-MEMS device 100. In an embodiment,bump stop 110a has a layer of silicon nitride (SiN) 112 over a layer ofsilicon oxide 109. Both Si and SiN surfaces are smooth with a roughness of about 0.5 to 2.5 nm (rms) without a surface treatment or etch. -
Figure 1B shows a cross section drawing of the bonded base-substrate MEMS device 100 withmovable structure 106b which can move and touch the bump stops 110b on the base substrate. In this embodiment, one of or bothmovable structure 106b surface andbump stop 110b surfaces can be roughened. - By roughening one or both of the surfaces, the area of atomic contact is reduced and hence the adhesion energy or stiction force is reduced. Surface roughening can be done by etching the surfaces of the
movable structure 106b or the surfaces of stationary bump stops 110b in a gas, plasma, or liquid with locally non-uniform etch rate. In this embodiment, the surface of themovable structure 106b or the surface of thebump stop 110b, or both surfaces can be roughened by various processing techniques to reduce the area of atomic surface contact, and thus the adhesion force when themovable structure 106b comes in contact withbump stop 110b. In an embodiment, themovable structure 106b can be made of silicon and thebump stop 110b can be made of SiN. Other embodiments can have bump stop 110bsurfaces made of any other material such as silicon oxide, aluminum or, titanium nitride (TiN). - In an embodiment,
Figures 2A - 2E show a series of cross section drawings of base substrate processing steps to complete a base substrate with bump stops having a rough surface.Figure 2A shows the cross-section of abase substrate 107 with aconductive layer 108 such as aluminum (Al) deposited, patterned and etched. As shown inFigure 2B , an Inter-Metal Dielectric (IMD)silicon oxide layer 109 is deposited on patternedconductive layer 108 and chemical mechanical polished (CMPed) to planarize the IMDsilicon oxide layer 109.Figure 2C shows a blanketpassivation SiN film 112 deposited on the planarized IMDsilicon oxide layer 109. TheSiN film 112 has a smooth surface with a root-mean-square (RMS) roughness in the order of 1 - 3 nm (nanometers). In an embodiment, to initiate the surface roughening process, a thin film of silicon carbide (SiC) or amorphous Si (not shown) can be deposited onto theSiN film 112. -
Figure 2D shows the cross section of abase substrate 107 with a roughenedSiN surface 112a achieved by local non-uniform etching with wet chemical, gas, or plasma processing. In an embodiment with bump stops with a top layer of SiN film, roughness can be obtained from oxygen-free plasma etching ofSiN film 112 using a mixture of CF4/H2 or SF6/CH4/N2 gas combinations. In the embodiment with bump stops with a top layer of SiC or amorphous Si film, the SiC or amorphous Si film can be etched with a plasma etch followed by further SiN etch for rougher surface. -
Figure 2E shows the cross section of the completedbase substrate 107 after passivation SiN, and patterning and etching IMDsilicon oxide layer 109a to formbump stop 110b, with a top layer ofSiN 112a with a rough surface onbump stop 110b. -
Figures 3A - 3D show a series of cross section drawings ofMEMS substrate 300 processing steps to complete the MEMS device with moveable structures having a rough surface in an embodiment.Figure 3A shows a cross-section of an engineered SOI (ESOI))wafer 310 comprised of adevice layer 307 and ahandle substrate 301 with cavities. Thedevice layer 307 and ahandle substrate 301 are bonded with athin dielectric film 102 in between. In an embodiment, thedevice layer 307 can be thinned before subsequent bonding to a base substrate. AGe film 305 is deposited onto thedevice layer 307 followed by coating andpatterning photoresist 302 to define a standoff. In an embodiment, as shown inFigure 3B , a wet etching step can be performed on theGe film 305 and a dry etching can be performed on a portion of thedevice layer 307 to expose asurface 303a of thedevice layer 307 to formstandoff 304 with aGe film 305 on top. - In an embodiment shown in
Fig 3C , thestandoff 304 is etched after depositing and patterning theGe film 305. As shown inFigure 3C exposedsurface 303a is etched to form arough surface 303b, followed by the removal of the patternedphotoresist 302 and cleaning of the wafer. In different embodiment, thestandoff 304 is patterned and etched before depositing andpatterning Ge film 305. - In an embodiment, the
surface 303a of thedevice layer 307 can be roughened by a plasma-less process such as isotropic silicon wet etch or isotropic silicon dry etch processes. Xenon diflouride (XeF2) dry chemical etch is an example of isotropic etch processes. In an embodiment, the wet etchant contains choline (C5H14NO), potassium hydroxide (KOH), sodium hydroxide (NaOH), lithium hydroxide (LiOH), ethylene diamine pyrocatechol (EDP), tetramethylammonium hydroxide (TMAH), or TMEH. Examples of plasma-less etching gases are xenon diflouride (XeF2), bromine difluoride (BrF2), iodine pentafluoride (IF5), bromine pentafluoride (BrF5), chlorine triflouride (ClF3), or fluorine (F2). - In an embodiment, the
surface 303a of thedevice layer 307 can be roughened by a plasma etch. Sulfur hexafluoride (SF6) plasma dry etch processes is an example of plasma etching process. In an embodiment, the plasma etching gas contains at least one of SF6, CF4, Cl2, HBr, He, Ne, Ar, Kr, or Xe. In an embodiment, the roughness of the etchedsurface 303a could be in the order of 5 - 20 nm. -
Figure 3D , shows a completedMEMS substrate 300. In an embodiment, therough device layer 307 is patterned, and etched to release theMEMS structure 306, Later,MEMS structure 306 is cleaned. -
Figures 4A-4D show a series of cross-section drawings of a second embodiment of the processing steps of providing a rough surface on a silicon substrate. - In an embodiment,
Fig 4A shows asilicon substrate 402 with a smooth surface.Figure 4B shows a thin layer of afilm 404 with a rough surface deposited onto the smooth surface of thesilicon substrate 402 to initiate the roughness. In an embodiment, therough film 404 can be made of poly silicon or silicon carbide. In some embodiments, therough film 404 provides a rough surface on thesilicon substrate 402 and no further etching is required, steps shown inFig 4C and Fig 4D are optional. Other embodiments include further etching of the rough surface.Figure 4C shows an intermediate step of etching therough film 404, resulting in athinner film 404a. In an embodiment, the etching step can be performed by wet etching or dry etching.Figure 4D , shows the final step, where further etching transfers the roughness of therough film 404a to thesilicon substrate 402a.
Claims (15)
- An integrated MEMS device (100) comprising:a MEMS substrate (111) having a first contacting surface; anda base substrate (107) coupled to the MEMS substrate having a second contacting surface;wherein at least one of the first contacting surface and the second contacting surface is roughened;wherein the MEMS substrate includes a handle layer (101) coupled to a device layer (103);the device layer comprises a movable structure (106) suspended above and parallel to the base substrate;the MEMS substrate faces one or more fixed bump stops (110) on the base substrate; andthe surface of the one or more fixed bump stops is roughened.
- The device (100) of claim 1, wherein the roughness of a surface of the movable structure (106) facing the base substrate (107) is greater than 4 nm-rms.
- The device (100) of claim 1, wherein roughness of the one or more fixed bump stops (110) is greater than 4 nm-rms.
- The device (100) of claim 1, wherein one or more fixed bump stops (110) is a dielectric material.
- The device (100) of claim 1, wherein the one or more fixed bump stops (110) is a conducting material.
- The device (100) of claim 1, wherein the one or more fixed bump stops (110) is a semiconducting material.
- The device (100) of claim 1, wherein the movable structure (106) is a portion of any of an actuator, accelerometer, a microphone, a gyroscope, a pressure sensor, or a magnetometer.
- The device (100) of claim 1, wherein the handle layer (101) includes a cavity.
- A method to reduce surface adhesion forces in an integrated MEMS device (100); the integrated MEMS device including a MEMS substrate (110) having a first contacting surface and a handle layer (101) coupled to a device layer (103), the device layer comprising a movable structure (106) suspended above and parallel to the base substrate, the integrated MEMS device further including a base substrate coupled to the MEMS substrate having a second contacting surface and one or more fixed bump stops (110) on the base substrate, the method comprising:etching at least one of the first contacting surface and the second contacting surface to roughen the at least one of the first contacting surface and the second contacting surface; andetching the surface of the one or more fixed bump stops to roughen the surface of the one or more fixed bump stops.
- The method of claim 9 wherein the etching comprises using a plasma-less etching gas to roughen the surface.
- The method of claim 10, where the plasma-less etching gas contains at least one of xenon and fluorine.
- The method of claim 9, wherein the etching comprises using a plasma etching gas to roughen the one contacting surface.
- The method of claim 12, where the plasma etching gas contains at least one of SF6, CF4, F2, O2, N2, CH4, and Xe.
- The method of claim 9 wherein the etching comprises using a wet etchant to roughen the one contacting surface.
- The method of claim 14, where the wet etchant contains choline, KOH, NaOH, LiOH, TMAH, or TMEH.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201361780776P | 2013-03-13 | 2013-03-13 | |
US14/061,152 US20140264655A1 (en) | 2013-03-13 | 2013-10-23 | Surface roughening to reduce adhesion in an integrated mems device |
PCT/US2014/019661 WO2014163985A1 (en) | 2013-03-13 | 2014-02-28 | Surface roughening to reduce adhesion in an integrated mems device |
Publications (3)
Publication Number | Publication Date |
---|---|
EP2973657A1 EP2973657A1 (en) | 2016-01-20 |
EP2973657A4 EP2973657A4 (en) | 2016-09-28 |
EP2973657B1 true EP2973657B1 (en) | 2018-06-20 |
Family
ID=51523773
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP14779860.7A Active EP2973657B1 (en) | 2013-03-13 | 2014-02-28 | Surface roughening to reduce adhesion in an integrated mems device |
Country Status (3)
Country | Link |
---|---|
US (1) | US20140264655A1 (en) |
EP (1) | EP2973657B1 (en) |
WO (1) | WO2014163985A1 (en) |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9618653B2 (en) | 2013-03-29 | 2017-04-11 | Stmicroelectronics Pte Ltd. | Microelectronic environmental sensing module |
US9176089B2 (en) | 2013-03-29 | 2015-11-03 | Stmicroelectronics Pte Ltd. | Integrated multi-sensor module |
US9082681B2 (en) | 2013-03-29 | 2015-07-14 | Stmicroelectronics Pte Ltd. | Adhesive bonding technique for use with capacitive micro-sensors |
US9000542B2 (en) | 2013-05-31 | 2015-04-07 | Stmicroelectronics Pte Ltd. | Suspended membrane device |
US9136165B2 (en) * | 2013-06-04 | 2015-09-15 | Invensense, Inc. | Methods for stiction reduction in MEMS sensors |
US9611133B2 (en) * | 2014-09-11 | 2017-04-04 | Invensense, Inc. | Film induced interface roughening and method of producing the same |
EP3072849B1 (en) * | 2015-03-24 | 2018-04-18 | InvenSense, Inc. | Film induced interface roughening and method of producing the same |
CN107848789B (en) * | 2015-09-17 | 2020-10-27 | 株式会社村田制作所 | MEMS device and method of manufacturing the same |
US9878899B2 (en) | 2015-10-02 | 2018-01-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and apparatus for reducing in-process and in-use stiction for MEMS devices |
US10254261B2 (en) | 2016-07-18 | 2019-04-09 | Stmicroelectronics Pte Ltd | Integrated air quality sensor that detects multiple gas species |
US10429330B2 (en) | 2016-07-18 | 2019-10-01 | Stmicroelectronics Pte Ltd | Gas analyzer that detects gases, humidity, and temperature |
US10557812B2 (en) | 2016-12-01 | 2020-02-11 | Stmicroelectronics Pte Ltd | Gas sensors |
US10745268B2 (en) * | 2017-06-30 | 2020-08-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of stiction prevention by patterned anti-stiction layer |
DE102017119114B4 (en) | 2017-06-30 | 2022-01-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Process to avoid adhesion using a structured non-stick layer |
US11661332B2 (en) | 2019-02-20 | 2023-05-30 | Invensense, Inc. | Stiction reduction system and method thereof |
CN113748081A (en) * | 2019-05-30 | 2021-12-03 | Qorvo美国公司 | MEMS device with reduced contact resistance |
US11253963B1 (en) | 2020-08-17 | 2022-02-22 | Raytheon Company | Separable component assembly having reduced seal stiction |
Family Cites Families (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2001048795A2 (en) * | 1999-12-23 | 2001-07-05 | Applied Materials, Inc. | Fluorine based plasma etch method for anisotropic etching of high open area silicon structures |
US6836366B1 (en) * | 2000-03-03 | 2004-12-28 | Axsun Technologies, Inc. | Integrated tunable fabry-perot filter and method of making same |
WO2002079853A1 (en) * | 2001-03-16 | 2002-10-10 | Corning Intellisense Corporation | Electrostatically actuated micro-electro-mechanical devices and method of manufacture |
US20020176984A1 (en) * | 2001-03-26 | 2002-11-28 | Wilson Smart | Silicon penetration device with increased fracture toughness and method of fabrication |
US7075160B2 (en) * | 2003-06-04 | 2006-07-11 | Robert Bosch Gmbh | Microelectromechanical systems and devices having thin film encapsulated mechanical structures |
US8198974B2 (en) * | 2004-04-23 | 2012-06-12 | Research Triangle Institute | Flexible electrostatic actuator |
US7944599B2 (en) * | 2004-09-27 | 2011-05-17 | Qualcomm Mems Technologies, Inc. | Electromechanical device with optical function separated from mechanical and electrical function |
US8207004B2 (en) * | 2005-01-03 | 2012-06-26 | Miradia Inc. | Method and structure for forming a gyroscope and accelerometer |
US7442570B2 (en) * | 2005-03-18 | 2008-10-28 | Invensence Inc. | Method of fabrication of a AL/GE bonding in a wafer packaging environment and a product produced therefrom |
US20060278942A1 (en) | 2005-06-14 | 2006-12-14 | Innovative Micro Technology | Antistiction MEMS substrate and method of manufacture |
US7372074B2 (en) * | 2005-10-11 | 2008-05-13 | Honeywell International, Inc. | Surface preparation for selective silicon fusion bonding |
US7600533B2 (en) * | 2006-08-10 | 2009-10-13 | California Institute Of Technology | Microfluidic valve having free-floating member and method of fabrication |
US8389314B2 (en) * | 2006-10-03 | 2013-03-05 | Analog Devices, Inc. | MEMS device with roughened surface and method of producing the same |
US8432239B2 (en) * | 2006-11-20 | 2013-04-30 | Massachusetts Institute Of Technology | Micro-electro mechanical tunneling switch |
JP5108489B2 (en) * | 2007-01-16 | 2012-12-26 | 株式会社日立ハイテクノロジーズ | Plasma processing method |
US7659150B1 (en) * | 2007-03-09 | 2010-02-09 | Silicon Clocks, Inc. | Microshells for multi-level vacuum cavities |
US7609136B2 (en) * | 2007-12-20 | 2009-10-27 | General Electric Company | MEMS microswitch having a conductive mechanical stop |
US10040681B2 (en) * | 2009-08-28 | 2018-08-07 | Miradia Inc. | Method and system for MEMS devices |
US8507306B2 (en) * | 2009-09-28 | 2013-08-13 | Analog Devices, Inc. | Reduced stiction MEMS device with exposed silicon carbide |
US8707734B2 (en) * | 2009-10-19 | 2014-04-29 | The Regents Of The University Of Michigan | Method of embedding material in a glass substrate |
WO2011094300A2 (en) * | 2010-01-28 | 2011-08-04 | Microstaq, Inc. | Process and structure for high temperature selective fusion bonding |
US8216882B2 (en) * | 2010-08-23 | 2012-07-10 | Freescale Semiconductor, Inc. | Method of producing a microelectromechanical (MEMS) sensor device |
US8507358B2 (en) * | 2010-08-27 | 2013-08-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Composite wafer semiconductor |
US8319254B2 (en) * | 2011-02-14 | 2012-11-27 | Kionix, Inc. | Micro-electromechanical system devices |
DE102012206875B4 (en) * | 2012-04-25 | 2021-01-28 | Robert Bosch Gmbh | Method for producing a hybrid integrated component and a corresponding hybrid integrated component |
US8350346B1 (en) * | 2012-07-03 | 2013-01-08 | Invensense, Inc. | Integrated MEMS devices with controlled pressure environments by means of enclosed volumes |
-
2013
- 2013-10-23 US US14/061,152 patent/US20140264655A1/en not_active Abandoned
-
2014
- 2014-02-28 EP EP14779860.7A patent/EP2973657B1/en active Active
- 2014-02-28 WO PCT/US2014/019661 patent/WO2014163985A1/en active Application Filing
Non-Patent Citations (1)
Title |
---|
None * |
Also Published As
Publication number | Publication date |
---|---|
EP2973657A1 (en) | 2016-01-20 |
US20140264655A1 (en) | 2014-09-18 |
EP2973657A4 (en) | 2016-09-28 |
WO2014163985A1 (en) | 2014-10-09 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP2973657B1 (en) | Surface roughening to reduce adhesion in an integrated mems device | |
TWI605489B (en) | Method for mems structure with dual-level structural layer and acoustic port | |
US7767484B2 (en) | Method for sealing and backside releasing of microelectromechanical systems | |
US11097941B2 (en) | Method of fabricating semiconductor structure | |
US9573806B2 (en) | MEMS device structure with a capping structure | |
US8802473B1 (en) | MEMS integrated pressure sensor devices having isotropic cavities and methods of forming same | |
JP6108793B2 (en) | Method for forming a structure comprising an active portion having at least one plurality of thicknesses | |
US8722537B2 (en) | Multi-sacrificial layer and method | |
US11661332B2 (en) | Stiction reduction system and method thereof | |
TW201430974A (en) | Method of manufacturing MEMS device | |
US10889493B2 (en) | MEMS method and structure | |
JP2013111745A (en) | Method of producing structure comprising at least one active part having zone of different thickness | |
CN104003348A (en) | Method for mems structure with dual-level structural layer and acoustic port | |
KR20190109725A (en) | Method of stiction prevention by patterned anti-stiction layer | |
US9434602B2 (en) | Reducing MEMS stiction by deposition of nanoclusters | |
US8389314B2 (en) | MEMS device with roughened surface and method of producing the same | |
US20130056858A1 (en) | Integrated circuit and method for fabricating the same | |
US7718457B2 (en) | Method for producing a MEMS device | |
Sun et al. | Post CMOS integration of high aspect ratio SOI MEMS devices | |
JP5827365B2 (en) | Method for forming device packaged at wafer level | |
CN104743497A (en) | Method for monitoring MEMS release performances | |
US9458010B1 (en) | Systems and methods for anchoring components in MEMS semiconductor devices | |
CN118929559A (en) | MEMS device and manufacturing process with reduced Z-axis static friction | |
TW201312649A (en) | Integrated circuit and method for fabricating the same | |
WO2022047977A1 (en) | Method for preparing silicon wafer having rough surface, and silicon wafer |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
17P | Request for examination filed |
Effective date: 20151013 |
|
AK | Designated contracting states |
Kind code of ref document: A1 Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR |
|
AX | Request for extension of the european patent |
Extension state: BA ME |
|
DAX | Request for extension of the european patent (deleted) | ||
A4 | Supplementary search report drawn up and despatched |
Effective date: 20160826 |
|
RIC1 | Information provided on ipc code assigned before grant |
Ipc: H01L 21/00 20060101AFI20160822BHEP |
|
GRAP | Despatch of communication of intention to grant a patent |
Free format text: ORIGINAL CODE: EPIDOSNIGR1 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: GRANT OF PATENT IS INTENDED |
|
INTG | Intention to grant announced |
Effective date: 20180105 |
|
RIN1 | Information on inventor provided before grant (corrected) |
Inventor name: WILLIAMS, KIRT REED Inventor name: SHIN, JONGWOO Inventor name: HUANG, KEGANG Inventor name: LIM, MARTIN Inventor name: XU, WENCHENG |
|
GRAS | Grant fee paid |
Free format text: ORIGINAL CODE: EPIDOSNIGR3 |
|
GRAA | (expected) grant |
Free format text: ORIGINAL CODE: 0009210 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE PATENT HAS BEEN GRANTED |
|
AK | Designated contracting states |
Kind code of ref document: B1 Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR |
|
REG | Reference to a national code |
Ref country code: GB Ref legal event code: FG4D |
|
REG | Reference to a national code |
Ref country code: IE Ref legal event code: FG4D |
|
REG | Reference to a national code |
Ref country code: DE Ref legal event code: R096 Ref document number: 602014027328 Country of ref document: DE |
|
REG | Reference to a national code |
Ref country code: AT Ref legal event code: REF Ref document number: 1011176 Country of ref document: AT Kind code of ref document: T Effective date: 20180715 |
|
REG | Reference to a national code |
Ref country code: NL Ref legal event code: MP Effective date: 20180620 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: LT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20180620 Ref country code: FI Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20180620 Ref country code: BG Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20180920 Ref country code: NO Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20180920 Ref country code: SE Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20180620 |
|
REG | Reference to a national code |
Ref country code: LT Ref legal event code: MG4D |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: GR Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20180921 Ref country code: HR Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20180620 Ref country code: LV Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20180620 Ref country code: RS Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20180620 |
|
REG | Reference to a national code |
Ref country code: AT Ref legal event code: MK05 Ref document number: 1011176 Country of ref document: AT Kind code of ref document: T Effective date: 20180620 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: NL Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20180620 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: SK Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20180620 Ref country code: RO Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20180620 Ref country code: PL Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20180620 Ref country code: EE Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20180620 Ref country code: CZ Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20180620 Ref country code: IS Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20181020 Ref country code: AT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20180620 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: ES Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20180620 Ref country code: SM Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20180620 Ref country code: IT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20180620 |
|
REG | Reference to a national code |
Ref country code: DE Ref legal event code: R097 Ref document number: 602014027328 Country of ref document: DE |
|
PLBE | No opposition filed within time limit |
Free format text: ORIGINAL CODE: 0009261 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT |
|
26N | No opposition filed |
Effective date: 20190321 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: DK Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20180620 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: SI Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20180620 |
|
REG | Reference to a national code |
Ref country code: CH Ref legal event code: PL |
|
GBPC | Gb: european patent ceased through non-payment of renewal fee |
Effective date: 20190228 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: LU Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20190228 Ref country code: MC Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20180620 |
|
REG | Reference to a national code |
Ref country code: BE Ref legal event code: MM Effective date: 20190228 |
|
REG | Reference to a national code |
Ref country code: IE Ref legal event code: MM4A |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: AL Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20180620 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: CH Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20190228 Ref country code: LI Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20190228 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: IE Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20190228 Ref country code: GB Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20190228 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: BE Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20190228 Ref country code: FR Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20190228 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: TR Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20180620 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: MT Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20190228 Ref country code: PT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20181022 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: CY Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20180620 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: HU Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT; INVALID AB INITIO Effective date: 20140228 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: MK Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20180620 |
|
P01 | Opt-out of the competence of the unified patent court (upc) registered |
Effective date: 20230524 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: DE Payment date: 20231229 Year of fee payment: 11 |