TW201312649A - Integrated circuit and method for fabricating the same - Google Patents

Abstract

A method for fabricating integrated circuit is provided. First, a substrate having a micro electromechanical system (MEMS) region is provided. A first interconnect structure and a hard mask layer have been disposed on the MEMS region in sequence. Next, an anisotropic etching process is performed by using the hard mask layer as a photo mask to etch a portion of the first interconnect structure exposed by the hard mask layer. Accordingly, a MEMS structure is formed. A portion of the substrate in MEMS region is exposed by the MEMS structure. Then, an isotropic etching process is performed for removing the portion of the substrate in MEMS region to form a cavity with a center region and a ring-like indentation region. The center region is surrounded by the ring-like indentation region and the MEMS structure suspends above the cavity.

Description

Integrated circuit and manufacturing method thereof

The present invention relates to a method of fabricating an integrated circuit, and more particularly to an integrated circuit having a microelectromechanical structure and a method of fabricating the same.

The development of Micro Electromechanical System (MEMS) technology has opened up a whole new field of technology and industry, which has been widely used in various microelectronic devices with both electronic and mechanical characteristics, such as pressure sensors and acceleration. Detector and micro microphone.

In order to reduce the manufacturing cost of MEMS, most of the current Complementary Metal Oxide Semiconductor (CMOS) processes are used to fabricate MEMS to integrate the process of MEMS and its driver circuits. Therefore, how to innovate or improve the existing integration process of CMOS and MEMS is one of the development priorities of the current MEMS industry.

In view of the above, an object of the present invention is to provide a method of manufacturing an integrated circuit which can etch patterns having different depths on a substrate in a single process.

Another object of the present invention is to provide an integrated circuit that includes a microelectromechanical structure with inconsistent distances from the underlying substrate.

The invention provides a method for manufacturing an integrated circuit, which first provides a substrate having a microelectromechanical system region, and a first interconnect structure and a hard mask layer are formed on the MEMS region of the substrate, wherein the hard mask The layer is located on the first interconnect structure. Continuing, using a hard mask layer as a mask, performing an anisotropic etching process to remove a portion of the first interconnect structure exposed by the hard mask layer, thereby forming a microelectromechanical structure, wherein the microelectromechanical structure is exposed A portion of the substrate of the MEMS region. Thereafter, an isotropic etch is performed to remove portions of the substrate of the MEMS region and a cavity is formed under the MEMS structure. The cavity includes an annular recessed region and a central region, and the annular recessed region surrounds the periphery of the central region, and the microelectromechanical structure is suspended above the cavity.

In an embodiment of the invention, the anisotropic etching process described above is, for example, a reactive ion etching process.

In an embodiment of the present invention, in the above-described anisotropic etching process, for example, tetrafluoromethane and octafluorocyclobutane are used as an etching gas.

In one embodiment of the invention, the flow ratio of tetrafluoromethane to octafluorocyclobutane is 4.

In an embodiment of the invention, in the anisotropic etching process described above, for example, trifluoromethane or ethylfluorocarbon is used as the etching gas.

In one embodiment of the invention, the process temperature of the anisotropic etching process described above is greater than 60 degrees Celsius.

In one embodiment of the invention, the process pressure of the anisotropic etching process described above is between 50 mTorr and 500 mTorr.

In one embodiment of the invention, the process power of the anisotropic etch process described above ranges from 300 watts to 3000 watts.

In an embodiment of the present invention, in the above isotropic etching process, for example, a fluorine-containing gas is used as the etching gas. For example, the fluorine-containing gas is, for example, sulfur hexafluoride, nitrogen trifluoride or tetrafluoromethane.

In an embodiment of the invention, in the isotropic etching process described above, for example, helium or nitrogen is used as the diluent gas.

In one embodiment of the invention, the process temperature of the isotropic etching process described above is between -15 degrees Celsius and 5 degrees Celsius.

In an embodiment of the invention, the first interconnect structure includes a plurality of first dielectric layers and a plurality of first conductive patterns alternately stacked in sequence, and the hard mask layer corresponds to the first The conductive pattern exposes a portion of the first dielectric layer of the uppermost layer. The anisotropic etching process described above is used to remove a portion of the first dielectric layer.

In an embodiment of the invention, after removing a portion of the first interconnect structure exposed by the hard mask layer, the hard mask layer is further removed. For example, the hard mask layer is removed, for example, in the anisotropic etching described above.

In an embodiment of the invention, the substrate further has a logic circuit region, and the second interconnect structure has been formed on the logic circuit region, and the second interconnect structure includes a plurality of layers of the second layer alternately stacked in sequence. The electrical layer and the plurality of second conductive patterns and the at least one connection pad, wherein the connection pads are disposed above the second conductive patterns, and the uppermost second dielectric layer has at least one opening exposing the connection pads. The manufacturing method of the integrated circuit further includes forming a photoresist layer on the second interconnect structure before forming the non-isotropic etching process, and removing the light after performing the anisotropic etching process described above. Resistance layer.

The present invention also provides an integrated circuit comprising a substrate and a microelectromechanical structure. The substrate has a microelectromechanical system region, and the MEMS region has a cavity, and the cavity includes an annular recessed region and a central region, wherein the annular recessed region surrounds the central region. The MEMS structure is partially suspended above the cavity.

In an embodiment of the invention, the ratio of the depth of the annular recessed region to the depth of the central region is between 1.5 and 3.5.

In an embodiment of the invention, the integrated circuit further includes a second interconnect structure, and the substrate further has a logic circuit region, and the second interconnect structure is disposed on the logic circuit region. The second interconnect structure includes a plurality of second dielectric layers and a plurality of second conductive patterns and at least one connection pad alternately stacked in sequence, wherein the connection pads are disposed above the second conductive patterns, and the second uppermost layer The dielectric layer has at least one opening that exposes the connection pads.

In the process of fabricating an integrated circuit, the present invention etches a portion of the underlying portion of the microelectromechanical structure to different depths to form a cavity having an annular recess and a central portion. In this way, the microelectromechanical structure partially suspended on the cavity can have a relatively flexible vibration space.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

The integrated circuit of the present invention is fabricated by a CMOS process. The following embodiment will be described by way of example of a MEMS integrated circuit in a CMOS circuit, but the present invention is not limited thereto. It will be appreciated by those skilled in the art that the present invention is also applicable to MEMS systems that do not have CMOS circuitry.

1A to 1D are schematic cross-sectional views showing an integrated circuit in a manufacturing process in an embodiment of the present invention. Referring to FIG. 1A, a substrate 110 having a logic circuit region 112 and a MEMS region 114 is first provided, wherein the substrate 110 may be a germanium substrate or a silicon on insulator (SOI) substrate. Moreover, at least one semiconductor component 120 has been formed in the logic circuit region 112 of the substrate 110. In the present embodiment, the semiconductor element 120 is, for example, a Complementary Metal Oxide Semiconductor (CMOS). In detail, when a plurality of semiconductor elements 120 are formed in the logic circuit region 112, the semiconductor elements 120 are separated from each other by a shallow trench isolation (STI) 111.

In the above, the first interconnect structure 130 and the second interconnect structure 140 are formed on the substrate 110, wherein the first interconnect structure 130 is located in the MEMS region 114, and the second interconnect structure 140 is located in the logic region 112. . Specifically, the first interconnect structure 130 and the second interconnect structure 140 are simultaneously formed on the substrate 110 in the same process, and the first interconnect structure 130 includes multiple layers sequentially stacked on the substrate 110 in sequence. The first dielectric layer 132 is connected to the plurality of first conductive patterns 134, and the first conductive patterns 134 located in the adjacent two layers are electrically connected to each other through the via plugs 136. The second interconnecting line 140 includes a plurality of second dielectric layers 142 and a plurality of second conductive patterns 144 alternately stacked on the substrate 110 in sequence, and the second conductive patterns 144 located in the adjacent two layers are inserted through the vias. The plugs 146 are electrically connected to each other. The material of the first dielectric layer 132 and the second dielectric layer 142 is, for example, an oxide. In addition, at least a portion of the second conductive pattern 144 is electrically connected to the semiconductor device 120 through the via plug 146.

Next, a hard mask layer 160 is formed on the first interconnect structure 130, wherein the hard mask layer 160 is a first dielectric layer 132 that is exposed corresponding to the first conductive pattern 134. In particular, the hard mask layer 160 may be composed of a metal nitride such as titanium nitride (TiN).

In particular, after the hard mask layer 160 is formed, the protective layer 170 is formed over the first interconnect structure 130 and the second interconnect structure 140 to cover the hard mask layer 160. The protective layer 170 may be a single layer structure or a composite layer structure in which a plurality of film layers are stacked, such as an oxide layer and a nitride layer.

Then, in this embodiment, for example, the partial protective layer 170 above the logic circuit region 112 and the second dielectric layer 142 of the uppermost layer are removed to form an opening 143 of the second conductive pattern 144 with the exposed portion located at the uppermost layer. The exposed second conductive patterns 144 are used as connection pads for electrically connecting the semiconductor device 120 to an external circuit. For example, after exposing the second conductive patterns 144 as connection pads, the semiconductor device 120 on the logic circuit region 112 can be electrically connected to an external circuit for electrical measurement.

Thereafter, a portion of the protective layer 170 is removed to expose the hard mask layer 160. Specifically, the method of removing a portion of the protective layer 170 is, for example, first forming a patterned photoresist layer 180 on the protective layer 170 to define a portion of the protective layer 170 to be removed, and using the patterned photoresist layer 180 as a mask. The cover removes a portion of the protective layer 170 to expose the hard mask layer 160.

Referring to FIG. 1A and FIG. 1B, a non-isotropic etching process is performed on the MEMS region 114 with the hard mask layer 160 as a mask to remove a portion of the first dielectric exposed by the hard mask layer 160. Layer 132, in turn, exposes portions of substrate 110. At this point, a microelectromechanical structure 190 is formed on the MEMS region 114. Thereafter, referring to FIG. 1C, the patterned photoresist layer 180 is removed.

In the present embodiment, the first dielectric layer 132 is removed, for example, by a reactive ion etching (RIE) process, for example, using tetrafluoromethane (CF ₄ ) and an octafluorocarbon ring. Octane fluorocyclobutane (C ₄ F ₈ ) is used as an etching gas, and the flow ratio of tetrafluoromethane to octafluorocyclobutane is, for example, 4. Of course, in other embodiments, trifluoromethane (CHF ₃ ) or Hexafluoroethane (C ₂ F ₆ ) may be used as the etching gas, and the invention is not limited thereto. Moreover, the process temperature of the anisotropic etching process of the present embodiment is, for example, greater than 60 degrees Celsius, and the process pressure is, for example, between 50 mTorr and 500 mTorr, and preferably 174 mTorr. The process power is, for example, between 300 watts and 3000 watts, and preferably 1750 watts.

It is worth mentioning that the first interconnect structure 130 includes a plurality of first dielectric layers 132, that is, in this step, the thickness of the first dielectric layer 132 to be removed is much larger than the hard mask layer. The thickness of 160. Therefore, the hard mask layer 160 can be simultaneously removed in the above-described anisotropic etching process.

Referring to FIG. 1D, an isotropic etching process is performed to remove a portion of the substrate 110 of the MEMS region 114, and a cavity 150 is formed under the MEMS structure 190 such that a portion of the MEMS structure 190 is suspended above the substrate 110. That is, the process of the integrated circuit 100 including the semiconductor element and the microelectromechanical element is substantially completed. Specifically, the microelectromechanical structure 190 of the present embodiment is suspended over the substrate 110, for example, in a cantilever manner, but the present invention is not limited thereto.

In the present embodiment, the isotropic etching process for etching the substrate 110 is, for example, using a fluorine-containing gas as an etching gas. For example, the fluorine-containing gas used in the present embodiment is, for example, sulfur hexafluoride (SF ₆ ), and helium gas or nitrogen gas is used as the diluent gas. In other embodiments, nitrogen trifluoride (NF ₃ ) or tetrafluoromethane (CF ₄ ) may also be used as the etching gas used in the isotropic etching process, and the present invention is not limited thereto. . Moreover, the process temperature of the isotropic etching process of the present embodiment is, for example, between -15 degrees Celsius and 5 degrees Celsius, the process pressure is about 200 mTorr, and the process power is, for example, higher than 5000 watts.

In particular, after removing the portion of the substrate 110 by the isotropic etching process, the formed cavity 150 includes an annular recessed region 152 and a central region 154, wherein the annular recessed region 152 surrounds the central region 154, as shown in the figure. 2 is shown.

In order to make the present invention more familiar with the present invention, the integrated circuit of the present invention will be described below by way of examples.

Referring again to FIG. 1D, the integrated circuit 100 includes a substrate 110 having a microelectromechanical system region 114 and a microelectromechanical system region 114 having a cavity 150 therein, and the cavity 150 including an annular recessed region. 152 and central zone 154, and annular recessed zone 152 surrounds central zone 154. The microelectromechanical structure 190 is then partially suspended above the cavity 150. Specifically, the ratio between the depth D1 of the annular recessed region 152 and the depth D2 of the central region 154 is, for example, between 1.5 and 3.5. For example, the depth D1 of the annular recessed region 152 is, for example, between 71.7 microns and 76.1 microns, and the depth D2 of the central region 154 is about 29.8 microns.

In addition, the integrated circuit 100 further includes a semiconductor component 120 and a second interconnect structure 140 disposed in the logic circuit region 114 of the substrate 110. The second interconnect structure 140 is composed of, for example, a plurality of second dielectric layers 142 and a plurality of second conductive patterns 144 alternately stacked on the substrate 110 in sequence, and the second conductive patterns 144 located in the adjacent two layers. They are electrically connected to each other through the via plugs 146. The microelectromechanical structure 190 is electrically connected to the semiconductor component 120 by the second interconnect structure 140 to control the microelectromechanical structure 190 by the semiconductor component 120.

In summary, in the process of fabricating an integrated circuit, the present invention etches a portion of the underlying portion of the microelectromechanical structure to different depths to form a cavity having an annular recess and a central portion. In this way, the microelectromechanical structure partially suspended on the cavity can have a relatively flexible vibration space.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

100. . . Integrated circuit

110. . . Base

111. . . Shallow trench isolation structure

112. . . Logic circuit area

114. . . MEMS area

120. . . Semiconductor component

130. . . First interconnect structure

132. . . First dielectric layer

134. . . First conductive pattern

136, 146. . . Interlayer plug

140. . . Second interconnect structure

142. . . Second dielectric layer

143. . . Opening

144. . . Second conductive pattern

150. . . Cavity

152. . . Annular depression

154. . . Central District

160. . . Hard mask layer

170. . . The protective layer

180. . . Patterned photoresist layer

190. . . Microelectromechanical structure

D1, D2. . . depth

1A to 1D are schematic cross-sectional views showing an integrated circuit in a manufacturing process in an embodiment of the present invention.

2 is a schematic view of a portion of a substrate in an embodiment of the present invention.

100. . . Integrated circuit

110. . . Base

111. . . Shallow trench isolation structure

112. . . Logic circuit area

114. . . MEMS area

120. . . Semiconductor component

140. . . Second interconnect structure

142. . . Second dielectric layer

143. . . Opening

144. . . Second conductive pattern

146. . . Interlayer plug

150. . . Cavity

152. . . Annular depression

154. . . Central District

170. . . The protective layer

190. . . Microelectromechanical structure

D1, D2. . . depth

Claims (19)

A method of manufacturing an integrated circuit, comprising: providing a substrate, wherein the substrate has a MEMS region, and the MEMS region is formed with a first interconnect structure and a hard mask layer, the hard mask a layer is disposed on the first interconnect structure; and the non-isotropic etching process is performed by using the hard mask layer as a mask to remove a portion of the first interconnect structure exposed by the hard mask layer Forming a microelectromechanical structure, the microelectromechanical structure exposing a portion of the substrate of the MEMS region; and performing an isotropic etching process to remove a portion of the substrate of the MEMS region, A cavity is formed under the microelectromechanical structure, wherein the cavity includes an annular recessed region and a central region surrounding the central region, and the microelectromechanical structure is suspended above the cavity. The method of manufacturing an integrated circuit according to claim 1, wherein the anisotropic etching process comprises a reactive ion etching process. The method of manufacturing an integrated circuit according to claim 2, wherein in the anisotropic etching process, tetrafluoromethane and octafluorocyclobutane are used as an etching gas. The method of manufacturing an integrated circuit according to claim 3, wherein a flow ratio of tetrafluoromethane to octafluorocyclobutane is 4 in the anisotropic etching process. The method of manufacturing an integrated circuit according to claim 2, wherein in the anisotropic etching process, trifluoromethane or ethyl fluorocarbon is used as an etching gas. The manufacturing method of the integrated circuit according to claim 1, wherein the process temperature of the anisotropic etching process is greater than 60 degrees Celsius. The manufacturing method of the integrated circuit according to claim 1, wherein the process pressure of the anisotropic etching process is between 50 mTorr and 500 mTorr. The manufacturing method of the integrated circuit according to claim 1, wherein the process power of the anisotropic etching process is between 300 watts and 3000 watts. The method of manufacturing an integrated circuit according to claim 1, wherein in the isotropic etching process, a fluorine-containing gas is used as the etching gas. The method of manufacturing an integrated circuit according to claim 9, wherein the fluorine-containing gas comprises sulfur hexafluoride, nitrogen trifluoride or tetrafluoromethane. The method of manufacturing an integrated circuit according to claim 9, wherein in the isotropic etching process, helium or nitrogen is further used as the diluent gas. The method of manufacturing an integrated circuit according to claim 1, wherein the process temperature of the isotropic etching process is between -15 degrees Celsius and 5 degrees Celsius. The method of manufacturing the integrated circuit of claim 1, wherein the first interconnect structure comprises a plurality of first dielectric layers and a plurality of first conductive patterns alternately stacked in sequence, and the hard mask The layer corresponds to the first conductive patterns to expose a portion of the first dielectric layer of the uppermost layer, and the anisotropic etching process is used to remove a portion of the first dielectric layers. The method of manufacturing an integrated circuit according to claim 1, wherein after removing the portion of the first interconnect structure exposed by the hard mask layer, the hard mask layer is further removed. The method of manufacturing an integrated circuit according to claim 1, further comprising removing the hard mask layer in the anisotropic etching process. The manufacturing method of the integrated circuit of claim 1, wherein the substrate further has a logic circuit region, and the second circuit structure is formed on the logic circuit region, the second interconnect structure The method includes a plurality of second dielectric layers and a plurality of second conductive patterns and at least one connection pad alternately stacked, wherein the connection pads are disposed above the second conductive patterns, and the second dielectric layer of the uppermost layer has Exposing at least one opening of the connection pad, and before performing the anisotropic etching process, further comprising forming a patterned photoresist layer on the second interconnect structure, and after performing the anisotropic etching process Removing the patterned photoresist layer. An integrated circuit includes: a substrate having a MEMS region, and having a cavity in the MEMS region, wherein the cavity includes an annular recessed region and a central region, the annular recessed region surrounding The central region; and a microelectromechanical structure partially suspended above the cavity. The integrated circuit of claim 17, wherein the ratio of the depth of the annular recessed region to the depth of the central region is between 1.5 and 3.5. The integrated circuit of claim 17, further comprising a second interconnect structure, wherein the substrate further has a logic circuit region, and the second interconnect structure is disposed on the logic circuit region. And comprising a plurality of second dielectric layers and a plurality of second conductive patterns and at least one connection pad alternately stacked, wherein the connection pads are disposed above the second conductive patterns, and the second dielectric of the uppermost layer The layer has at least one opening that exposes the connection pad.