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EP2577826A2 - Détecteur de défaut d'arc destiné à des installations à courant alternatif ou à courant continu - Google Patents

Détecteur de défaut d'arc destiné à des installations à courant alternatif ou à courant continu

Info

Publication number
EP2577826A2
EP2577826A2 EP11723040.9A EP11723040A EP2577826A2 EP 2577826 A2 EP2577826 A2 EP 2577826A2 EP 11723040 A EP11723040 A EP 11723040A EP 2577826 A2 EP2577826 A2 EP 2577826A2
Authority
EP
European Patent Office
Prior art keywords
arc fault
core
supply
voltage
conductors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP11723040.9A
Other languages
German (de)
English (en)
Inventor
Patrick Ward
Brien Daniels
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shakira Ltd
Original Assignee
Shakira Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shakira Ltd filed Critical Shakira Ltd
Publication of EP2577826A2 publication Critical patent/EP2577826A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H1/00—Details of emergency protective circuit arrangements
    • H02H1/0007—Details of emergency protective circuit arrangements concerning the detecting means
    • H02H1/0015—Using arc detectors

Definitions

  • This invention relates to an arc fault detector for AC or DC installations.
  • Arcing is a normal consequence of switching loads on or off. Such normal arcing occurs within the switch and is usually of relatively short duration. As a result it rarely results in a hazardous condition.
  • arc fault conditions can arise anywhere along a circuit or installation which can give rise to high and sustained levels of arcing which can result in electrical fires, and it is desirable to detect and eliminate such arcing faults quickly and effectively.
  • Arc fault detectors also known as arc fault circuit interrupters (AFCIs) are intended to provide protection against such faults.
  • US 5,706,154 detects arcing by passing the load conductor through an interrupted transformer core. An arcing fault causes arcing across the gap in the core. This heats a bi-metal strip which causes the contacts to open.
  • US 7,253,637, US 6,259,996 and US 7,151 ,656 use ferrite, iron or molded permeable cores which are designed to operate at frequencies less than about 10kHz.
  • Arcing is often referred to as having a signal which can be detected, or a signature which can be recognised and detected.
  • processing of the detected signals can involve filters, timers, data extraction, algorithms, microprocessors, etc.
  • the processing element is the most sophisticated and complex part of the entire system, adding considerably to cost and reliability problems.
  • an arc fault detector comprising a current transformer (CT) having a primary winding and a secondary winding, the primary winding being formed by at least one conductor of an AC or DC supply circuit , the inductance of the CT being selected so that the CT has a lower frequency operating point (LFOP) of at least 10 KHz, the detector also comprising circuitry for disconnecting the supply if the voltage induced in the secondary winding meets predetermined criteria as to magnitude and duration.
  • CT current transformer
  • LFOP lower frequency operating point
  • winding is used in relation to the primary in accordance with conventional terminology, even though the primary may constitute a single conductor passing through the CT.
  • the invention applies both to arrangements in which the vector sum of currents flowing in the primary conductor(s) at normal operating frequency is zero under normal supply conditions and also to arrangements in which the vector sum of currents flowing in the primary conductor(s) at normal operating frequency is greater than zero under normal supply conditions.
  • the current transformer has an air core or a ferrite core, and an LFOP within the range 150 KHz to 350 KHz.
  • the supply circuit is a single phase AC supply comprising live and neutral conductors and the CT has a core which surrounds the live conductor only.
  • the supply circuit is a two phase AC supply and the CT has a core which surrounds both phase conductors whose currents pass in the same direction through the core such that the vector sum of the currents passing through the core is greater than zero during normal operating conditions.
  • the supply circuit is a multi phase AC supply and a respective CT core surrounds each of the supply conductors.
  • the supply circuit is a single phase AC supply comprising live and neutral conductors and the CT has a core which surrounds both conductors such that the vector sum of the currents passing through the core is greater than zero during normal operating conditions.
  • the supply circuit is a multi phase AC supply and the CT has a core which surrounds all of the supply conductors such that the vector sum of the currents passing through the core is zero during normal operating conditions.
  • the supply circuit is a DC supply and the CT has a core which surrounds one of the supply conductors.
  • the detection circuitry comprises a first comparator for providing an output pulse each time the voltage induced in the secondary winding rises above a first threshold level, a pulse stretcher for stretching the output pulses of the first comparator, a second comparator for providing an output pulse each time the voltage of a stretched output pulse rises above a second threshold level, a voltage integrator for the output pulses of the second comparator, and a third comparator for providing an output pulse when the integrated voltage rises above a third threshold level.
  • the arc fault detector may further include a test circuit comprising a further CT primary winding and a test signal generator for generating in the further primary winding a voltage which will induce a voltage representative of an arc fault in the secondary winding.
  • a key characteristic of arcing under fault conditions is that the arc produces a substantial amount of energy each time the arc is established and current flow results.
  • the arcing condition causes the arc current to make and break at a very rapid rate and at frequencies substantially higher than the normal mains supply frequency.
  • the current produced under series arcing conditions can be as much as the full load current that would flow under non fault conditions, and can be of several amperes for parallel arc fault conditions.
  • arcing produces a relatively large amount of energy at high frequencies during arcing occurrences. This is evidenced by US 5,706,154 (GEC) which indicates how the energy from an arc fault current can be harnessed and transformed into heat to achieve tripping of an AFD.
  • the embodiments of the present invention "harness" the energy produced by the arc fault current as the primary means of detection, the characteristics of the arcing current in terms of its wave shape, form or signature, etc., not being of significance for the correct functioning of the embodiments.
  • the harnessed energy is in the form of the RMS value of the current induced into a current transformer by an arc fault current which is used to trip an AFD.
  • an arc fault detector including a current transformer (CT) having a primary winding comprising at least one conductor of an AC or DC supply and a secondary winding connected to circuitry for detecting a voltage induced in the secondary winding
  • CT current transformer
  • Figure 1 is a schematic diagram showing the nature of series and parallel arcing.
  • FIG. 2 is a schematic circuit diagram of a known type of residual current device (RCD).
  • RCD residual current device
  • Figure 3 is a schematic circuit diagram of a current transformer and is helpful in explaining the embodiments of the invention.
  • FIGS 4 and 5 are waveforms helpful in explaining the embodiments of the invention.
  • Figure 6 shows energy transfer rates plotted against frequency for three transformer core materials.
  • Figure 7 is a modification of Figure 3.
  • Figure 8 is a schematic diagram of a first embodiment of the invention as used with an AC supply.
  • Figure 8a is a schematic diagram of an alternative embodiment of the invention as used with a DC supply.
  • Figure 9 is a schematic diagram showing series and parallel arcing in a two phase AC mains supply.
  • Figures 10 and 1 1 are schematic diagrams of further embodiments of the invention.
  • Figure 12 is a circuit diagram of a still further embodiment of the invention.
  • Figures 13 to 17 are waveform diagrams useful in explaining the operation of the embodiment of Figure 12.
  • Figure 18 shows a still further embodiment of the invention including a test circuit.
  • Figure 19 shows an embodiment in which a single CT is used for detection of arc fault currents in a multiphase circuit.
  • Figures 20a, 20b and 20c demonstrate how the Figure 19 embodiment exploits the phenomenon of core imbalance.
  • Figure 21 is an embodiment for a single or two phase circuit based on a balanced CT arrangement.
  • FIG 2 is an example of a known type of residual current device (RCD), also known as a ground fault circuit interrupter (GFCI).
  • RCD residual current device
  • GFCI ground fault circuit interrupter
  • a single phase AC mains supply to a load LD comprises live L and neutral N conductors which pass through the core 20 of a current transformer CT.
  • the currents li_ and IN in the live and neutral conductors flow in opposite directions through the core. These conductors serve as a primary "winding" of the current transformer CT, and a winding W1 on the core serves as a secondary of the current transformer.
  • the mains frequency current induced in the winding W1 is detected by a WA050 RCD integrated circuit (IC) 10.
  • the WA050 IC 10 is an industry standard RCD IC supplied by Western Automation Research &
  • the arrangement of Figure 3 comprises a 230V/50Hz mains supply, live and neutral conductors L, N respectively, a load LD comprising (in this example) a domestic vacuum cleaner, and a current transformer CT with a core 20 comprising a permeable material such as soft iron.
  • a resistive load could have been used, but a vacuum cleaner was chosen as the load because it tends to produce a relatively high level of electrical noise or interference signals on the mains supply and could therefore produce more onerous conditions for detection of a coincident arc fault current.
  • a secondary winding W1 As before there is a secondary winding W1 , but the important difference is that only the live conductor L passes through the CT core 20 as the primary winding.
  • Figure 4 shows the voltage generated by the CT (i.e. across the winding W1 ) in response to the load current and a coincident series arc fault condition based on the arrangement of Figure 3, with the LFOP of the CT set at or close to the mains supply frequency.
  • Figure 4 comprises a waveform substantially at the mains frequency.
  • the wave shape is not a pure sine wave due to partial saturation of the soft iron core caused by the load current of several amperes.
  • the first part of the waveform (roughly the left hand two thirds) shows the pre-arcing state and the second part (the right hand third) shows the output under an arc fault condition. It is very difficult to distinguish between the normal load current and the arc fault current states, and it would require considerable effort to develop means which could use this CT output to reliably differentiate between the arc fault and non arc fault conditions.
  • the CT could be made less responsive to the mains frequency of the normal load currents and more responsive to the high frequency components of the arc fault currents.
  • the CT in Figure 3 by altering the CT in Figure 3 to have an LFOP of about 10KHz, the non arcing and arcing responses of the CT were significantly changed, as shown in Figure 5.
  • the pre-arcing waveform and the arcing waveform produced by the CT are substantially different, making differentiation between the two states much more obvious. Therefore, by more closely matching (i.e. making more equal) the LFOP of the CT to the frequency of the targeted source current (arc current), energy transfer between primary and secondary circuits can be maximised.
  • the pre-arcing output from the CT can be considered to be quiescent "noise” caused by the normal load current, as produced by the vacuum cleaner in this case, and the arcing waveform can be considered to be an arc fault "indicative signal" induced by the arcing current energy.
  • the "noise” and the indicative signal will each have an RMS value which can be measured and quantified.
  • the ratio of the two RMS values can be considered to be a qualitative value indicating the extent to which energy is transferred from the CT primary circuit to its secondary circuit by the arcing current. For the purpose of this specification, this ratio is referred to as the energy transfer ratio, ETR.
  • ETR energy transfer ratio
  • the ETR was calculated to have a value of about 1
  • the ETR was about 4.
  • a low ETR makes it difficult to distinguish between arc fault and non arc fault conditions.
  • the LFOP of the CT was set to several values over the range of about 2 KHz to 1 MHz by changing the inductance value of the CT, and the ETR value was calculated at various frequency points over the range. This was repeated by replacing the soft iron core of the CT with an air core and then with a ferrite core, to determine the impact on ETR of using different CT core materials across the same frequency range.
  • Figure 6 shows a plot of ETR versus frequency for the three CT core materials over the above frequency range. The ETR axis is linear whilst the frequency axis is logarithmic.
  • the ETR value for the soft iron core was relatively low over the frequency range, having a maximum value of about 4 within the range 25 KHz to about 75 KHz and then decreasing thereafter.
  • the ETR value for the air core increased rapidly from about 50 KHz and peaked at about 27 at 150 KHz with a gradual decrease thereafter to about 600 KHz.
  • the ETR value increased rapidly from the start point of 2 KHz and peaked at about 48 at 200 KHz, after which it fell off rapidly.
  • the peak ETR value indicates the frequency point at which maximum energy was transferred from the arcing current by the CT. This frequency point was approximately 150 KHz for the air core CT and about 200 KHz for the ferrite core.
  • the rate of decrease in ETR values was lower for frequencies just above 150KHz than for
  • the optimum LFOP for the air core CT and the ferrite core CT is in the range 150KHz to about 350KHz, after which the ETR value decreases significantly. This frequency range therefore represents the optimum operating (i.e. LFOP) range of either of these CTs for arc fault current detection.
  • the ferrite CT core provided the best results in terms of ETR values.
  • a CT core made from any magnetically responsive material including ferrite will be more expensive in comparison to a CT based on an air core.
  • the magnetically responsive core material will cause more variances in the characteristics or performance across a range of CTs, such as permeability, the effects of temperature, RMS output, etc. which would result in additional production problems and costs in comparison to an air cored CT.
  • the core geometry could also place constraints on design options.
  • the air core may be a conventional CT wound on a core containing no magnetically responsive material, or may advantageously be produced in the form of a Rogowski coil which has a relatively low inductance compared to cores based on soft iron or ferrite and is especially suited to detecting high frequency components.
  • the air core CT mitigates most of the problems associated with the use of a CT core comprising magnetically responsive material.
  • Figure 7 shows the circuit of Figure 3 modified to use a Rogowski coil as an air core, and subsequent embodiments of the invention may be similarly modified to use Rogowski coils.
  • the magnitude of the energy transferred from the CT primary circuit to its secondary circuit is largely determined by the choice of the lower frequency operating point (LFOP) and the CT core material.
  • the CT may produce an output in response to the normal load current, noise, low level arcing or arcing caused by load switching, but these will not induce sufficient energy into the CT to produce an output that exceeds predetermined time and magnitude thresholds.
  • arcing currents such as those caused under arc fault conditions result in multiple flows and interruptions of relatively high level currents at very fast rates. The energy produced by these sudden bursts of current will result in energy transfer to the CT secondary circuit of sufficient magnitude and duration to facilitate detection.
  • FIG. 8 shows a first embodiment of an AFD according to the invention, based upon the above principles.
  • a single phase AC mains supply to a load LD comprises live L and neutral N conductors.
  • a series or parallel arc fault condition in each case indicated by an X, has occurred in the circuit.
  • the full load current I Prior to the arc fault condition, the full load current I will flow in the live conductor L.
  • the arc fault condition will result in an arcing current flow with a broad spectrum of frequencies in the circuit.
  • the energy from the arcing current is harnessed to facilitate detection of the arc fault.
  • the CT will have minimal response to slowly rising or sustained load currents at the mains supply frequency but will be highly responsive to current pulses with very fast rise times which would be generated by arcing.
  • the arcing current induces a voltage across W1 which is detected by the WA050 RCD integrated circuit 10. If the voltage developed across W1 is of sufficient magnitude and duration, the IC 10 will produce an output which will cause the mechanical actuator 12 to open the ganged switch contacts SW in the live and neutral conductors to disconnect the mains supply.
  • Switches can produce normal arcing when switching loads on and off, but immunity against unwanted tripping is provided because such arcing is generally not sustained beyond the response time set on the WA050 IC 10.
  • the embodiment of Figure 8 shows how arc faults can be detected in a single conductor in an AC supply system.
  • Figure 8a shows how the invention can be applied to a DC system.
  • the load is supplied from a DC supply which may be derived from any convenient DC source.
  • the core 20 surrounds the DC negative conductor and in the event of a series arc fault condition as
  • the arcing current will induce a voltage across W1 which will be detected by the WA050 RCD integrated circuit 10 as previously described.
  • an optional capacitor C1 is shown placed in parallel with the CT secondary winding W1 to cause oscillations between the CT and the capacitor in response to the arcing current energy. This causes an effective stretching of the output pulses produced by the CT and facilitates easier detection of the CT output.
  • Such a capacitor may advantageously be placed across the winding W1 in any of the embodiments herein.
  • Some installations use a two phase supply as shown in Figure 9 which is an example of an installation with two phases, L1 and L2, and a centre point earth E. Parallel arc faults are shown between each phase and earth, as an example, and it would be beneficial to detect such faults regardless of which phase they occurred on.
  • Figure 10 shows how arc faults on either phase can be detected by a single arc fault detecting circuit.
  • the core 20 surrounds both the L1 and L2 phase conductors whose currents pass in the same direction through the core.
  • the current flowing through the CT is twice that of the load current but the CT characteristics and the associated circuitry are chosen to ensure that the arc fault detecting circuit is not responsive under normal operating conditions.
  • a series arc fault occurring along either conductor or a parallel arc fault occurring from either line to earth will be detected as previously described.
  • Figure 1 1 shows an embodiment of the invention for arc fault detection in a three phase installation.
  • Each conductor N, 1 , 2, and 3 in the three phase installation is passed through a separate CT core each having its own arc fault detection circuitry W1 , 10 (shown only for conductor 3), and if there is a series or parallel arc fault, a common actuator 12 is activated as before and all four poles will open.
  • Figure 12 shows an alternative circuit arrangement which can be used for detection of the CT output signals in the AFDs of Figures 8, 10, 1 1 or 18 (to follow), in place of the WA050 IC 10.
  • the output of the CT ( Figure 13) is fed to a first comparator, Comp 1 .
  • Comp 1 This has a reference voltage Vrefl on its negative input terminal and the CT output voltage is fed to the positive input terminal . Only voltages which exceed Vrefl level will be detected by Comp 1 and produce output voltages of approximately Vcc level . It follows that all negative going voltages are ignored by Comp 1 .
  • the voltage pulses ( Figure 14) produced by Comp 1 are fed to a pulse stretching stage comprising of diode D, capacitor C1 and resistor R. Diode D allows C1 to charge up very rapidly for each pulse produced by Comp 1 .
  • Resistor R is a bleed resistor which controls the rate of discharge of C1 .
  • Comp 2 is a second comparator with a reference voltage Vref2 on its negative terminal .
  • the voltage developed across capacitor C1 is fed to the positive terminal of Comp 2.
  • Vref2 the voltage developed across capacitor C1
  • Comp 2 output will go high.
  • C1 acquires a charge from each pulse produced by Comp 1 very rapidly, the voltage on C1 will exceed Comp 2 reference level for a sustained period as determined by the discharge rate of C1 and R; thus Comp 2 output pulses will be wider than Comp 1 output pulses.
  • Figure 15 shows the stretched pulses fed to Comp 2 and Figure 16 shows the resultant square wave output pulses from Comp 2.
  • Comp 3 produces an output ( Figure 17).
  • C2 acts as a voltage integrator so that Comp 3 output will only go high if the current transformer CT produces sufficient pulses of sufficient magnitude sustained over a certain period of time indicative of an arc fault current.
  • Figure 17 it will be seen that the onset of the Comp 3 output is delayed until sufficient charge has built up on C2 for the voltage thereon to exceed Vref3, and persists after the arcing event until leakage on C2 once again brings the voltage thereon below Vref3.
  • the circuit of Figure 12 provides for detection of arc fault current induced voltage pulses of a certain level in the form of a cluster sustained for a certain period of time.
  • the pulse detection circuit of Figure 12 could use a diode rectifier as a first stage so as to combine rectification with threshold setting, or a full wave rectifier stage could be added so as to capture positive and negative going pulses from the CT. Because the CT response has been optimised for operation at frequencies above about 150KHz, lower frequency components produced by the CT will be of relatively low amplitude or magnitude and will be largely ignored, so filtering of the CT output is not required before it is fed to the electronic processing circuit, e.g. the WA050 IC of Figure 8 or the electronic circuit of Figure 12.
  • the flawed devices may have a non functioning AFD section, have too low or too high an operating arc fault current threshold or be prone to nuisance tripping, etc.
  • Testing of arc fault currents within UL1699 is generally carried out at the amperes level, typically greater than 2 amperes, whereas RCD/GFCI testers generally generate test currents within the milliampere region, typically less than 100mA.
  • Such residual currents are not representative of arc fault currents.
  • parallel arc faults between lines and series arc faults will not have a residual current element to them, so it is not possible to verify arc fault detection under these conditions simply by the use of a relatively low level residual current to earth. There is therefore a question mark over the validity of the testing of many AFDs.
  • Figure 18 shows an arc fault detector as previously described with reference to Figure 8, but with an additional test circuit comprising a second winding W2 on the CT core 20, and a test signal generator 50 which is powered from the mains supply when a normally open test switch 52 is manually closed .
  • the signal generator When the signal generator is powered up it produces a series of pulses at a frequency representative of an arc fault condition. It can be seen from Figure 6 that with a ferrite core the RMS energy transfer ratio increases rapidly from frequencies above about 10KHz, and for an air core CT the RMS energy transfer ratio increases rapidly from about 40KHz.
  • the pulses produced by the signal generator may be a continuous series of pulses or a burst of pulses.
  • winding W2 acts as a CT primary winding so as to induce energy into the arc current detecting secondary winding W1 .
  • the frequency and the amplitude of the voltage pulses produced by the signal generator combined with the number of turns in W2 are selected so as to ensure that the resultant ampere turns in W2 is representative of an arc fault current rather than a mains frequency residual current.
  • the resultant output from W1 is detected by the arc current detection circuit as before, and causes automatic opening of the contacts. In this manner the requirement of subclause 15.1 of UL1699 is met by the standalone AFD.
  • this test technique may be used to provide an efficient and cost effective means of carrying out testing on 100% of production and can be used in any of the embodiments herein.
  • the amplitude of the pulses produced by the signal generator may be reduced to a certain level to verify non tripping at the lower level and thereby verify the minimum operating threshold of the AFD so as to mitigate the risks of nuisance tripping due to over sensitivity.
  • the invention can be used for detection of arc fault conditions in AC and DC circuits because its operation is dependent on energy induced into the current transformer CT and this can be derived from arcing produced on AC or DC circuits.
  • the RCD shown in Figure 2 has both conductors passing through the CT such that the vector sum of the load currents as seen by the CT is zero. This is referred to as a balanced arrangement.
  • the conductor(s) were passed through the CT so as to always result in a non-zero vector sum. This is referred to as a differential arrangement.
  • the prior art has always used differential arrangements in AFDs. Whilst it can be seen from Figures 8 and 10 that a single CT can be used for the detection of arc fault currents in single phase or two phase installations, the arrangement of Figure 1 1 shows that several CTs are required for arc fault current detection in a multiphase installation.
  • the differential arrangement has several drawbacks, not least of which is the complexity associated with multiphase circuits.
  • Figure 19 shows an embodiment in which a single CT is used for the detection of arc fault currents in a multiphase circuit.
  • the detection circuit is as described with reference to Figure 12, although it could use a WA050 RCD integrated circuit as in previous embodiments. It can be seen from Figure 19 that the four conductors of a three phase supply all pass through the CT core in the same direction such that the vector sum of the currents flowing in the conductors is zero under normal conditions, a balanced arrangement. It was previously stated that a conventional residual current detecting circuit could not normally be used for arc fault detection.
  • the embodiment of Figure 19 exploits the phenomenon of core imbalance to detect arc fault currents. Asymmetry in the CT windings is intentionally introduced because it will have negligible effect under full load conditions at normal supply frequency but will have significant effects at arc fault current frequencies.
  • Figures 20a, 20b and 20c show the signal monitored at the Comp 1 output of Figure 12 for a series arc fault current of magnitude l x for three arrangements as follows.
  • a balanced CT arrangement was used for a multiphase circuit as shown in Figure 19 where all of the supply conductors of a three phase supply pass through the CT in the same direction so that the vector sum of the load currents seen by the CT is effectively zero, the CT winding being optimized to minimize core imbalance.
  • CT winding as used in the description of Figures 19 to 21 covers both the manner in which the winding W1 is placed on the CT and the manner in which the load conductors are fed through the CT core aperture.
  • the CT winding was arranged to maximize core imbalance so as to exploit the effects of CT asymmetry.
  • the CT has been designed to have a certain LFOP as previously described. Because the CT will be largely non responsive to full differential load currents at normal supply frequencies as previously described, it will also be largely non responsive to imbalance currents at normal supply frequencies in a balanced arrangement. The CT will be highly responsive to differential currents at frequencies above the LFOP, so parallel arc fault currents will be detected as previously described.
  • FIG. 21 shows a balanced arrangement for detection of arc fault currents in a single phase circuit (N, L), a two phase circuit (L1 , L2) or a DC supply circuit (DC+, DC-). If desired the invention could be used with an RCD to combine the functions of arc fault protection with shock protection and ground fault protection, etc.

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  • Testing Relating To Insulation (AREA)
  • Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
  • Protection Of Transformers (AREA)

Abstract

La présente invention a trait à un détecteur de défaut d'arc qui comprend un transformateur de courant (CT) doté d'un enroulement primaire et d'un enroulement secondaire (W1), l'enroulement primaire étant constitué au moins d'un conducteur (L) de circuit d'alimentation en courant alternatif ou en courant continu. L'inductance du CT est sélectionnée de manière à ce que le CT ait un point de fonctionnement de fréquence inférieure (LFOP) d'au moins 10 KHz. Le détecteur comprend également un ensemble de circuits (10, 12, SW) permettant de déconnecter l'alimentation si la tension induite dans l'enroulement secondaire répond à des critères prédéterminés en termes d'amplitude et de durée.
EP11723040.9A 2010-06-03 2011-05-27 Détecteur de défaut d'arc destiné à des installations à courant alternatif ou à courant continu Withdrawn EP2577826A2 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
IE20100361 2010-06-03
IE20100534 2010-09-02
PCT/EP2011/058754 WO2011151267A2 (fr) 2010-06-03 2011-05-27 Détecteur de défaut d'arc destiné à des installations à courant alternatif ou à courant continu

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EP2577826A2 true EP2577826A2 (fr) 2013-04-10

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Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2990322B1 (fr) * 2012-05-01 2016-09-09 Ge Aviat Systems Ltd Dispositif et procede pour detecter l'amorcage d'un arc electrique
GB2501693B (en) * 2012-05-01 2016-01-20 Ge Aviat Systems Ltd Apparatus and method for arc fault detection
US9634479B2 (en) 2012-11-16 2017-04-25 Sensata Technologies, Inc. Noise propagation immunity of a multi-string arc fault detection device
US9465909B2 (en) * 2012-11-16 2016-10-11 Sensata Technologies, Inc. Systems and methods of discriminating DC arcs and load switching noise
US9897642B1 (en) 2014-03-27 2018-02-20 National Technology & Engineering Solutions Of Sandia, Llc Detection of arcing location on photovoltaic systems using filters
WO2016001824A1 (fr) 2014-06-30 2016-01-07 Societa' Elettrica S.R.L. Dispositif de protection d'une centrale photovoltaïque à courant continu
CN104601105B (zh) * 2015-01-08 2017-04-26 西安交通大学 一种非正常光照条件下的光伏系统故障电弧检测方法
TWI537570B (zh) * 2015-11-20 2016-06-11 台達電子工業股份有限公司 改良型電弧偵測裝置
GB2546743B (en) 2016-01-26 2019-02-13 Shakira Ltd An arc fault current detector
FR3053798B1 (fr) * 2016-07-11 2020-08-14 Commissariat Energie Atomique Procede et dispositif de detection d'un arc electrique dans une installation photovoltaique
ES2880955T3 (es) * 2016-08-11 2021-11-26 Fimer S P A Una disposición de detección de fallas de arco para bus eléctrico de CC
US11742651B2 (en) 2019-05-10 2023-08-29 Hamilton Sundstrand Corporation Systems and methods for arc fault detection built-in-test

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999043066A1 (fr) * 1998-02-19 1999-08-26 Square D Company Detection d'arcs de court-circuit par zones
US20030058596A1 (en) * 2000-03-04 2003-03-27 Macbeth Bruce F. Two winding resonating arc fault sensor which boosts arc fault signals while rejecting arc mimicking noise
WO2004102760A1 (fr) * 2003-05-19 2004-11-25 Ellenberger & Poensgen Gmbh Procede et dispositif de detection d'arcs electriques perturbateurs
US20070262780A1 (en) * 2003-12-22 2007-11-15 Leviton Manufacturing Company, Inc. Arc fault detector

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6259996B1 (en) 1998-02-19 2001-07-10 Square D Company Arc fault detection system
US5706154A (en) 1996-10-04 1998-01-06 General Electric Company Residential circuit breaker with arcing fault detection
US6373257B1 (en) * 1998-12-09 2002-04-16 Pass & Seymour, Inc. Arc fault circuit interrupter
US7035066B2 (en) * 2000-06-02 2006-04-25 Raytheon Company Arc-default detecting circuit breaker system
US7151656B2 (en) 2001-10-17 2006-12-19 Square D Company Arc fault circuit interrupter system
AU2003216697B2 (en) 2002-06-24 2007-11-22 Shakira Limited Residual current detection circuit
US7009406B2 (en) * 2003-04-24 2006-03-07 Delphi Technologies, Inc. Arc fault detector and method
US7253637B2 (en) 2005-09-13 2007-08-07 Square D Company Arc fault circuit interrupter system
IES20070918A2 (en) 2007-12-19 2009-03-18 Atreus Entpr Ltd A current transformer

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999043066A1 (fr) * 1998-02-19 1999-08-26 Square D Company Detection d'arcs de court-circuit par zones
US20030058596A1 (en) * 2000-03-04 2003-03-27 Macbeth Bruce F. Two winding resonating arc fault sensor which boosts arc fault signals while rejecting arc mimicking noise
WO2004102760A1 (fr) * 2003-05-19 2004-11-25 Ellenberger & Poensgen Gmbh Procede et dispositif de detection d'arcs electriques perturbateurs
US20070262780A1 (en) * 2003-12-22 2007-11-15 Leviton Manufacturing Company, Inc. Arc fault detector

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO2011151267A2 *

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