EP2294637A1 - Field effect superconductor transistor and method for making such transistor - Google Patents
Field effect superconductor transistor and method for making such transistorInfo
- Publication number
- EP2294637A1 EP2294637A1 EP09769498A EP09769498A EP2294637A1 EP 2294637 A1 EP2294637 A1 EP 2294637A1 EP 09769498 A EP09769498 A EP 09769498A EP 09769498 A EP09769498 A EP 09769498A EP 2294637 A1 EP2294637 A1 EP 2294637A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- channel
- transistor
- superconducting
- layer
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 230000005669 field effect Effects 0.000 title claims abstract description 27
- 238000000034 method Methods 0.000 title claims description 20
- 239000002887 superconductor Substances 0.000 title abstract description 3
- 239000004065 semiconductor Substances 0.000 claims abstract description 66
- 239000000758 substrate Substances 0.000 claims abstract description 42
- 230000003746 surface roughness Effects 0.000 claims abstract description 26
- 230000000694 effects Effects 0.000 claims abstract description 23
- 239000000463 material Substances 0.000 claims description 50
- 238000004519 manufacturing process Methods 0.000 claims description 17
- 239000000969 carrier Substances 0.000 claims description 11
- 230000010287 polarization Effects 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052782 aluminium Inorganic materials 0.000 claims description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 7
- 239000010955 niobium Substances 0.000 claims description 7
- 230000008569 process Effects 0.000 claims description 7
- 229910001275 Niobium-titanium Inorganic materials 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 229910052758 niobium Inorganic materials 0.000 claims description 6
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 claims description 6
- RJSRQTFBFAJJIL-UHFFFAOYSA-N niobium titanium Chemical compound [Ti].[Nb] RJSRQTFBFAJJIL-UHFFFAOYSA-N 0.000 claims description 6
- PZKRHHZKOQZHIO-UHFFFAOYSA-N [B].[B].[Mg] Chemical compound [B].[B].[Mg] PZKRHHZKOQZHIO-UHFFFAOYSA-N 0.000 claims description 5
- 239000011521 glass Substances 0.000 claims description 5
- KJSMVPYGGLPWOE-UHFFFAOYSA-N niobium tin Chemical compound [Nb].[Sn] KJSMVPYGGLPWOE-UHFFFAOYSA-N 0.000 claims description 5
- 229920000642 polymer Polymers 0.000 claims description 5
- 239000010453 quartz Substances 0.000 claims description 5
- 238000009825 accumulation Methods 0.000 claims description 4
- 239000004020 conductor Substances 0.000 claims description 4
- DGAHKUBUPHJKDE-UHFFFAOYSA-N indium lead Chemical compound [In].[Pb] DGAHKUBUPHJKDE-UHFFFAOYSA-N 0.000 claims description 4
- 230000003247 decreasing effect Effects 0.000 claims description 3
- 229910001092 metal group alloy Inorganic materials 0.000 claims description 2
- 229910052738 indium Inorganic materials 0.000 claims 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims 1
- 239000007769 metal material Substances 0.000 claims 1
- 235000012239 silicon dioxide Nutrition 0.000 description 5
- 230000009471 action Effects 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 229910000657 niobium-tin Inorganic materials 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 238000004873 anchoring Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000012552 review Methods 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 230000000779 depleting effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 230000005686 electrostatic field Effects 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000004445 quantitative analysis Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N60/00—Superconducting devices
- H10N60/20—Permanent superconducting devices
- H10N60/205—Permanent superconducting devices having three or more electrodes, e.g. transistor-like structures
- H10N60/207—Field effect devices
Definitions
- the present invention relates to a superconductive field effect transistor of the type comprising a source electrode and a drain electrode, connected by a superconducting channel, the channel and the source and drain electrodes being disposed on a substrate, and a grid covering the canal.
- the invention also relates to a method for manufacturing a field-effect superconductive transistor, said transistor comprising a source electrode and a drain electrode, connected by a superconducting channel, the channel and the source and drain electrodes being disposed on a substrate, and a gate electrode covering the channel.
- EP 0 505 259 discloses a superconductive field effect transistor comprising a substrate and a multilayer structure defining a channel and disposed on the substrate.
- the transistor comprises a source electrode and a drain electrode connected by the channel.
- the channel is controlled by a gate electrode, between a blocked state in which current does not flow substantially between the source electrode and the drain electrode, and a conducting state in which current flows from the source electrode. to the drain electrode.
- the amount of current flowing in the channel in the on state depends in particular on the polarization of the gate electrode.
- the multilayer structure comprises at least one pair of layers formed of a superconducting layer and a non-superconducting layer.
- the field effect produced by polarization of the gate electrode directly affects the carrier rate in the superconducting channel.
- the maximum current density of the channel is therefore strongly limited.
- the superconducting field effect transistor of the state of the art thus makes it possible to control only small currents.
- the invention therefore aims to enable the control of high currents, and to increase the current gain between the source electrode and the drain electrode, when the transistor is conducting.
- the subject of the invention is a transistor of the aforementioned type, characterized in that a layer of semiconductor material is disposed between the channel and the gate electrode, so as to allow control of the critical current of the superconducting channel by controlling the surface roughness of said channel, said surface roughness being controlled by combining the proximity effect between the superconducting channel and the layer of semiconductor material, and the field effect in the layer of semiconductor material by biasing the gate electrode, said critical current being controlled between a minimum value Icjnin by decreasing the surface roughness under the effect of an accumulation of free carriers of the semiconductor at the interface between the semiconductor layer and the channel for a first bias voltage of the gate electrode, and a maximum value Icjnax by increasing the surface roughness under the effect of free carrier depletion of the semiconductor at the interface between the semiconductor layer and the channel for a second bias voltage of the gate electrode.
- the transistor comprises one or more of the following characteristics, taken individually or according to all the technically possible combinations:
- the gate electrode is galvanically isolated from the channel by an insulating layer disposed on the layer of semiconductor material, and the transistor is a MOSFET transistor; the transistor is a JFET transistor;
- the substrate is a semiconductor substrate
- the substrate is an amorphous substrate of the glass or quartz type
- the substrate is a metal substrate
- the substrate is a flexible substrate of the polymer type;
- the superconducting channel is made of one of the group consisting of: niobium, aluminum, indium lead, niobium titanium, niobium tin and magnesium diboride;
- the critical current is determined by the width of the superconducting channel, and the maximum value Icjnax is greater than or equal to 50 A / cm,
- the critical current is determined by the width of the superconducting channel, and the minimum value Icjnin is between 0 A / cm and 0.5A / cm, the thickness of the superconducting channel is between 3 nm and 1 cm,
- the source and drain electrodes are of superconductive material
- the channel is a channel in fins.
- the invention also relates to a manufacturing method of the aforementioned type, characterized in that it comprises the addition of a layer of semiconductor material between the channel and the gate electrode, so as to allow a control the critical current of the superconducting channel by controlling the surface roughness of said channel, said surface roughness being controlled by combining the proximity effect between the superconducting channel and the semiconductor material layer and the field effect in the semiconductor material layer by polarization of the gate electrode, between a minimum value Icynin by reducing the surface roughness under the effect of an accumulation of free carriers of the semiconductor at the interface between the layer; semiconductor and the channel, and a maximum value Icjnax by increasing the surface roughness under the effect of a depletion of semiconductor free carriers at the interface between the semiconductor layer and channel.
- the manufacturing method comprises one or more of the following characteristics, taken separately or in any technically possible combination:
- the method comprises the addition of an insulating layer between the gate electrode and the layer of semiconductor material,
- the thickness of the superconducting channel is between 3 nm and 1 cm
- the method comprises producing the substrate made of a semiconductor material
- the process comprises producing the substrate in an amorphous material of the glass or quartz type
- the method comprises making the substrate of a metal or a metal alloy, the method comprises producing the substrate in a flexible material of the polymer type,
- the method comprises selecting the material of the superconducting channel from the group consisting of: niobium, aluminum, indium lead, niobium titanium, niobium tin and magnesium diboride,
- the method comprises forming the canal in the form of a channel in fins.
- FIG. 1 is a schematic representation of the superconducting field effect transistor according to a first embodiment of the invention
- FIG. 2 is an operating flow diagram of the manufacturing method according to the first embodiment of the invention.
- FIG. 3 is a schematic representation of the superconducting field effect transistor according to a second embodiment of the invention.
- FIG. 4 is an operating flow diagram of the manufacturing method according to the second embodiment of the invention.
- a field effect superconducting transistor 2 comprises a source electrode 4, a drain electrode 6 and a gate electrode 8.
- the gate electrode 8 is electrically isolated from the remainder of the transistor by a gate insulator layer 10.
- the source 4 and drain 6 electrodes are connected by a superconducting channel 12.
- the transistor 2 is of the Metal-Oxide Semiconductor Field-Effect Transistor (MOSFET) type or metal-oxide gate field effect transistor.
- MOSFET Metal-Oxide Semiconductor Field-Effect Transistor
- a layer of semiconductor material 14 is disposed between the channel 12 and the insulating layer 10 of the gate electrode.
- the source electrode 4, the drain electrode 6 and the superconducting channel 12 are arranged on a substrate 16.
- the source 4, drain 6 and gate 8 electrodes are metallic.
- the gate electrode 8 is, for example, aluminum or tungsten.
- the source 4 and drain 6 electrodes are, for example, aluminum or tungsten.
- the insulating layer 10 is made of thermal oxide, for example silicon dioxide (SIO 2 ).
- the superconducting channel 12 extends between the source electrode 4 and the drain electrode 6 in a longitudinal direction.
- the channel 12 has a width L in a transverse direction, perpendicular to the longitudinal direction.
- the width L of the channel 12 is between 10 nanometers and 0.1 micrometer, preferably equal to 100 nanometers.
- the channel 12 is of thickness E, visible in FIG. 1, between 3 nanometers and one centimeter, preferably equal to 0.1 micrometer.
- the superconducting material of channel 12 is a type II superconducting material, such as niobium (Nb).
- the surface of the channel 12 in contact with the layer of semiconductor material 14 is called the upper surface of the superconducting channel 12, and the surface in contact with the substrate 16 is called the inner surface of the superconducting channel 12.
- the layer 14 of semiconductor material is adapted to allow a control of the critical current Ic of the superconducting channel 12 between a minimum value lc_min and a maximum value Icjnax by controlling the surface roughness of the channel 12.
- the surface roughness is controlled by combination of the effect of proximity between the superconducting channel 12 and the layer 14 of semiconductor material, and the field effect in the layer 14 of semiconductor material by polarization of the gate electrode 8.
- the critical current Ic is determined by the width L of the superconducting channel 12.
- the maximum value Icjnax of the critical current is greater than or equal to 50 amperes per centimeter.
- the minimum value Icjnin is between 0 Ampere per centimeter and 0.5 Ampere per centimeter, preferably equal to 0.1 ampere per centimeter.
- the substrate 16 made of a semiconductor material, such as solid silicon.
- a semiconductor material such as solid silicon.
- the manufacturing process begins in step 100 by producing the semiconductor substrate 16.
- the process continues in step 110 by forming the source 4 and drain 6 metal electrodes on the semiconductor substrate 16.
- the superconducting channel 12 is then produced in step 120 by depositing niobium between the source 4 and drain 6 electrodes, along the width L, until the thickness E is obtained.
- the process comprises, in step 130, the addition of the layer 14 of semiconductor material on the superconducting channel 12, so as to allow a control of the critical current Ic of the superconducting channel 12 by controlling the surface roughness of the channel 12 .
- the manufacturing process is continued in step 140 by the formation of the insulating layer 10 on the layer of semiconductor material 14.
- step 150 ends in step 150 by forming the tungsten gate electrode 8 on the insulating layer 10 of silicon dioxide.
- the operating principle of the superconducting transistor 2 lies in the control of the electrical resistance of the channel 12 under the action of the polarization of the gate electrode 8.
- the value of the electrical resistance of the channel 12 is substantially zero if the superconducting channel 12 is in a non-dissipative superconductive state, or a conducting state. If, on the contrary, the superconducting channel 12 is in a dissipative state, or a blocked state, then the electrical resistance of the channel is non-zero. This results in a switching behavior of the transistor 2 between the superconductive or non-dissipative state, and the dissipative state. This switching behavior does not exclude a linear mode in which the channel resistance varies in proportion under the biasing action of the gate electrode 8.
- the conduction of the channel 12 is controlled by the bias voltage V G s applied between the gate electrode 8 and the source electrode 4.
- the bias voltage V G applied between the gate electrode 8 and the source electrode 4 is called the bias voltage Vg of the gate electrode 8.
- the free carriers of the semiconductor material of the layer 14 accumulate at the interface between the layer of semiconductor material 14 and the channel 12 superconducting, which has the effect of reducing the surface roughness by proximity effect.
- the minimum value Icjnin of the critical current Ic is obtained for a minimum roughness of the upper surface of the superconducting channel 12.
- the free carriers of the semiconductor material of the layer 14 are depleted at the interface between the layer of semiconductor material 14 and the superconducting channel 12, which has the effect of increasing the surface roughness by proximity effect.
- the maximum value Icjnax of the critical current Ic is obtained for a maximum roughness e of the surface of the superconducting circuit.
- the surface roughness of the superconducting channel 12 contributes to vortex anchoring by providing sites for connecting non-normal vortices to the average surface.
- the vortex being anchored they do not disturb the superconducting regime of the channel 12, which still acts substantially as a perfect conductor, which corresponds to a strong critical current.
- the displacement of the vortex network is not constrained when the surface of the channel 12 is slightly rough, or even smooth.
- the movement of the vortex network then creates an electromotive force, since each vortex carries a magnetic flux, and the superconducting channel 12 no longer acts as a perfect conductor, which corresponds to a low critical current.
- a sample of high roughness has a high critical current
- a sample of low roughness has a low critical current.
- the critical current is substantially zero for a substantially smooth surface.
- the superconducting transistor 2 makes it possible to control the anchoring or the decanting of the vortices, and thus to control the threshold value for the appearance of a non-electrical resistance. null of the superconducting channel 12.
- the so-called proximity effect characterizes the fact that a layer of highly doped semiconductor material deposited on a superconducting layer itself becomes superconductive on a film whose thickness is related to the mobility and to the concentration of free carriers.
- the bias voltage Vg of the gate electrode 8 leads to increasing the concentration of free carriers in the vicinity of the interface between the superconducting channel 12 and the semiconductor layer 14, then the roughness is smoothed and decreases, and the critical current Ic decreases to the minimum value Icjnin. When the value of the critical current Ic is close to the minimum value Icjnin, the superconducting transistor 2 is in the off state. If, on the other hand, the bias voltage Vg of the gate electrode 8 leads to depleting the interface between the superconducting channel 12 and the semiconductor layer 14, then the surface roughness increases, implying an increase in the critical current Ic up to at its maximum value Icjnax. When the value of the critical current Ic is close to the maximum value lc_max, the superconducting transistor 2 is in the on state.
- the interface between the semiconductor layer 14 and the superconducting channel 12 thus behaves as a surface with variable roughness as a function of the bias voltage Vg of the gate electrode 8.
- the transistor 2 When the superconducting transistor 2 is conducting, the current flows from the source electrode 4 to the drain electrode 6 in both the superconducting channel 12 and in the thickness of the semiconductor material layer 14 where the carriers are located. free. This thickness of layer 14 of semiconductor material is then superconducting by proximity effect.
- the transistor 2 according to the invention thus allows the direct control, by electrostatic field effect, of the critical current Ic of the superconducting channel 12.
- the superconducting transistor 2 according to the invention is capable of being used for applications in the field of high currents, such as power switching and current limiting.
- the dissipative state of the superconducting channel 12 does not result from a reduction of the carrier rate, but from the decrease of the critical current Ic by vortex decanting.
- the superconducting transistor 2 makes it possible to control a current of intensity greater than or equal to 50 amperes for each centimeter of the width L of the superconducting channel 12.
- the current gain of the transistor 2 is important.
- the superconducting transistor 2 according to the invention is capable of being used for applications in the field of low currents.
- the frequency response of the superconducting transistor 2 according to the invention is high, since the transition between the dissipative state of the channel 12 and the superconductive or non-dissipative state is due to the dynamics of the vortices.
- the manufacturing method according to the invention of the superconducting transistor 2 does not require a heavy technological means making it possible to deposit or etch at the nanoscale.
- the manufacturing method according to the invention does not require a superconducting channel of very small thickness.
- the layer undergoing the field effect due to the polarization of the gate electrode 8 is not the superconducting channel 12 itself, but only the semiconductor layer 14 deposited on the channel 12.
- FIG. 3 and 4 illustrate a second embodiment of the invention, for which the elements similar to the embodiment described above are identified by identical references.
- the superconducting field effect transistor 2 does not comprise an insulating layer between the gate electrode 8 and the layer of semiconductor material 14, as represented in FIG.
- the transistor 2 is of JFET (Junction Field Effect Transistor) type or junction field effect transistor, for which the gate electrode 8 is directly in contact with the channel 12.
- the method of manufacturing transistor 2 according to the second embodiment does not include a step of forming an insulating layer on the layer of semiconductor material 14.
- Step 155 the last step of the manufacturing process, consists of the formation of the gate electrode 8, directly on the layer of semiconductor material 14.
- the operation of this second embodiment is identical to that of the first embodiment. and is therefore not described again.
- the substrate 16 is an amorphous substrate, of the glass or quartz type.
- the substrate 16 is a metal substrate.
- the substrate 16 is a flexible substrate, of polymer type.
- the source 4 and drain 6 electrodes are made of a superconducting material.
- the source 4 and drain 6 electrodes are made of a doped semiconductor material.
- the superconducting channel 12 is a finned channel.
- the superconducting material of the channel 12 is aluminum (Al), indium lead (PbIn), niobium titanium (NbTi), niobium tin (NbSn), or magnesium diboride ( MgB 2 ).
- the superconducting transistor according to the invention makes it possible to control the passage of currents of high intensity through its superconducting channel, since the density of the free carriers in the superconducting channel is not affected by the field effect which acts only on the layer of semiconductor material. It is also conceivable that the superconductive transistor according to the invention makes it possible to amplify the current in the channel with a large gain, due to the large variation in the resistance of the channel under the field effect, due to the polarization of the electrode grid.
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- Superconductor Devices And Manufacturing Methods Thereof (AREA)
Abstract
Description
Transistor supraconducteur à effet de champ et procédé de fabrication d'un tel transistor Superconducting field effect transistor and method of manufacturing such a transistor
La présente invention concerne un transistor supraconducteur à effet de champ du type comprenant une électrode de source et une électrode de drain, reliées par un canal supraconducteur, le canal et les électrodes de source et de drain étant disposés sur un substrat, et une électrode de grille recouvrant le canal.The present invention relates to a superconductive field effect transistor of the type comprising a source electrode and a drain electrode, connected by a superconducting channel, the channel and the source and drain electrodes being disposed on a substrate, and a grid covering the canal.
L'invention concerne également un procédé de fabrication d'un transistor supraconducteur à effet de champ, ledit transistor comprenant une électrode de source et une électrode de drain, reliées par un canal supraconducteur, le canal et les électrodes de source et de drain étant disposés sur un substrat, et une électrode de grille recouvrant le canal.The invention also relates to a method for manufacturing a field-effect superconductive transistor, said transistor comprising a source electrode and a drain electrode, connected by a superconducting channel, the channel and the source and drain electrodes being disposed on a substrate, and a gate electrode covering the channel.
L'invention s'applique à tout composant électronique comportant au moins un transistor, notamment aux composants électroniques de puissance, tels que des limiteurs de courant ou des commutateurs à fort courant. Le brevet EP 0 505 259 décrit un transistor supraconducteur à effet de champ comprenant un substrat et une structure multicouches définissant un canal et disposée sur le substrat. Le transistor comprend une électrode de source et une électrode de drain reliées par le canal. Le canal est commandé par une électrode de grille, entre un état bloqué dans lequel le courant ne circule sensiblement pas entre l'électrode de source et l'électrode de drain, et un état passant dans lequel le courant circule de l'électrode de source vers l'électrode de drain. La quantité de courant circulant dans le canal à l'état passant dépend notamment de la polarisation de l'électrode de grille. Lorsque le canal est bloqué, le transistor est dit bloqué, et lorsque le canal est passant, le transistor est dit passant. La structure multicouches comprend au moins une paire de couches formée d'une couche supraconductrice et d'une couche non supraconductrice.The invention applies to any electronic component comprising at least one transistor, particularly to electronic power components, such as current limiters or high current switches. EP 0 505 259 discloses a superconductive field effect transistor comprising a substrate and a multilayer structure defining a channel and disposed on the substrate. The transistor comprises a source electrode and a drain electrode connected by the channel. The channel is controlled by a gate electrode, between a blocked state in which current does not flow substantially between the source electrode and the drain electrode, and a conducting state in which current flows from the source electrode. to the drain electrode. The amount of current flowing in the channel in the on state depends in particular on the polarization of the gate electrode. When the channel is blocked, the transistor is said to be off, and when the channel is on, the transistor is said to be on. The multilayer structure comprises at least one pair of layers formed of a superconducting layer and a non-superconducting layer.
Toutefois, l'effet de champ produit par polarisation de l'électrode de grille affecte directement le taux de porteurs dans le canal supraconducteur. La densité de courant maximal du canal est de ce fait fortement limitée. Le transistor supraconducteur à effet de champ de l'état de la technique permet donc de commander uniquement de faibles courants.However, the field effect produced by polarization of the gate electrode directly affects the carrier rate in the superconducting channel. The maximum current density of the channel is therefore strongly limited. The superconducting field effect transistor of the state of the art thus makes it possible to control only small currents.
En outre, le gain en courant du transistor de l'état de la technique est fréquemment faible. L'invention a donc pour but de permettre la commande de forts courants, et d'augmenter le gain en courant entre l'électrode de source et l'électrode de drain, lorsque le transistor est passant.In addition, the current gain of the transistor of the state of the art is frequently low. The invention therefore aims to enable the control of high currents, and to increase the current gain between the source electrode and the drain electrode, when the transistor is conducting.
A cet effet, l'invention a pour objet un transistor du type précité, caractérisé en ce qu'une couche de matériau semi-conducteur est disposée entre le canal et l'électrode de grille, de manière à permettre un contrôle du courant critique du canal supraconducteur par contrôle de la rugosité de surface dudit canal, ladite rugosité de surface étant contrôlée par combinaison de l'effet de proximité entre le canal supraconducteur et la couche de matériau semi-conducteur, et de l'effet de champ dans la couche de matériau semi-conducteur par polarisation de l'électrode de grille, ledit courant critique étant contrôlé entre une valeur minimale Icjnin par diminution de la rugosité de surface sous l'effet d'une accumulation de porteurs libres du semi-conducteur à l'interface entre la couche de semi-conducteur et le canal pour une première tension de polarisation de l'électrode de grille, et une valeur maximale Icjnax par augmentation de la rugosité de surface sous l'effet d'une déplétion de porteurs libres du semi-conducteur à l'interface entre la couche de semi-conducteur et le canal pour une deuxième tension de polarisation de l'électrode de grille.For this purpose, the subject of the invention is a transistor of the aforementioned type, characterized in that a layer of semiconductor material is disposed between the channel and the gate electrode, so as to allow control of the critical current of the superconducting channel by controlling the surface roughness of said channel, said surface roughness being controlled by combining the proximity effect between the superconducting channel and the layer of semiconductor material, and the field effect in the layer of semiconductor material by biasing the gate electrode, said critical current being controlled between a minimum value Icjnin by decreasing the surface roughness under the effect of an accumulation of free carriers of the semiconductor at the interface between the semiconductor layer and the channel for a first bias voltage of the gate electrode, and a maximum value Icjnax by increasing the surface roughness under the effect of free carrier depletion of the semiconductor at the interface between the semiconductor layer and the channel for a second bias voltage of the gate electrode.
Suivant d'autres modes de réalisation, le transistor comprend une ou plusieurs des caractéristiques suivantes, prises isolément ou suivant toutes les combinaisons techniquement possibles :According to other embodiments, the transistor comprises one or more of the following characteristics, taken individually or according to all the technically possible combinations:
- l'électrode de grille est isolée galvaniquement du canal par une couche isolante disposée sur la couche de matériau semi-conducteur, et le transistor est un transistor MOSFET, - le transistor est un transistor JFET,the gate electrode is galvanically isolated from the channel by an insulating layer disposed on the layer of semiconductor material, and the transistor is a MOSFET transistor; the transistor is a JFET transistor;
- le substrat est un substrat semi-conducteur,the substrate is a semiconductor substrate,
- le substrat est un substrat amorphe du type verre ou quartz,the substrate is an amorphous substrate of the glass or quartz type,
- le substrat est un substrat métallique,the substrate is a metal substrate,
- le substrat est un substrat souple du type polymère, - le canal supraconducteur est en un matériau parmi le groupe constitué de : le niobium, l'aluminium, le plomb indium, le niobium titane, le niobium étain et le diboride de magnésium, - le courant critique est déterminé par la largeur du canal supraconducteur, et la valeur maximale Icjnax est supérieure ou égale à 50 A/cm,the substrate is a flexible substrate of the polymer type; the superconducting channel is made of one of the group consisting of: niobium, aluminum, indium lead, niobium titanium, niobium tin and magnesium diboride; the critical current is determined by the width of the superconducting channel, and the maximum value Icjnax is greater than or equal to 50 A / cm,
- le courant critique est déterminé par la largeur du canal supraconducteur, et la valeur minimale Icjnin est comprise entre 0 A/cm et 0,5A/cm, - l'épaisseur du canal supraconducteur est comprise entre 3 nm et 1 cm,the critical current is determined by the width of the superconducting channel, and the minimum value Icjnin is between 0 A / cm and 0.5A / cm, the thickness of the superconducting channel is between 3 nm and 1 cm,
- les électrodes de source et de drain sont en matériau supraconducteur,the source and drain electrodes are of superconductive material,
- le canal est un canal en ailettes.the channel is a channel in fins.
L'invention a également pour objet un procédé de fabrication du type précité, caractérisé en ce qu'il comprend l'adjonction d'une couche de matériau semi-conducteur entre le canal et l'électrode de grille, de manière à permettre un contrôle du courant critique du canal supraconducteur par contrôle de la rugosité de surface dudit canal, ladite rugosité de surface étant contrôlée par combinaison de l'effet de proximité entre le canal supraconducteur et la couche de matériau semi-conducteur et de l'effet de champ dans la couche de matériau semi- conducteur par polarisation de l'électrode de grille, entre une valeur minimale Icjnin par diminution de la rugosité de surface sous l'effet d'une accumulation de porteurs libres du semi-conducteur à l'interface entre la couche de semiconducteur et le canal, et une valeur maximale Icjnax par accroissement de la rugosité de surface sous l'effet d'une déplétion de porteurs libres du semi- conducteur à l'interface entre la couche de semi-conducteur et le canal.The invention also relates to a manufacturing method of the aforementioned type, characterized in that it comprises the addition of a layer of semiconductor material between the channel and the gate electrode, so as to allow a control the critical current of the superconducting channel by controlling the surface roughness of said channel, said surface roughness being controlled by combining the proximity effect between the superconducting channel and the semiconductor material layer and the field effect in the semiconductor material layer by polarization of the gate electrode, between a minimum value Icynin by reducing the surface roughness under the effect of an accumulation of free carriers of the semiconductor at the interface between the layer; semiconductor and the channel, and a maximum value Icjnax by increasing the surface roughness under the effect of a depletion of semiconductor free carriers at the interface between the semiconductor layer and channel.
Suivant d'autres modes de réalisation, le procédé de fabrication comprend une ou plusieurs des caractéristiques suivantes, prises isolément ou suivant toutes les combinaisons techniquement possibles :According to other embodiments, the manufacturing method comprises one or more of the following characteristics, taken separately or in any technically possible combination:
- le procédé comprend l'adjonction d'une couche isolante entre l'électrode de grille et la couche de matériau semi-conducteur,the method comprises the addition of an insulating layer between the gate electrode and the layer of semiconductor material,
- l'épaisseur du canal supraconducteur est comprise entre 3 nm et 1 cm,the thickness of the superconducting channel is between 3 nm and 1 cm,
- le procédé comprend la réalisation du substrat en un matériau semiconducteur,the method comprises producing the substrate made of a semiconductor material,
- le procédé comprend la réalisation du substrat en un matériau amorphe du type verre ou quartz,the process comprises producing the substrate in an amorphous material of the glass or quartz type,
- le procédé comprend la réalisation du substrat en un métal ou un alliage métallique, - le procédé comprend la réalisation du substrat en un matériau souple du type polymère,the method comprises making the substrate of a metal or a metal alloy, the method comprises producing the substrate in a flexible material of the polymer type,
- le procédé comprend la sélection du matériau du canal supraconducteur parmi le groupe constitué de : le niobium, l'aluminium, le plomb indium, le niobium titane, le niobium étain et le diboride de magnésium,the method comprises selecting the material of the superconducting channel from the group consisting of: niobium, aluminum, indium lead, niobium titanium, niobium tin and magnesium diboride,
- le procédé comprend la réalisation du canal en forme d'un canal en ailettes.the method comprises forming the canal in the form of a channel in fins.
L'invention et ses avantages seront mieux compris à la lecture de la description qui va suivre, donnée uniquement à titre d'exemple, et faite en référence aux dessins annexés, sur lesquels :The invention and its advantages will be better understood on reading the description which follows, given solely by way of example, and with reference to the appended drawings, in which:
- la figure 1 est une représentation schématique du transistor supraconducteur à effet de champ selon un premier mode de réalisation de l'invention,FIG. 1 is a schematic representation of the superconducting field effect transistor according to a first embodiment of the invention,
- la figure 2 est un organigramme de fonctionnement du procédé de fabrication selon le premier mode de réalisation de l'invention,FIG. 2 is an operating flow diagram of the manufacturing method according to the first embodiment of the invention,
- la figure 3 est une représentation schématique du transistor supraconducteur à effet de champ selon un deuxième mode de réalisation de l'invention, etFIG. 3 is a schematic representation of the superconducting field effect transistor according to a second embodiment of the invention, and
- la figure 4 est un organigramme de fonctionnement du procédé de fabrication selon le deuxième mode de réalisation de l'invention.- Figure 4 is an operating flow diagram of the manufacturing method according to the second embodiment of the invention.
Sur la figure 1 , un transistor 2 supraconducteur à effet de champ comprend une électrode de source 4, une électrode de drain 6 et une électrode de grille 8.In FIG. 1, a field effect superconducting transistor 2 comprises a source electrode 4, a drain electrode 6 and a gate electrode 8.
L'électrode de grille 8 est isolée électriquement du reste du transistor par une couche d'isolant 10 de grille. Les électrodes de source 4 et de drain 6 sont reliées par un canal 12 supraconducteur.The gate electrode 8 is electrically isolated from the remainder of the transistor by a gate insulator layer 10. The source 4 and drain 6 electrodes are connected by a superconducting channel 12.
Dans le mode de réalisation décrit, le transistor 2 est de type MOSFET (de l'anglais Metal-Oxide Semiconductor Field-Effect Transistor) ou transistor à effet de champ à grille métal-oxyde.In the embodiment described, the transistor 2 is of the Metal-Oxide Semiconductor Field-Effect Transistor (MOSFET) type or metal-oxide gate field effect transistor.
Une couche de matériau semi-conducteur 14 est disposée entre le canal 12 et la couche isolante 10 de l'électrode de grille. L'électrode de source 4, l'électrode de drain 6 et le canal 12 supraconducteur sont disposés sur un substrat 16.A layer of semiconductor material 14 is disposed between the channel 12 and the insulating layer 10 of the gate electrode. The source electrode 4, the drain electrode 6 and the superconducting channel 12 are arranged on a substrate 16.
Les rapports des dimensions représentées sur la figure 1 ont été volontairement modifiés pour la clarté des dessins. Dans le mode de réalisation décrit, les électrodes de source 4, de drain 6 et de grille 8 sont métalliques. L'électrode de grille 8 est, par exemple en aluminium ou tungstène. Les électrodes de source 4 et de drain 6 sont, par exemple, en aluminium ou tungstène. La couche isolante 10 est réalisée en oxyde thermique, par exemple en dioxyde de silicium (SIO2).The ratios of the dimensions shown in FIG. 1 have been voluntarily modified for the clarity of the drawings. In the embodiment described, the source 4, drain 6 and gate 8 electrodes are metallic. The gate electrode 8 is, for example, aluminum or tungsten. The source 4 and drain 6 electrodes are, for example, aluminum or tungsten. The insulating layer 10 is made of thermal oxide, for example silicon dioxide (SIO 2 ).
Le canal 12 supraconducteur s'étend entre l'électrode de source 4 et l'électrode de drain 6 selon une direction longitudinale. Le canal 12 présente une largeur L selon une direction transversale, perpendiculaire à la direction longitudinale. La largeur L du canal 12 est comprise entre 10 nanomètres et 0,1 micromètre, de préférence égale à 100 nanomètres. Le canal 12 est d'épaisseur E, visible sur la figure 1 , comprise entre 3 nanomètres et un centimètre, de préférence égale à 0,1 micromètre.The superconducting channel 12 extends between the source electrode 4 and the drain electrode 6 in a longitudinal direction. The channel 12 has a width L in a transverse direction, perpendicular to the longitudinal direction. The width L of the channel 12 is between 10 nanometers and 0.1 micrometer, preferably equal to 100 nanometers. The channel 12 is of thickness E, visible in FIG. 1, between 3 nanometers and one centimeter, preferably equal to 0.1 micrometer.
Le matériau supraconducteur du canal 12 est un matériau supraconducteur de type II, tel que le niobium (Nb). La surface du canal 12 au contact de la couche de matériau semiconducteur 14 est appelée surface supérieure du canal 12 supraconducteur, et la surface au contact du substrat 16 est appelée surface intérieure du canal 12 supraconducteur.The superconducting material of channel 12 is a type II superconducting material, such as niobium (Nb). The surface of the channel 12 in contact with the layer of semiconductor material 14 is called the upper surface of the superconducting channel 12, and the surface in contact with the substrate 16 is called the inner surface of the superconducting channel 12.
La couche 14 de matériau semi-conducteur est propre à permettre un contrôle du courant critique Ic du canal 12 supraconducteur entre une valeur minimale lc_min et une valeur maximale Icjnax par contrôle de la rugosité de surface du canal 12. La rugosité de surface est contrôlée par combinaison de l'effet de proximité entre le canal 12 supraconducteur et la couche 14 de matériau semi-conducteur, et de l'effet de champ dans la couche 14 de matériau semi- conducteur par polarisation de l'électrode de grille 8.The layer 14 of semiconductor material is adapted to allow a control of the critical current Ic of the superconducting channel 12 between a minimum value lc_min and a maximum value Icjnax by controlling the surface roughness of the channel 12. The surface roughness is controlled by combination of the effect of proximity between the superconducting channel 12 and the layer 14 of semiconductor material, and the field effect in the layer 14 of semiconductor material by polarization of the gate electrode 8.
Le courant critique Ic est déterminé par la largeur L du canal 12 supraconducteur. La valeur maximale Icjnax du courant critique est supérieure ou égale à 50 ampères par centimètre.The critical current Ic is determined by the width L of the superconducting channel 12. The maximum value Icjnax of the critical current is greater than or equal to 50 amperes per centimeter.
La valeur minimale Icjnin est comprise entre 0 Ampère par centimètre et 0,5 ampère par centimètre, de préférence égale à 0,1 ampère par centimètre.The minimum value Icjnin is between 0 Ampere per centimeter and 0.5 Ampere per centimeter, preferably equal to 0.1 ampere per centimeter.
Dans le mode de réalisation décrit, le substrat 16 réalisé en un matériau semi-conducteur, tel que du silicium massif. Le procédé de fabrication du transistor supraconducteur 2 va maintenant être décrit à l'aide de la figure 2.In the embodiment described, the substrate 16 made of a semiconductor material, such as solid silicon. The method of manufacturing the superconducting transistor 2 will now be described with reference to FIG.
Le procédé de fabrication débute à l'étape 100 par la réalisation du substrat 16 semi-conducteur. Le procédé se poursuit à l'étape 110 par la formation des électrodes métalliques de source 4 et de drain 6 sur le substrat 16 semi-conducteur.The manufacturing process begins in step 100 by producing the semiconductor substrate 16. The process continues in step 110 by forming the source 4 and drain 6 metal electrodes on the semiconductor substrate 16.
Le canal 12 supraconducteur est ensuite réalisé à l'étape 120 par dépôt de niobium entre les électrodes de source 4 et de drain 6, sur la largeur L, jusqu'à obtenir l'épaisseur E. Après réalisation du canal 12 supraconducteur, le procédé comprend, à l'étape 130, l'adjonction de la couche 14 de matériau semi-conducteur sur le canal 12 supraconducteur, de manière à permettre un contrôle du courant critique Ic du canal 12 supraconducteur par contrôle de la rugosité de surface du canal 12.The superconducting channel 12 is then produced in step 120 by depositing niobium between the source 4 and drain 6 electrodes, along the width L, until the thickness E is obtained. After the superconducting channel 12 has been formed, the process comprises, in step 130, the addition of the layer 14 of semiconductor material on the superconducting channel 12, so as to allow a control of the critical current Ic of the superconducting channel 12 by controlling the surface roughness of the channel 12 .
Dans le mode de réalisation décrit, le procédé de fabrication se poursuit à l'étape 140 par la formation de la couche isolante 10 sur la couche de matériau semi-conducteur 14.In the embodiment described, the manufacturing process is continued in step 140 by the formation of the insulating layer 10 on the layer of semiconductor material 14.
Le procédé de fabrication se termine à l'étape 150 par la formation de l'électrode de grille 8 en tungstène sur la couche isolante 10 en dioxyde de silicium. Le principe de fonctionnement du transistor supraconducteur 2 réside dans le contrôle de la résistance électrique du canal 12 sous l'action de la polarisation de l'électrode de grille 8.The manufacturing process ends in step 150 by forming the tungsten gate electrode 8 on the insulating layer 10 of silicon dioxide. The operating principle of the superconducting transistor 2 lies in the control of the electrical resistance of the channel 12 under the action of the polarization of the gate electrode 8.
La valeur de la résistance électrique du canal 12 est sensiblement nulle si le canal 12 supraconducteur est dans un état non dissipatif supraconducteur, ou état passant. Si au contraire, le canal 12 supraconducteur se trouve dans un état dissipatif, ou état bloqué, alors la résistance électrique du canal est non nulle. Il en résulte un comportement de commutation du transistor 2 entre l'état supraconducteur ou non dissipatif, et l'état dissipatif. Ce comportement de commutation n'exclut pas un mode linéaire dans lequel la résistance de canal varie en proportion sous l'action de polarisation de l'électrode de grille 8.The value of the electrical resistance of the channel 12 is substantially zero if the superconducting channel 12 is in a non-dissipative superconductive state, or a conducting state. If, on the contrary, the superconducting channel 12 is in a dissipative state, or a blocked state, then the electrical resistance of the channel is non-zero. This results in a switching behavior of the transistor 2 between the superconductive or non-dissipative state, and the dissipative state. This switching behavior does not exclude a linear mode in which the channel resistance varies in proportion under the biasing action of the gate electrode 8.
La conduction du canal 12 est commandée par la tension de polarisation VGs appliquée entre l'électrode de grille 8 et l'électrode de source 4. Par souci de simplification, la tension de polarisation VGs appliquée entre l'électrode de grille 8 et l'électrode de source 4 est appelée tension de polarisation Vg de l'électrode de grille 8.The conduction of the channel 12 is controlled by the bias voltage V G s applied between the gate electrode 8 and the source electrode 4. For the sake of simplification, the bias voltage V G applied between the gate electrode 8 and the source electrode 4 is called the bias voltage Vg of the gate electrode 8.
Pour une première valeur de la tension de polarisation Vg de l'électrode de grille 8, les porteurs libres du matériau semi-conducteur de la couche 14 s'accumulent à l'interface entre la couche de matériau semi-conducteur 14 et le canal 12 supraconducteur, ce qui a pour effet de diminuer la rugosité de surface par effet de proximité. La valeur minimale Icjnin du courant critique Ic est obtenue pour une rugosité minimale de la surface supérieure du canal 12 supraconducteur.For a first value of the bias voltage Vg of the gate electrode 8, the free carriers of the semiconductor material of the layer 14 accumulate at the interface between the layer of semiconductor material 14 and the channel 12 superconducting, which has the effect of reducing the surface roughness by proximity effect. The minimum value Icjnin of the critical current Ic is obtained for a minimum roughness of the upper surface of the superconducting channel 12.
Pour une deuxième valeur de la tension de polarisation Vg de l'électrode de grille 8, les porteurs libres du matériau semi-conducteur de la couche 14 sont dépiétés à la interface entre la couche de matériau semi-conducteur 14 et le canal 12 supraconducteur, ce qui a pour effet d'augmenter la rugosité de surface par effet de proximité. La valeur maximale Icjnax du courant critique Ic est obtenue pour une rugosité maximal e d e l a s u rfa ce s u péri e u re d u ca n a l 1 2 supraconducteur.For a second value of the bias voltage Vg of the gate electrode 8, the free carriers of the semiconductor material of the layer 14 are depleted at the interface between the layer of semiconductor material 14 and the superconducting channel 12, which has the effect of increasing the surface roughness by proximity effect. The maximum value Icjnax of the critical current Ic is obtained for a maximum roughness e of the surface of the superconducting circuit.
En effet, la rugosité de surface du canal 12 supraconducteur contribue à l'ancrage des vortex en offrant des sites de raccordement des vortex non normaux à la surface moyenne. Les vortex étant ancrés, ils ne perturbent pas le régime supraconducteur du canal 12, qui agit toujours sensiblement comme un conducteur parfait, ce qui correspond à un fort courant critique.Indeed, the surface roughness of the superconducting channel 12 contributes to vortex anchoring by providing sites for connecting non-normal vortices to the average surface. The vortex being anchored, they do not disturb the superconducting regime of the channel 12, which still acts substantially as a perfect conductor, which corresponds to a strong critical current.
Inversement, le déplacement du réseau de vortex n'est pas contraint lorsque la surface du canal 12 est peu rugueuse, voire lisse. Le mouvement du réseau de vortex crée alors une force électromotrice, puisque chaque vortex porte un flux magnétique, et le canal 12 supraconducteur n'agit plus comme un conducteur parfait, ce qui correspond à un faible courant critique.Conversely, the displacement of the vortex network is not constrained when the surface of the channel 12 is slightly rough, or even smooth. The movement of the vortex network then creates an electromotive force, since each vortex carries a magnetic flux, and the superconducting channel 12 no longer acts as a perfect conductor, which corresponds to a low critical current.
Ainsi, un échantillon de forte rugosité présente un fort courant critique, et inversement, un échantillon de faible rugosité présente un faible courant critique. Le courant critique est sensiblement nul pour une surface sensiblement lisse.Thus, a sample of high roughness has a high critical current, and conversely, a sample of low roughness has a low critical current. The critical current is substantially zero for a substantially smooth surface.
Cette relation entre la rugosité de surface et le courant critique est bien connue de l'homme de métier, et est, par exemple, décrite dans la publication intitulée «Quantitative analysis of the critical current due to vortex pinning by surface corrugation » de Pautrat, Scola, Goupil et al., parue dans la revueThis relationship between the surface roughness and the critical current is well known to those skilled in the art, and is, for example, described in the publication entitled "Quantitative analysis of the critical current due to vortex pinning by surface corrugation "Pautrat, Scola, Goupil et al., published in the journal
Physical Review, B69, article n° 224504 de juin 2004.Physical Review, B69, article n ° 224504 of June 2004.
Sous l'action de la tension de polarisation Vg de l'électrode de grille 8, le transistor 2 supraconducteur permet de contrôler l'ancrage ou le désancrage des vortex, et donc de contrôler la valeur seuil d'apparition d'une résistance électrique non nulle du canal 12 supraconducteur.Under the action of the bias voltage Vg of the gate electrode 8, the superconducting transistor 2 makes it possible to control the anchoring or the decanting of the vortices, and thus to control the threshold value for the appearance of a non-electrical resistance. null of the superconducting channel 12.
L'effet dit de proximité caractérise le fait qu'une couche de matériau semiconducteur fortement dopé, déposé sur une couche supraconductrice devient elle- même supraconductrice sur une pellicule dont l'épaisseur est liée à la mobilité et à la concentration en porteurs libres. Cet effet est bien connu de l'homme du métier, et est décrit par exemple dans la publication intitulée «Boundary effects in superconductors » de Pierre-Gilles de Gennes, parue dans la revue Reviews of Modem Physics de janvier 1964.The so-called proximity effect characterizes the fact that a layer of highly doped semiconductor material deposited on a superconducting layer itself becomes superconductive on a film whose thickness is related to the mobility and to the concentration of free carriers. This effect is well known to those skilled in the art, and is described for example in the publication entitled "Boundary effects in superconductors" by Pierre-Gilles de Gennes, published in the journal Reviews of Modern Physics of January 1964.
Si la tension de polarisation Vg de l'électrode de grille 8 conduit à accroître la concentration en porteurs libres au voisinage de l'interface entre le canal 12 supraconducteur et la couche 14 semi-conductrice, alors la rugosité se trouve lissée et diminue, et le courant critique Ic diminue jusqu'à la valeur minimale Icjnin. Lorsque la valeur du courant critique Ic est proche de la valeur minimale Icjnin, le transistor 2 supraconducteur est dans l'état bloqué. Si au contraire la tension de polarisation Vg de l'électrode de grille 8 conduit à dépléter l'interface entre le canal 12 supraconducteur et la couche 14 semi- conductrice, alors la rugosité de surface augmente, impliquant une augmentation du courant critique Ic jusqu'à sa valeur maximale Icjnax. Lorsque la valeur du courant critique Ic est proche de la valeur maximale lc_max, le transistor 2 supraconducteur est dans l'état passant.If the bias voltage Vg of the gate electrode 8 leads to increasing the concentration of free carriers in the vicinity of the interface between the superconducting channel 12 and the semiconductor layer 14, then the roughness is smoothed and decreases, and the critical current Ic decreases to the minimum value Icjnin. When the value of the critical current Ic is close to the minimum value Icjnin, the superconducting transistor 2 is in the off state. If, on the other hand, the bias voltage Vg of the gate electrode 8 leads to depleting the interface between the superconducting channel 12 and the semiconductor layer 14, then the surface roughness increases, implying an increase in the critical current Ic up to at its maximum value Icjnax. When the value of the critical current Ic is close to the maximum value lc_max, the superconducting transistor 2 is in the on state.
L'interface entre la couche 14 semi-conductrice et le canal 12 supraconducteur se comporte ainsi comme une surface à rugosité variable en fonction de la tension de polarisation Vg de l'électrode de grille 8.The interface between the semiconductor layer 14 and the superconducting channel 12 thus behaves as a surface with variable roughness as a function of the bias voltage Vg of the gate electrode 8.
Lorsque le transistor 2 supraconducteur est passant, le courant circule de l'électrode de source 4 vers l'électrode de drain 6 à la fois dans le canal 12 supraconducteur et dans l'épaisseur de la couche 14 de matériau semiconducteur où se trouvent les porteurs libres. Cette épaisseur de couche 14 de matériau semi-conducteur est alors supraconductrice par effet de proximité. Le transistor 2 selon l'invention autorise ainsi le contrôle direct, par effet de champ électrostatique, du courant critique Ic du canal 12 supraconducteur.When the superconducting transistor 2 is conducting, the current flows from the source electrode 4 to the drain electrode 6 in both the superconducting channel 12 and in the thickness of the semiconductor material layer 14 where the carriers are located. free. This thickness of layer 14 of semiconductor material is then superconducting by proximity effect. The transistor 2 according to the invention thus allows the direct control, by electrostatic field effect, of the critical current Ic of the superconducting channel 12.
Avantageusement, le transistor 2 supraconducteur selon l'invention est susceptible d'être utilisé pour des applications dans le domaine des forts courants, telles que la commutation de puissance et la limitation de courant. En effet, l'état dissipatif du canal 12 supraconducteur ne résulte pas d'une diminution du taux de porteur, mais de la diminution du courant critique Ic par désancrage des vortex.Advantageously, the superconducting transistor 2 according to the invention is capable of being used for applications in the field of high currents, such as power switching and current limiting. Indeed, the dissipative state of the superconducting channel 12 does not result from a reduction of the carrier rate, but from the decrease of the critical current Ic by vortex decanting.
Avantageusement, le transistor 2 supraconducteur selon l'invention permet de commander un courant d'intensité supérieure ou égale à 50 ampères pour chaque centimètre de la largeur L du canal 12 supraconducteur.Advantageously, the superconducting transistor 2 according to the invention makes it possible to control a current of intensity greater than or equal to 50 amperes for each centimeter of the width L of the superconducting channel 12.
Avantageusement, le gain en courant du transistor 2 est important.Advantageously, the current gain of the transistor 2 is important.
Avantageusement, le transistor 2 supraconducteur selon l'invention est susceptible d'être utilisé pour des applications dans le domaine des faibles courants. Avantageusement, la réponse en fréquence du transistor 2 supraconducteur selon l'invention est élevée, puisque la transition entre l'état dissipatif du canal 12 et l'état supraconducteur ou non dissipatif est due à la dynamique des vortex.Advantageously, the superconducting transistor 2 according to the invention is capable of being used for applications in the field of low currents. Advantageously, the frequency response of the superconducting transistor 2 according to the invention is high, since the transition between the dissipative state of the channel 12 and the superconductive or non-dissipative state is due to the dynamics of the vortices.
Avantageusement, le procédé de fabrication selon l'invention du transistor 2 supraconducteur ne nécessite pas de moyen technologique lourd permettant de réaliser un dépôt ou une gravure à l'échelle nanométrique.Advantageously, the manufacturing method according to the invention of the superconducting transistor 2 does not require a heavy technological means making it possible to deposit or etch at the nanoscale.
Avantageusement, le procédé de fabrication selon l'invention ne nécessite pas de réaliser un canal supraconducteur de très faible épaisseur. En effet, la couche subissant l'effet de champ due à la polarisation de l'électrode de grille 8 n'est pas le canal 12 supraconducteur lui-même, mais uniquement la couche 14 semi-conductrice déposée sur le canal 12.Advantageously, the manufacturing method according to the invention does not require a superconducting channel of very small thickness. Indeed, the layer undergoing the field effect due to the polarization of the gate electrode 8 is not the superconducting channel 12 itself, but only the semiconductor layer 14 deposited on the channel 12.
Les figures 3 et 4 illustrent un deuxième mode de réalisation de l'invention, pour lequel les éléments analogues au mode de réalisation décrit précédemment sont repérés par des références identiques. Selon le deuxième mode de réalisation, le transistor 2 supraconducteur à effet de champ ne comporte pas de couche isolante entre l'électrode de grille 8 et la couche de matériau semi-conducteur 14, comme représenté sur la figure 3. Dans ce deuxième mode de réalisation, le transistor 2 est de type JFET (de l'anglais Junction Field Effect Transistor) ou transistor à effet de champ à jonction, pour lequel l'électrode de grille 8 est directement en contact avec le canal 12.Figures 3 and 4 illustrate a second embodiment of the invention, for which the elements similar to the embodiment described above are identified by identical references. According to the second embodiment, the superconducting field effect transistor 2 does not comprise an insulating layer between the gate electrode 8 and the layer of semiconductor material 14, as represented in FIG. In this second embodiment, the transistor 2 is of JFET (Junction Field Effect Transistor) type or junction field effect transistor, for which the gate electrode 8 is directly in contact with the channel 12.
Sur la figure 4, le procédé de fabrication du transistor 2 selon le deuxième mode de réalisation ne comporte pas d'étape de formation d'une couche isolante sur la couche de matériau semi-conducteur 14.In FIG. 4, the method of manufacturing transistor 2 according to the second embodiment does not include a step of forming an insulating layer on the layer of semiconductor material 14.
L'étape 155, dernière étape du procédé de fabrication, consiste en la formation de l'électrode de grille 8, directement sur la couche de matériau semiconducteur 14. Le fonctionnement de ce deuxième mode de réalisation est identique à celui du premier mode de réalisation et n'est donc pas décrit à nouveau.Step 155, the last step of the manufacturing process, consists of the formation of the gate electrode 8, directly on the layer of semiconductor material 14. The operation of this second embodiment is identical to that of the first embodiment. and is therefore not described again.
Les avantages de ce deuxième mode de réalisation sont identiques à ceux du premier mode de réalisation et ne sont donc pas décrits à nouveau.The advantages of this second embodiment are identical to those of the first embodiment and are therefore not described again.
Selon un autre mode de réalisation, le substrat 16 est un substrat amorphe, du type verre ou quartz.According to another embodiment, the substrate 16 is an amorphous substrate, of the glass or quartz type.
Selon un autre mode de réalisation, le substrat 16 est un substrat métallique.According to another embodiment, the substrate 16 is a metal substrate.
Selon un autre mode de réalisation, le substrat 16 est un substrat souple, de type polymère. Selon un autre mode de réalisation, les électrodes de source 4 et de drain 6 sont réalisées en un matériau supraconducteur.According to another embodiment, the substrate 16 is a flexible substrate, of polymer type. According to another embodiment, the source 4 and drain 6 electrodes are made of a superconducting material.
Selon un autre mode de réalisation, les électrodes de source 4 et de drain 6 sont réalisées en un matériau semi-conducteur dopé.According to another embodiment, the source 4 and drain 6 electrodes are made of a doped semiconductor material.
Selon un autre mode de réalisation, le canal 12 supraconducteur est un canal en ailettes.According to another embodiment, the superconducting channel 12 is a finned channel.
Selon un autre mode de réalisation, le matériau supraconducteur du canal 12 est de l'aluminium (Al), du plomb indium (PbIn), du niobium titane (NbTi), du niobium étain (NbSn), ou encore du diboride de magnésium (MgB2).According to another embodiment, the superconducting material of the channel 12 is aluminum (Al), indium lead (PbIn), niobium titanium (NbTi), niobium tin (NbSn), or magnesium diboride ( MgB 2 ).
On conçoit ainsi que le transistor supraconducteur selon l'invention permet de commander le passage de courants de forte intensité à travers son canal supraconducteur, puisque la densité des porteurs libres dans le canal supraconducteur n'est pas affectée par l'effet de champ qui agit uniquement sur la couche de matériau semi-conducteur. On conçoit également que le transistor supraconducteur selon l'invention permet d'amplifier le courant dans le canal avec un gain important, de par la variation importante de la résistance du canal sous l'effet de champ, dû à la polarisation de l'électrode de grille. It is thus conceivable that the superconducting transistor according to the invention makes it possible to control the passage of currents of high intensity through its superconducting channel, since the density of the free carriers in the superconducting channel is not affected by the field effect which acts only on the layer of semiconductor material. It is also conceivable that the superconductive transistor according to the invention makes it possible to amplify the current in the channel with a large gain, due to the large variation in the resistance of the channel under the field effect, due to the polarization of the electrode grid.
Claims
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR0853620A FR2932012B1 (en) | 2008-06-02 | 2008-06-02 | FIELD EFFECT SUPERCONDUCTING TRANSISTOR AND METHOD FOR MANUFACTURING SUCH TRANSISTOR. |
| PCT/FR2009/051010 WO2009156657A1 (en) | 2008-06-02 | 2009-05-29 | Field effect superconductor transistor and method for making such transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| EP2294637A1 true EP2294637A1 (en) | 2011-03-16 |
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Family Applications (1)
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| EP09769498A Withdrawn EP2294637A1 (en) | 2008-06-02 | 2009-05-29 | Field effect superconductor transistor and method for making such transistor |
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| US (1) | US20110254053A1 (en) |
| EP (1) | EP2294637A1 (en) |
| FR (1) | FR2932012B1 (en) |
| WO (1) | WO2009156657A1 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2019160572A2 (en) | 2017-05-16 | 2019-08-22 | PsiQuantum Corp. | Gated superconducting photon detector |
| WO2019160573A2 (en) | 2017-05-16 | 2019-08-22 | PsiQuantum Corp. | Superconducting signal amplifier |
| US10586910B2 (en) | 2017-07-28 | 2020-03-10 | PsiQuantum Corp. | Superconductor-based transistor |
| US10374611B2 (en) | 2017-10-05 | 2019-08-06 | PsiQuantum Corp. | Superconducting logic components |
| US10461445B2 (en) | 2017-11-13 | 2019-10-29 | PsiQuantum Corp. | Methods and devices for impedance multiplication |
| WO2019157077A1 (en) | 2018-02-06 | 2019-08-15 | PsiQuantum Corp. | Superconducting photon detector |
| WO2019160871A2 (en) | 2018-02-14 | 2019-08-22 | PsiQuantum Corp. | Superconducting field-programmable gate array |
| US11313719B2 (en) | 2018-05-01 | 2022-04-26 | PsiQuantum Corp. | Photon number resolving superconducting detector |
| US10984857B2 (en) | 2018-08-16 | 2021-04-20 | PsiQuantum Corp. | Superconductive memory cells and devices |
| US10573800B1 (en) | 2018-08-21 | 2020-02-25 | PsiQuantum Corp. | Superconductor-to-insulator devices |
| US11101215B2 (en) | 2018-09-19 | 2021-08-24 | PsiQuantum Corp. | Tapered connectors for superconductor circuits |
| US11719653B1 (en) | 2018-09-21 | 2023-08-08 | PsiQuantum Corp. | Methods and systems for manufacturing superconductor devices |
| WO2020162993A1 (en) * | 2018-10-27 | 2020-08-13 | PsiQuantum Corp. | Superconductor switch |
| US10944403B2 (en) | 2018-10-27 | 2021-03-09 | PsiQuantum Corp. | Superconducting field-programmable gate array |
| US11289590B1 (en) | 2019-01-30 | 2022-03-29 | PsiQuantum Corp. | Thermal diode switch |
| US11569816B1 (en) | 2019-04-10 | 2023-01-31 | PsiQuantum Corp. | Superconducting switch |
| US11009387B2 (en) | 2019-04-16 | 2021-05-18 | PsiQuantum Corp. | Superconducting nanowire single photon detector and method of fabrication thereof |
| US11380731B1 (en) | 2019-09-26 | 2022-07-05 | PsiQuantum Corp. | Superconducting device with asymmetric impedance |
| US11585695B1 (en) | 2019-10-21 | 2023-02-21 | PsiQuantum Corp. | Self-triaging photon detector |
| US11994426B1 (en) | 2019-11-13 | 2024-05-28 | PsiQuantum Corp. | Scalable photon number resolving photon detector |
| IT202100027515A1 (en) | 2021-10-27 | 2023-04-27 | Consiglio Nazionale Ricerche | Superconducting variable inductance transistor |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPS63283177A (en) * | 1987-05-15 | 1988-11-21 | Toshiba Corp | Superconducting transistor |
| FR2674067B1 (en) * | 1991-03-15 | 1993-05-28 | Thomson Csf | SEMICONDUCTOR DEVICE WITH JOSEPHSON EFFECT. |
| US5686745A (en) * | 1995-06-19 | 1997-11-11 | University Of Houston | Three-terminal non-volatile ferroelectric/superconductor thin film field effect transistor |
| US7867791B2 (en) * | 2005-07-29 | 2011-01-11 | Semiconductor Energy Laboratory Co., Ltd. | Manufacturing method of semiconductor device using multiple mask layers formed through use of an exposure mask that transmits light at a plurality of intensities |
-
2008
- 2008-06-02 FR FR0853620A patent/FR2932012B1/en not_active Expired - Fee Related
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2009
- 2009-05-29 WO PCT/FR2009/051010 patent/WO2009156657A1/en active Application Filing
- 2009-05-29 US US12/995,781 patent/US20110254053A1/en not_active Abandoned
- 2009-05-29 EP EP09769498A patent/EP2294637A1/en not_active Withdrawn
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Also Published As
| Publication number | Publication date |
|---|---|
| FR2932012B1 (en) | 2011-04-22 |
| US20110254053A1 (en) | 2011-10-20 |
| WO2009156657A1 (en) | 2009-12-30 |
| FR2932012A1 (en) | 2009-12-04 |
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