EP2173148A4 - Ceramic multilayer substrate - Google Patents

Ceramic multilayer substrate

Info

Publication number: EP2173148A4
Authority: EP; European Patent Office
Prior art keywords: multilayer substrate; ceramic multilayer; ceramic; substrate; multilayer
Prior art date: 2007-08-29
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Granted

Application number

EP08791765A

Other languages

German (de)

French (fr)

Other versions

EP2173148A1 (en

EP2173148B1 (en

Inventor

Masato Nomiya

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

Murata Manufacturing Co Ltd

Original Assignee

Murata Manufacturing Co Ltd

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

2007-08-29

Filing date

2008-07-28

Publication date

2010-09-08

2008-07-28 Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd

2010-04-07 Publication of EP2173148A1 publication Critical patent/EP2173148A1/en

2010-09-08 Publication of EP2173148A4 publication Critical patent/EP2173148A4/en

2013-01-09 Application granted granted Critical

2013-01-09 Publication of EP2173148B1 publication Critical patent/EP2173148B1/en

Status Not-in-force legal-status Critical Current

2028-07-28 Anticipated expiration legal-status Critical

Classifications

- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/403—Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/15—Ceramic or glass substrates
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0183—Dielectric layers
- H05K2201/0195—Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/096—Vertically aligned vias, holes or stacked vias
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09709—Staggered pads, lands or terminals; Parallel conductors in different planes
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09845—Stepped hole, via, edge, bump or conductor
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
- H05K3/0052—Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
- H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
- H05K3/4061—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in inorganic insulating substrates
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
- H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets

Landscapes

Engineering & Computer Science (AREA)
Microelectronics & Electronic Packaging (AREA)
Computer Hardware Design (AREA)
Physics & Mathematics (AREA)
Condensed Matter Physics & Semiconductors (AREA)
General Physics & Mathematics (AREA)
Power Engineering (AREA)
Manufacturing & Machinery (AREA)
Chemical & Material Sciences (AREA)
Ceramic Engineering (AREA)
Production Of Multi-Layered Print Wiring Board (AREA)
Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

EP08791765A 2007-08-29 2008-07-28 Ceramic multilayer substrate Not-in-force EP2173148B1 (en)

Applications Claiming Priority (2)

Application Number	Priority Date	Filing Date	Title
JP2007223249		2007-08-29
PCT/JP2008/063530 WO2009028289A1 (en)	2007-08-29	2008-07-28	Ceramic multilayer substrate

Publications (3)

Publication Number	Publication Date
EP2173148A1 EP2173148A1 (en)	2010-04-07
EP2173148A4 true EP2173148A4 (en)	2010-09-08
EP2173148B1 EP2173148B1 (en)	2013-01-09

Family

ID=40387017

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
EP08791765A Not-in-force EP2173148B1 (en)	2007-08-29	2008-07-28	Ceramic multilayer substrate

Country Status (5)

Country	Link
US (1)	US8450615B2 (en)
EP (1)	EP2173148B1 (en)
JP (1)	JP5229227B2 (en)
CN (1)	CN101785374B (en)
WO (1)	WO2009028289A1 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
JP5550280B2 (en) *	2009-07-29	2014-07-16	京セラ株式会社	Multilayer wiring board
JP5423621B2 (en) *	2010-06-04	2014-02-19	株式会社デンソー	Circuit board terminal connection structure
JP5791283B2 (en) *	2011-01-28	2015-10-07	京セラ株式会社	Electronic component storage package and electronic device including the same
JP5966146B2 (en) *	2012-05-10	2016-08-10	パナソニックＩｐマネジメント株式会社	Multilayer electronic component and manufacturing method thereof
WO2014020975A1 (en) *	2012-07-31	2014-02-06	株式会社村田製作所	Layered substrate
JP6133901B2 (en) *	2012-12-27	2017-05-24	京セラ株式会社	Wiring board, electronic device and light emitting device
WO2019172336A1 (en) *	2018-03-08	2019-09-12	京セラ株式会社	Light emitting element mounting substrate and light emitting device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US20020177360A1 (en) *	2001-05-25	2002-11-28	Murata Manufacturing Co., Ltd.	Composite electronic component and method of producing same
DE10224057A1 (en) *	2002-05-31	2004-01-08	Robert Bosch Gmbh	Ceramic electronics device, of multiple layer construction, has internal electrical connections provided by external conductor grooves, transverse to the layer edges
US20060115637A1 (en) *	2003-10-06	2006-06-01	Masanori Hongo	Multilayer ceramic substrate and its manufacturing method

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
JPH05110258A (en)	1991-10-15	1993-04-30	Hitachi Ltd	Multilayer ceramic board
JPH0697656A (en) *	1992-09-11	1994-04-08	Matsushita Electric Ind Co Ltd	Production of ceramic multilayered board
JPH08162765A (en)	1994-12-09	1996-06-21	Ibiden Co Ltd	Multilayer printed wiring board
JP2002237680A (en)	1997-02-03	2002-08-23	Ibiden Co Ltd	Printed circuit board and its manufacturing method
JPH10308584A (en) *	1997-05-08	1998-11-17	Sumitomo Kinzoku Electro Device:Kk	Ceramic multilayered board and its manufacture
JP2000277916A (en)	1999-03-29	2000-10-06	Kyocera Corp	Board and split board
JP2002026523A (en)	2000-07-07	2002-01-25	Tamagawa Seiki Co Ltd	Multi-layer printed circuit board through-hole structure
JP2003017851A (en) *	2001-06-29	2003-01-17	Murata Mfg Co Ltd	Manufacturing method of multilayer ceramic substrate
JP2003101225A (en) *	2001-09-26	2003-04-04	Kyocera Corp	Ceramic board and split circuit board
US7381283B2 (en) *	2002-03-07	2008-06-03	Yageo Corporation	Method for reducing shrinkage during sintering low-temperature-cofired ceramics
JP4696443B2 (en) *	2003-09-19	2011-06-08	株式会社村田製作所	Manufacturing method of multilayer ceramic substrate
JP2006165108A (en)	2004-12-03	2006-06-22	Asahi Glass Co Ltd	Ceramic circuit board
JP2007207802A (en)	2006-01-31	2007-08-16	Sharp Corp	Electronic circuit module and method of manufacturing same
JP2008270741A (en) *	2007-03-27	2008-11-06	Kyocera Corp	Wiring board

2008
- 2008-07-28 JP JP2009530025A patent/JP5229227B2/en not_active Expired - Fee Related
- 2008-07-28 WO PCT/JP2008/063530 patent/WO2009028289A1/en active Application Filing
- 2008-07-28 EP EP08791765A patent/EP2173148B1/en not_active Not-in-force
- 2008-07-28 CN CN2008801044688A patent/CN101785374B/en not_active Expired - Fee Related
2010
- 2010-02-26 US US12/713,199 patent/US8450615B2/en active Active

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US20020177360A1 (en) *	2001-05-25	2002-11-28	Murata Manufacturing Co., Ltd.	Composite electronic component and method of producing same
DE10224057A1 (en) *	2002-05-31	2004-01-08	Robert Bosch Gmbh	Ceramic electronics device, of multiple layer construction, has internal electrical connections provided by external conductor grooves, transverse to the layer edges
US20060115637A1 (en) *	2003-10-06	2006-06-01	Masanori Hongo	Multilayer ceramic substrate and its manufacturing method

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO2009028289A1 *

Also Published As

Publication number	Publication date
CN101785374A (en)	2010-07-21
US20100147568A1 (en)	2010-06-17
US8450615B2 (en)	2013-05-28
CN101785374B (en)	2011-12-07
EP2173148A1 (en)	2010-04-07
JPWO2009028289A1 (en)	2010-11-25
WO2009028289A1 (en)	2009-03-05
JP5229227B2 (en)	2013-07-03
EP2173148B1 (en)	2013-01-09

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EP2130672A4 (en)	2012-04-25	Flexible substrate
PT2144966E (en)	2013-03-28	Multilayer structure
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EP2014626A4 (en)	2012-01-04	Semiconductor ceramic composition
HUE051583T2 (en)	2021-03-01	Ceramic assembly
IL180783A0 (en)	2007-06-03	Ceramic matrix laminates
EP2159207A4 (en)	2014-06-18	Semiconductor ceramic material
EP2228353A4 (en)	2012-01-04	Semiconductor ceramic composition
EP2014462A4 (en)	2010-02-10	Multilayer film
EP2019946A4 (en)	2011-10-05	Ceramic heating elements
IL201780A0 (en)	2010-06-16	Ceramic material
EP2173148A4 (en)	2010-09-08	Ceramic multilayer substrate
EP2106554A4 (en)	2013-05-15	Second surface metallization
EP2129201A4 (en)	2010-12-22	Multilayer wiring substrate
GB0612357D0 (en)	2006-08-02	Multi-layer coatings
DE602007008043D1 (en)	2010-09-09	Multilayer ceramic substrate
GB0821674D0 (en)	2008-12-31	Ceramic
GB0621627D0 (en)	2006-12-06	Ceramic pigments
TWI368303B (en)	2012-07-11	Packaging substrate structure
EP2128111A4 (en)	2011-03-09	Crystal aligned ceramic

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2011-05-04	17Q	First examination report despatched	Effective date: 20110401
2011-12-07	RIC1	Information provided on ipc code assigned before grant	Ipc: H05K 1/11 20060101ALI20111103BHEP Ipc: H05K 3/46 20060101AFI20111103BHEP Ipc: H01L 23/498 20060101ALI20111103BHEP Ipc: H05K 3/40 20060101ALI20111103BHEP
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