Classifications

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  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/02—Details
  • H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
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  • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
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  • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
  • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
  • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
  • H01L23/49838—Geometry or layout
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  • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
  • H01L23/5386—Geometry or layout of the interconnection structure
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  • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
  • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
  • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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  • H01L2224/321—Disposition
  • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
  • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
  • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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  • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
  • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
  • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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  • H01L2224/732—Location after the connecting process
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  • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L24/42—Wire connectors; Manufacturing methods related thereto
  • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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  • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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  • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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  • H01L2924/10251—Elemental semiconductors, i.e. Group IV
  • H01L2924/10253—Silicon [Si]
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  • H01L2924/14—Integrated circuits
  • H01L2924/143—Digital devices
  • H01L2924/1433—Application-specific integrated circuit [ASIC]
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  • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
  • H01L2924/151—Die mounting substrate
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  • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
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  • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
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  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
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  • H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
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  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K3/00—Apparatus or processes for manufacturing printed circuits
  • H05K3/22—Secondary treatment of printed circuits
  • H05K3/28—Applying non-metallic protective coatings
  • H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
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  • H05K3/00—Apparatus or processes for manufacturing printed circuits
  • H05K3/46—Manufacturing multilayer circuits
  • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits

Definitions

• Embodiments of the present invention relate to a method of forming a chip carrier substrate to prevent warping, and a chip carrier formed thereby.
• Non- volatile semiconductor memory devices such as flash memory storage cards
• flash memory storage cards are becoming widely used to meet the ever-growing demands on digital information storage and exchange.
• Their portability, versatility and rugged design, along with their high reliability and large capacity, have made such memory devices ideal for use in a wide variety of electronic devices, including for example digital cameras, digital music players, video game consoles, PDAs and cellular telephones.
• SD Secure Digital
• electronic devices such as SD cards have included an integrated circuit (“IC") system consisting of several individually packaged ICs each handling different functions, including logic circuits for information processing, memory for storing information, and I/O circuits for information exchange with the outside world.
• the individually packaged ICs have been mounted separately on a substrate such as a printed circuit board to form the IC system.
• SiP system-in-a-package
• MCM multichip modules
• an MCM includes a plurality of chips mounted side by side on a substrate and then packaged.
• An SiP typically includes a plurality of chips, some or all of which may be stacked on a substrate and then packaged.
• the substrate on which the die and passive components may be mounted in general includes a rigid or soft dielectric base having a conductive layer etched on one or both sides. Electrical connections are formed between the die and the conductive layer(s), and the conductive layer(s) provide an electric lead structure for integration of the die into an electronic system. Once electrical connections between the die and substrate are made, the assembly is then typically encased in a molding compound to provide a protective package.
• the substrate 20 includes a conductance pattern 22 for transferring electrical signals between the various components mounted on the substrate, as well as between the substrate components and the external environment.
• the conductance pattern may have any number of configurations and occupy various amounts of space on the substrate. In that past it has been recognized that if the conducting layer on a surface of the substrate is completely etched away from the areas not forming part of the conductance pattern, this results in areas of different thermal expansion properties, and a build up of mechanical stresses in the substrate upon heating of the substrate during IC package fabrication.
• the metal of the conductance pattern tends to expand upon heating, and having some areas with metal and some areas without results is stress generation in the substrate.
• Embodiments of the present invention relate to a method of forming a chip carrier substrate to prevent warping, and a chip carrier formed thereby.
• the substrate includes a conductance pattern for transferring electrical signals between die and components on the substrate, and a dummy circuit pattern to prevent warpage of the substrate in areas not occupied by the conductance pattern.
• the dummy circuit pattern may have straight line segments with a length controlled so as not to generate stresses within the line segments above a desired stress.
• the desired length of a line segment may be determined experimentally by determining the stress within a straight segment as a function of length, and then setting the length below a desired maximum stress within a given straight segment.
• the desired length of a line segment may be estimated based on the known properties of the materials used in the substrate.
• the dummy circuit pattern may be formed in a plurality of lines, shapes and sizes.
• the dummy circuit pattern may be formed of a plurality of polygons, such as for example hexagons.
• the polygons may be contiguous with each other, or the polygons may be spaced from each other.
• the polygons may each be the same size as each other, or the dummy circuit pattern may include polygons of different sizes.
• the dummy circuit pattern may be formed of randomly shaped polygons formed on the substrate.
• the random shapes may also be randomly oriented and/or randomly positioned on the substrate.
• the random shapes may be contiguous with each other, or they may be spaced from each other in alternative embodiments.
• the dummy circuit pattern may further be formed of random lines on the substrate.
• the lines may have a random orientation, random length and/or a random position on the dummy circuit pattern in alternative embodiments.
• the dummy circuit pattern may be formed on a photomask, along with the conductance pattern, and then etched into the conductive layers on the top and/or bottom of the substrate in a known etching process.
• Figure 1 is a top view of a prior art substrate including a cross-hatched dummy circuit pattern.
• Figure 2 is a top view of a substrate including a conductance pattern and a dummy circuit pattern according to embodiments of the present invention in regions not occupied by the conductance pattern.
• Figure 3 is a cross-sectional view of the substrate shown in Fig. 2.
• Figure 4 is a top view of a substrate including a conductance pattern and a dummy circuit pattern according to an alternative embodiment of the present invention.
• Figure 5 is a top view of a substrate including a conductance pattern and a dummy circuit pattern according to a second alternative embodiment of the present invention.
• Figure 6 is a top view of a substrate including a conductance pattern and a dummy circuit pattern according to a third alternative embodiment of the present invention.
• Figure 7 is a top view of a substrate including a conductance pattern and a dummy circuit pattern according to a fourth alternative embodiment of the present invention.
• Figure 8 is a top view of a substrate including a conductance pattern and a dummy circuit pattern according to a fifth alternative embodiment of the present invention.
• Figure 9 is a cross-sectional side view of a substrate including a plurality of conductive layers, one or more of which may include a dummy circuit pattern as shown in any of the above-described embodiments.
• Figure 10 is a cross-sectional side view of a semiconductor package including a substrate having a dummy circuit pattern according to an embodiment of the present invention.
• Figure 11 is a flow chart illustrating a process for fabricating the conductance pattern and dummy circuit pattern on a substrate.
• Figure 12 is an overall flowchart of a process for fabricating a semiconductor package including a dummy circuit pattern according to embodiments of the present invention.
• Fig. 2 is a top view of a chip carrier substrate 100
• Fig. 3 is a cross- sectional view through a plane normal to the top and bottom surfaces of substrate 100.
• substrate 100 may have a top surface 102 and a bottom surface 104.
• Substrate 100 may be formed of an electrically insulative core 106 having a top conductive layer 108 formed on a top surface of the core and a bottom conductive layer 110 formed on a bottom surface of the core.
• the core may be formed of various dielectric materials such as for example, polyimide laminates, epoxy resins including FR4 and FR5, bismaleiniide triazine (BT), and the like.
• core 106 may have a thickness of between 40 microns ( ⁇ m) to 200 ⁇ m, although thickness of the core may vary outside of that range in alternative embodiments.
• the core may be ceramic or organic in alternative embodiments.
• the conductive layers 108 and 110 may be formed of copper, copper alloy or other low resistance electrical conductor, and may be patterned in a conductance pattern and dummy circuit according to embodiments of the present invention as explained hereinafter.
• the layers 108 and/or 110 may have a thickness of about 10 ⁇ m to 24 ⁇ m, although the thickness of the layers 108 and 110 may vary outside of that range in alternative embodiments.
• the top and bottom conductive layers may be laminated with a solder mask 112, 114, respectively, as is known in the art.
• Substrate 100 may be patterned and configured for use in a wide variety of semiconductor packages.
• One such package is a so-called land grid array (LGA) semiconductor package used, for example, in SD Flash Memory Cards.
• LGA land grid array
• the dummy circuit pattern explained hereinafter may be used on any substrate in which a conductance pattern may be formed and assembled into a semiconductor device.
• one or both of the conductive layers 108 and 110 may be etched or otherwise processed as explained hereinafter so as to include a conductance pattern 120 to provide electrical connection between components mounted to substrate 100, as well as between components on substrate 100 and external devices.
• a conductance pattern 120 to provide electrical connection between components mounted to substrate 100, as well as between components on substrate 100 and external devices.
• vias may be provided to transmit electrical signals between the conductance patterns in different layers.
• Substrate 100 further includes a plurality of regions 122, 124, 126 not having a conductance pattern, referred to herein as dummy circuit regions.
• a dummy circuit pattern 130 may be formed in one or more of the dummy circuit regions 122, 124, and 126. It is understood that the size and shape of substrate 100, as well as the size and shape of conductance pattern 102 may vary greatly in alternative embodiments of the present invention so as to define one or more dummy circuit regions of any size or shape. Dummy circuit 130 may be provided in any one or more of these dummy circuit regions.
• a dummy circuit pattern according to any of the embodiments described hereinafter may be provided on both sides of the substrate, even where a conductance pattern is provided only on one side of the substrate. It is conceivable that a substrate may be used in a semiconductor device which does not include a conductance pattern on either first or second opposed surfaces of the substrate. Such a substrate may be formed with a dummy circuit pattern according to embodiments of the present invention.
• the dummy circuit pattern is comprised of lines and/or shapes.
• the lines and/or shapes are provided in a given density in the one or more dummy circuit regions. Density refers to the number, length and/or amount of material in the conductive traces forming a dummy circuit pattern, or the conductance pattern, per a unit of area on the substrate.
• the stress level within a straight segment in a portion of a dummy circuit pattern will be linearly or non-linearly related to the length of that straight segment when the substrate is heated. In general, the longer the length, the greater the stress upon heating. [0036] With regard to the maximum length of a straight segment in any portion of a dummy circuit pattern according to the embodiments described hereinafter, the length of a straight segment may be set to maintain the stresses within that straight segment below a desired level.
• the stress per unit length of a straight segment of a portion of the dummy circuit may be determined experimentally and/or by known physical characteristics and behavior of the substrate materials as a function of the type of the materials used, the thicknesses of the materials used and the temperature range to which the materials are to be subjected. Other characteristics may be included in the analysis.
• the maximum length of a straight segment of a portion of the dummy circuit may be selected to maintain the stresses within that segment below any desired, predetermined level.
• a desired maximum stress may be selected, and then the length of all or a portion of the straight segments in a dummy circuit may be set to maintain a stress at or below the selected stress level. It is understood that a quantitative analysis of stress per unit length need not be performed, and the maximum length of a straight segment may instead be estimated in embodiments of the invention. It is also understood that a dummy circuit pattern may include straight segments in which stresses exceeding a predetermined maximum may result in those segments upon heating in embodiments of the invention.
• the density of a dummy circuit pattern without regard to other factors which may contribute to stress within a substrate, stresses within the substrate may be minimized when the density of the dummy pattern approximates that of the conductance pattern.
• the density of a dummy circuit pattern may be selected to approximate that of a given conductance pattern on a substrate in embodiments of the invention.
• the density of the dummy circuit pattern may be selected to be greater or lesser than the density of the conductance pattern, such that the resulting stresses on the substrate remain within predetermined acceptable levels. It is understood that a quantitative analysis of stress resulting from a difference in densities between the dummy circuit pattern and conductance pattern need not be performed, and the density of the dummy circuit pattern may instead be estimated in embodiments of the invention.
• the dummy circuit pattern 130 is formed of a plurality of contiguous, aligned cells 130' etched into layer 108 and/or 110.
• Each of the contiguous cells may be uniform in shape, and fit together so as not to leave any spaces between the cells. It is understood that individual cells may fit together so as to leave a space therebetween in alternative embodiments.
• Pattern 130 is etched or otherwise processed so that no straight line extends through any two contiguous cells 130'.
• the individual cells 130' are hexagonal, forming a honeycomb pattern 130.
• the length of the various straight segment traces forming the pattern 130 may be controlled to maintain the stress generation within the straight segments below a predetermined, desired stress level.
• the length of the straight segments forming each cell 130' may range between about 50 ⁇ m and 250 ⁇ m, and more particularly between 70 ⁇ m and 150 ⁇ m. It is understood to the maximum length of a cell 130' segment may have a maximum diameter larger than 250 ⁇ m and smaller than 50 ⁇ m in alternative embodiments.
• the width of the individual traces forming the various sides of each cell 130' may be between approximately 70 ⁇ m and 150 ⁇ m, although the width of each cell may be larger or smaller than that in alternative embodiments of the present invention.
• Each of the dummy circuit regions 122 through 126 may include the same sized cells 130'.
• the cells in one or more regions (122, 124) may be larger than the cells 130' in other dummy circuit regions (126).
• dummy circuit pattern 130 may be omitted from one or more of the dummy circuit regions.
• individual cells 130' within a given dummy circuit region may be of different sizes.
• each individual cell 130' had a uniform shape.
• one or more of the dummy regions 122, 124, and 126 may include a dummy circuit pattern 140 including a plurality of irregular, randomly shaped cells 140'.
• the random shapes of cells 140' may be created in the pattern mask laid down on the substrate as explained hereinafter.
• a controller for creating the pattern mask may include software for generating random shapes.
• the configuration of the random shapes may be created, and then the information transferred to the system that creates the pattern mask.
• Fig. 4 shows randomly shaped, straight-edged polygons, one or more of the cells 140' may have rounded edges in alternative embodiments of the present invention.
• each randomly shaped cell 140' may each be positioned at a random location within a given dummy circuit region.
• each dummy circuit region may be subdivided into predefined sub-regions, and the cell distribution across the various sub-regions controlled, but the positioning of a cell 140' within a given sub-region randomly determined.
• the position of each randomly shaped cell may be predetermined within a dummy circuit region.
• any two adjacent cells 140' will have a continuous straight line extending therethrough. While it is possible that edges of two randomly shaped cells will align in this embodiment, the likelihood of any two randomly shaped adjacent cells having aligning sides forming a straight line therebetween in exceedingly small.
• the average length of any side in a randomly shaped cell 140' may range between 0.3mm and lmm in an embodiment of the present invention. However, it is appreciated that the average size of any side of a randomly shaped cell 140' may be greater or smaller than that range in alternative embodiments of the present invention. Additionally, it is understood that the standard deviation from that average size may vary in alternative embodiments of the present invention. hi embodiments, the thickness of the lines 140' may be approximately 50 ⁇ m, but this may vary in embodiments of the invention.
• the average size of the randomly shaped cells 140' may be the same or different in the different dummy circuit regions 122-126.
• the dummy circuit pattern 140 may be omitted from one or more of the dummy circuit regions 122-126.
• the density of the dummy circuit pattern 140 may be controlled to be generally the same as, less than or greater than the density of the conductance pattern 120 as described above.
• a chip-carrying substrate 100 may include a conductance pattern 120 and one or more dummy circuit regions 122-126, each including a dummy circuit pattern 150 comprised of randomly oriented lines 150'.
• Lines 150' may be straight or curved. Where straight, the length of each line 150' may be selected to be less than a predetermined length. Alternatively, the average length of all lines 150' may be selected to be below a predetermined.
• the density of the lines within a dummy circuit pattern 150 may approximate the density of the conductance pattern, or may be greater than or lesser than the density of the conductance pattern as described above.
• the thickness of the lines 150' may be approximately 50 ⁇ m, but this may vary in embodiments of the invention.
• the lines 150' are randomly oriented, randomly sized (within a given range), and randomly positioned. It is understood that one or more of the orientation, length, and location of the lines 150' may be controlled so as not to be random in alternative embodiments. Thus, for example, the orientation and position may be random but the length of the lines within pattern 150 may be controlled. Alternatively, the orientation and position of the lines in pattern 150 may be random, but the position partially or completely controlled. Similarly, the length and position of lines 150' may be random and their orientation controlled. Each of the above described properties of lines 150' may be the same for each dummy circuit region, or the above-described properties may vary from one dummy circuit region to the next.
• Fig. 6 shows a further embodiment of the present invention, including a substrate 100 having a conductance pattern 120 and dummy circuit regions 122 through 126.
• the lines and shapes shown in the drawings as the dummy circuit patterns represent trace material that is left behind on the substrate after the pattern is etched or otherwise formed on the substrate.
• the dummy circuit regions each include a dummy circuit pattern 160 wherein the white lines in the drawing represent material that is etched away during the fabrication process, and the dark background represents material from layers 108 or 110 that is left behind after the dummy circuit pattern is formed.
• Dummy circuit pattern 160 includes etched lines 160'. Etched lines 160' may have any of the properties of lines 150' from dummy circuit pattern 150 in Fig. 5. In the embodiment of Fig. 6, the length and density of the lines 160' are preferably selected to reduce the amount of material in layer 108 or 110 after fabrication to maintain the stress levels within dummy circuit pattern 160 and substrate 100 in general to predetermined acceptable levels as described above.
• Fig. 7 shows a further embodiment of the present invention including a substrate 100 having a conductance pattern 120 and dummy circuit regions 122-126.
• One or more of the dummy circuit regions may include a dummy circuit pattern 170 comprised of a plurality of shapes 170'.
• each of the shapes 170' approximates the outline of the letter "C" with the material from within the outline being etched away during the fabrication process. It is understood that a wide variety of other outline shapes be provided in alternative embodiments of the present invention.
• the shapes may alternatively be "filled in.” That is, the material from within the outer outline of the shape may remain after the etching process.
• the majority of segments forming the shapes 170' are curved. Curved shapes have an advantage in that stresses within the shape are minimized. Moreover, semiconductor die and other components are more sensitive to patterns on the substrate that are aligned along the axes of the die and component(s). A curved shape reduces stresses that may otherwise result in a semiconductor die or other component mounted above the shape on the substrate. However, it is understood the shapes 170' may be defined by all or partial straight lines in alternative embodiment of the present invention.
• each of the shapes 170' are spaced from each other of the shapes 170'. It is understood that the shapes may overlap in alternative embodiments of the invention. Moreover the shapes may each be in the same orientation (as in dummy circuit regions 122 and 124), or the orientations of the shapes 170' may differ (as in dummy circuit region 126). The size of each of the shapes 170' within a given dummy circuit region may be the same or different than each other, and the size of the shapes 170' from one dummy region to the next may be the same or different (as shown in Fig. 7). The number, size, and/or position of the shapes 170' may be controlled in each dummy circuit region or may be random.
• Fig. 8 illustrates a further embodiment of the present invention, including a substrate 100 having a conductance pattern 120 and one or more dummy circuit regions 122-126.
• One or more of the dummy circuit regions 122-126 may include a conductance pattern 180 formed of a plurality of cells 180'.
• Fig. 8 is similar to the embodiment of Fig. 2 described above, with the difference that the cells 180' forming dummy circuit pattern 180 may not each have the same size or shape as each other cell 180'.
• a plurality of larger hexagonal cells 180' are joined by a plurality of smaller hexagonal cells 180'.
• the cells 180' may have the properties described above with respect to cells 130' of Fig. 2.
• a plurality of layers 108 and 110 may be provided on the respective upper and lower surfaces of core 106 in substrate 100 in embodiments of the invention.
• core includes three layers 108, each laminated by a layer of solder mask 112 on the top surface 102
• substrate 100 includes three layers 110, each laminated by a layer solder mask 114 on lower surface 104.
• One or more of the layers 108 and 110 may include a conductance pattern 120 and any of the above-described embodiments of a dummy circuit pattern.
• the dummy circuit pattern in the various layers 108 may align with each other or not align with each other in embodiments of the invention.
• Figure 10 is a cross-sectional view of a semiconductor package 182 which may be formed with a substrate 100 including a dummy circuit pattern according to any of the above-described embodiments.
• Fig. 10 shows two stacked semiconductor die 184 on the top surface 102 of substrate 100.
• Embodiments of the invention may operate with a single die or between three and eight or more stacked die in an SiP, MCM, or other type of arrangement.
• the one or more die 184 may be a flash memory chip (NOR/NAND), SRAM 5 or DDT, and/or a controller chip such as an ASIC. Other silicon chips are contemplated.
• the dummy circuit pattern according to embodiments of the present invention described above controls and/or minimizes mechanical stresses on, and warping of, the substrate 100. This in turn results in control over and/or minimizing of the stresses seen by die 184, thus improving overall yield.
• the one or more die 184 may be mounted on the top surface 102 of the substrate 100 in a known adhesive or eutectic die bond process, using a known die attach compound 186.
• the one or more die 184 may be electrically connected to conductive layers 108, 110 of the substrate 100 by wire bonds 188 in a known wire bond process.
• the circuit may be packaged in a molding compound 190 in a known molding process to complete the package 182.
• the dummy circuit pattern may also serve electrical functions.
• the dummy circuit pattern may provide a path to ground (VSS) or be connected to a power source (VDD) to supply power to the semiconductor die and/or other components mounted on the substrate.
• VDD power source
• the dummy circuit pattern may carry signals to and/or from the semiconductor die and substrate components.
• the dummy circuit pattern may be "floating," i.e., it has no electrical function.
• the photoresist film is exposed (step 156) and developed (step 158) to remove the photoresist from areas on the conductive layers that are to be etched.
• the exposed areas are next etched away using an etchant such as ferric chloride in step 160 to define the conductance and dummy circuit patterns on the core.
• the photoresist is removed in step 162, and the solder mask layer is applied in step 164.
• the substrate 100 starts out as a large panel which is separated into individual substrates after fabrication.
• the panel is drilled to provide reference holes off of which the position of the respective substrates is defined.
• the conductance pattern and dummy circuit pattern are then formed on the respective surfaces of the panel in step 222 as explained above.
• the patterned panel is then inspected and tested in step 224. Once inspected, the solder mask is applied to the panel in step 226.
• a router then separates the panel into individual substrates in step 228.
• the individual substrates are then inspected and tested again in an automated step (step 230) and in a final visual inspection (step 232) to check electrical operation, and for contamination, scratches and discoloration.
• the substrates that pass inspection are then sent through the die attach process in step 234, and the substrate and dice are then packaged in step 236 in a known injection mold process to form a JEDEC standard (or other) package. It is understood that the die package 182 including a dummy circuit pattern may be formed by other processes in alternative embodiments.

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• 2006
  • 2006-06-28 JP JP2008519547A patent/JP2009500830A/ja active Pending
  • 2006-06-28 WO PCT/US2006/025303 patent/WO2007005492A1/en active Application Filing
  • 2006-06-28 KR KR1020077030881A patent/KR101015265B1/ko not_active IP Right Cessation
  • 2006-06-28 EP EP06785812A patent/EP1905080A1/en not_active Withdrawn
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