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EP1835374B1 - Device and method of adapting the potential of the substrate of an MOS transistor - Google Patents

Device and method of adapting the potential of the substrate of an MOS transistor Download PDF

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Publication number
EP1835374B1
EP1835374B1 EP07104336.8A EP07104336A EP1835374B1 EP 1835374 B1 EP1835374 B1 EP 1835374B1 EP 07104336 A EP07104336 A EP 07104336A EP 1835374 B1 EP1835374 B1 EP 1835374B1
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EP
European Patent Office
Prior art keywords
mos transistor
transistor
substrate
msw
circuit
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EP07104336.8A
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German (de)
French (fr)
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EP1835374A1 (en
Inventor
Olivier Thomas
Marc Belleville
Vincent Liot
Philippe Flatresse
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STMicroelectronics SA
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
STMicroelectronics SA
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is DC
    • G05F3/10—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/205—Substrate bias-voltage generators

Definitions

  • the present invention relates to a device and a method for biasing the substrate of a metal oxide semiconductor field effect transistor, or MOS transistors.
  • the leakage current is all the more important as the threshold voltage of the transistor is low, the voltage between the substrate (in English body or bulk) and the source of the transistor is high or that the voltage between the gate and the source of the transistor is high.
  • a conventional method of reducing the leakage current of an N-channel MOS transistor whose source is connected to ground is to bias the substrate of the N-channel MOS transistor to a potential lower than the potential of the source.
  • a P-channel MOS transistor whose source receives a supply voltage such a method consists of biasing the transistor substrate to a potential greater than the potential of the source.
  • Such a process is called reverse bulk biasing (reverse bulk biasing).
  • the main drawback of such a method is that the polarization of the transistor substrate is generally performed by a voltage source connected, in the inactive state, to the transistor substrate.
  • the realization of such a voltage source can be relatively complex.
  • the operation of such a voltage source results in additional consumption which limits the decrease in total consumption due to the reduction of the leakage current of the transistor.
  • the present invention aims to overcome all or part of the disadvantages of known devices and methods for biasing the substrate of a MOS transistor.
  • the present invention more specifically relates to a device for biasing the substrate of a MOS transistor which has a reduced power consumption.
  • the polarization device has a relatively simple structure and can be realized at reduced cost.
  • the present invention also aims more particularly at a method of polarizing the substrate of a MOS transistor whose implementation results in a reduced additional consumption.
  • the present invention provides a polarization circuit of the substrate of a MOS transistor, the substrate of the MOS transistor being surrounded by a box providing electrical insulation of the substrate.
  • the circuit comprises a capacitive element connecting the substrate of the MOS transistor to a source of an alternating voltage at a first value for a first duration and at a second value for a second duration less than half of the first duration.
  • the capacitive element comprises an electrode directly connected to the substrate.
  • the source is adapted to supply the AC voltage to the first value during the first duration and to the second value during the second duration less than 1/10 of the first duration.
  • the MOS transistor is an N-channel transistor, the second value being the zero voltage and the first value being greater than the direct voltage drop of the substrate-source junction of the MOS transistor.
  • the circuit comprises means adapted to connect the substrate and the gate of the MOS transistor when the MOS transistor is in the inactive state.
  • the circuit comprises an additional MOS transistor of which the main terminals connect the substrate to the gate of the MOS transistor and means adapted to connect the gate of the additional transistor to the gate of the MOS transistor when the MOS transistor is in the inactive state.
  • the means is adapted to connect the gate of the additional MOS transistor to the substrate of the MOS transistor when the MOS transistor is in the active state.
  • the MOS transistor is formed at a support of the SOI, GeOI or SON type.
  • the MOS transistor comprises a first main terminal connected to a terminal of an electronic circuit and a second main terminal connected to a source of a reference potential, the assembly consisting of the transistor MOS, the capacitive element and the source of the AC voltage forming a charge pump of the substrate of the MOS transistor, the MOS transistor also acting as a switch for the electronic circuit.
  • the present invention also provides a method for polarizing the substrate of a MOS transistor, the substrate of the MOS transistor being surrounded by a box providing electrical insulation of the substrate.
  • the method consists of connecting the substrate of the MOS transistor to a source of an alternating voltage by a capacitive element, the alternating voltage being at a first value for a first duration and at a second value for a second duration less than half the time. first duration.
  • the second duration is less than 1/10 of the first duration.
  • the method further comprises providing an additional MOS transistor whose main terminals connect the substrate to the gate of the MOS transistor and to connect the gate of the additional transistor to the gate of the MOS transistor when the MOS transistor is in the inactive state and to connect the gate of the additional MOS transistor to the substrate of the MOS transistor when the MOS transistor is at the active state.
  • the present invention aims to modify the potential of the substrate of a MOS transistor in the inactive state to reduce the leakage current of the transistor, the modification of the potential of the substrate being obtained by a process which results in only a very low additional consumption.
  • the present invention applies to a transistor for which the potential of the substrate is likely to be modified.
  • the present invention can therefore be applied to an insulated substrate MOS transistor, for example a MOS transistor produced at a silicon on insulator or SOI (Silicon On Insulator) substrate, a germanium on insulator substrate. or GeOI (Germanium On Insulator) or an ultra-thin film silicon substrate or SON (Silicon On None).
  • SOI Silicon on Insulator
  • GeOI Germanium On Insulator
  • SON Ultra-thin film silicon substrate
  • SON Silicon On Nothing
  • the present invention can also be applied to a MOS transistor formed at a silicon wafer for which the transistor substrate is electrically isolated from the remainder of the wafer, for example by means of a box having a type of adapted dopant surrounding the transistor.
  • the polarization of the box is adapted to ensure the isolation of the transistor substrate, that is to say that the box is polarized in reverse vis-à-vis other adjacent junctions to provide electrical isolation of the transistor substrate.
  • the advantage of the partially deserted SOI technology or PD-SOI in terms of performance, is related to the dynamic modulation of the threshold voltage of the transistors.
  • This dynamic modulation is due to the variation of the potential of the floating substrate of the transistors.
  • the disadvantage of a conventional method of reducing the leakage currents of a MOS transistor is that the substrate is no longer floating. In the active state, the advantage of the dynamic modulation of the threshold voltage of the transistor is lost.
  • the advantage of the invention is to control the polarization of the substrate in idle mode while leaving the possibility of leaving the floating substrate in active mode. For this, the potential of the floating substrate of the transistor is controlled by the modulation of its load.
  • the figure 1 represents, very schematically, a section of an N-channel MOS transistor produced at a SOI-type substrate.
  • a support 10 for example a p-type doped silicon wafer, is covered with an insulating layer 12, for example silicon oxide.
  • Active areas 13 of monocrystalline silicon separated by insulating regions 14, 16 are formed on the insulating layer 12.
  • the MOS transistor is formed at one of the active areas 13 and comprises two separate regions 18, 20 doped N-type by a p-type doped region 22.
  • the regions 18, 20 correspond to the drain and the source of the MOS transistor and the region 22 corresponds to the substrate of the MOS transistor.
  • the region 22 is covered with an insulating layer 24, corresponding to the gate oxide, itself covered with a conductive region 26, corresponding to the gate of the transistor.
  • Such a transistor is said to be made according to SOI technology Partially deserted, or SOI-PD, insofar as the substrate 22 of the transistor is left floating.
  • a power MOS transistor is a MOS transistor capable of accepting high currents in the active state and whose leakage current in the inactive state is low compared to the leakage currents of the MOS transistors conventionally used in the electronic circuits and so-called fast switching.
  • a power MOS transistor can conventionally be used as a switch to reduce the consumption of an electronic circuit in the inactive state. To do this, the power MOS transistor is generally available between the electronic circuit and the ground. The power MOS transistor is blocked when the electronic circuit is in the inactive state (or in stand-by) to limit the total electrical losses.
  • the present invention makes it possible to polarize the substrate of the power MOS transistor in order to reduce the leakage current of the transistor used as a switch and thus to further reduce the consumption of the electronic circuit in the inactive state.
  • the present invention can generally be applied to any type of MOS transistor whose inactive leakage current is to be reduced.
  • the figure 2 represents a first exemplary embodiment of a substrate biasing circuit 30 of an N-channel power MOS transistor MSW disposed between an output terminal O of an electronic circuit CL and a source of a reference potential. GND, for example mass.
  • the electronic circuit CL comprises, for example, low threshold voltage MOS transistors which have switching speeds higher than that of the power MOS transistor MSW.
  • the transistor MSW comprises a source S, a drain D, a substrate B and a gate G.
  • the transistor MSW is, for example, made at a SOI type substrate and has the structure represented in FIG. figure 1 .
  • Source S is connected to ground GND and drain D is connected to the output terminal O.
  • the gate G is connected to a terminal of a voltage source SL whose other terminal is connected to ground GND.
  • V SL is called the terminal voltage of the voltage source SL.
  • the circuit 30 comprises a capacitor C 1 , one electrode of which is directly connected to the substrate B and the other electrode of which is connected to a terminal of a voltage source SP.
  • the other terminal of the voltage source SP is connected to GND ground.
  • the voltage at the terminals of the voltage source SP is called V P.
  • the capacitor C 1 comprises two metal electrodes separated by a dielectric material.
  • the region 22 comprises an extension, not shown, for producing a contact pad for connecting the transistor substrate to an electrode of the capacitor C 1 .
  • the capacitor C 1 comprises two polycrystalline silicon electrodes, or a first metal electrode and a second polycrystalline silicon electrode.
  • the region 22 may comprise an extension, not shown, directly in contact with the second electrode.
  • the capacitor C 1 comprises a metal electrode or polycrystalline silicon and an electrode corresponding to a doped silicon region, which is, for example, in contact with the substrate.
  • the voltage sources SP and SL may correspond to any type of electronic circuit adapted to provide the voltages V P and V SL sought. In particular, the voltages V P and V SL can be obtained from a single voltage source.
  • the voltage V P corresponds to a periodic rectangular voltage varying, for example, between the zero voltage and the supply voltage VDD.
  • the period of the voltage V P is for example of the order of 100 ms.
  • the duty cycle ⁇ of the voltage V P corresponds to the ratio between the duration during which the voltage V P is equal to VDD and the duration during which the voltage V P is equal to 0 V.
  • the duty ratio ⁇ is less than 1, for example less than 1/2, preferably less than 1/10, or even less than 1/100 , for example of the order of 1/500 for a circuit realized by an SOI technology.
  • the duty cycle ⁇ may be less than 1/500.
  • the figure 3 represents an evolution curve 32 of the potential of the substrate B, called V B , of the transistor MSW in the inactive state, an evolution curve 33 which corresponds to an enlargement of the evolution curve 32 of the potential V B for the first periods of the signal V P during the inactive state of the transistor MSW and an evolution curve 34 of the signal V P.
  • Curve 32 is drawn to scale.
  • curves 33 and 34 are not drawn to scale.
  • the circuit 30 makes it possible, in the inactive state, to reduce overall the potential V B of the substrate B of the transistor MSW to a negative potential so as to reduce the leakage current of the transistor MSW.
  • the present invention uses the fact that for a MOS transistor whose substrate B is not directly connected to a source of a constant potential, the potential V B depends on the amount of charge Q B stored at the level of the substrate B.
  • V B Q B + VS D ⁇ V D + VS S ⁇ V S + VS BOY WUT ⁇ V BOY WUT + VS 1 ⁇ V P / VS T
  • V D , V S and V G respectively correspond to the potential of the drain D, the source S and the gate G
  • C D , C S and C G respectively correspond to the drain, source and gate capacity
  • C T is the sum of the capacitances C G , C S , C D and C 1 .
  • the amount of charge Q B varies as a function of the charge rate and the discharge rate of the substrate B at a given instant.
  • the charge rate of the substrate B is representative of the phenomena leading to the generation of carriers (for example the formation of a tunnel current, impact ionization phenomena, etc.), that is to say causing an increase in Q B.
  • the rate of discharge of the substrate B is representative of the phenomena leading to carrier recombination (for example the formation of a drain-substrate or source-substrate junction current), that is to say causing a decrease in Q B.
  • the phenomena leading to the recombination of carriers are much faster than the phenomena leading to the generation of carriers with a factor that can vary from 100 to 1000.
  • the quantity of charges Q B is substantially constant and fixed by the potentials V B , V D , V S , V G and the voltage Vp.
  • the charge Q B changes, for a longer or shorter transition phase, to a new static equilibrium.
  • the MSW transistor is in an intermediate state between two equilibrium states.
  • the present invention consists in controlling the amount of charge Q B by varying the voltage V P. More specifically, the present invention utilizes the fact that the time required for charging the substrate is much longer than the time required for the discharge of the substrate so that it is sufficient, to control the amount of charge Q B , to put the voltage V P to VDD periodically for a very short time. Most of the time, the voltage V P is left at 0 V, the amount of charge Q B evolving then little and setting the potential V B to a substantially constant and negative value. As a result, except for the pulses of the voltage V P , the potential V B is substantially permanently constant and negative.
  • the potential V B has sufficiently decreased so that when the voltage V P goes from 0 V to VDD, the potential V B is not high enough to make the substrate junction completely passable. source but only slightly passing to compensate for the generation of charges.
  • the quantity of charge Q B then increases substantially more and the potential V B is maintained, when V P is at 0 V, at a negative value for example between -0.5 V to -1 V.
  • the assembly consisting of the voltage source SP, the capacitor C 1 and the transistor MSW therefore behaves like a charge pump adapted to reduce the amount of charge Q B.
  • the values between which V P varies can be different from 0 V and VDD.
  • the only condition is that the variation of V P causes, by capacitive effect, a variation of the potential V B sufficient to make the substrate-source junction of the transistor MSW pass, at least at the beginning of the transition to the inactive state.
  • the figure 4 represents the evolution of the leakage current I 1 of the circuit 30 as a function of the duty cycle ⁇ .
  • CAD Computer Aided Design
  • SPICE Synchronization Program with Integrated Circuit Emphasis
  • the period of the signal V P is determined so that the dynamic consumption of the circuit 30 is the lowest. Part of the dynamic consumption is due to the switching of the voltage V P on a rising or falling edge. To reduce the dynamic consumption, the period of the signal V P is chosen as large as possible to limit the number of switching of the voltage V P.
  • the figure 5 represents the evolution of the potential V B as a function of time when a falling edge is applied to V P (transition from a high value to a low value).
  • the abscissa scale is a logarithmic scale.
  • the circuit 30 When the circuit 30 goes from the active state to the inactive (or stand-by) state, it is possible, in an initial phase, to accelerate the frequency of the signal V P with respect to the frequency F previously determined, in order to reduce the potential V B of the MSW transistor as quickly as possible. Then, the frequency of the signal V P is reset to the frequency F so as to maintain the potential V B at the low value while reducing the dynamic consumption of the circuit 30.
  • the figure 6 represents a second embodiment of a polarization circuit 40 according to the invention.
  • the circuit 40 corresponds to the circuit 30 represented in figure 2 in which a diode-mounted N-channel transistor MOS MD 1 has been added whose gate G 1 and the drain D 1 are connected to the gate G of the transistor MSW.
  • the source S 1 of the transistor MD 1 is connected to the substrate B of the transistor MSW.
  • a capacitor C 2 is provided between the gate G and the ground GND. According to a variant of the second embodiment, the capacitor C 2 is not present.
  • the voltage source SL is at high impedance and is not represented in figure 6 .
  • the circuit 40 makes it possible to put the substrate B at a negative potential in the inactive state, and, in parallel, to set the gate G of the transistor MSW to a negative potential. Indeed, the leakage current of an N-channel MOS transistor is all the higher as the voltage between the gate and the source is large. This further reduces the leakage current of the transistor MSW to the inactive state.
  • the figure 7 represents a circuit diagram equivalent to the circuit 40 represented in figure 6 in the idle state.
  • the MSW transistor is equivalent to a diode MSW 'whose anode is connected to the substrate B and whose cathode is connected to the ground GND.
  • the transistor MD 1 is equivalent to a diode MD 1 'whose anode is connected to the gate G and whose cathode is connected to the substrate B.
  • the potential V G follows on average the potential V B.
  • the capacitor C 2 if present, stabilizes the potential V G.
  • the figure 7 also corresponds to the diagram of a charge pump. This means that the MSW transistor has two functions: the first is that of the power switch and the second is that of the active element of the charge pump.
  • the transistor MD 1 can be replaced by a diode whose anode is connected to the gate G and whose cathode is connected to the substrate B.
  • the figure 8 represents a bias circuit 45 according to a third embodiment of the invention in which, compared with the circuit 40 represented in FIG. figure 6 Was added between the substrate B and the ground GND, a MOS MD transistor 2 to P channel whose gate G 2 is controlled by a SLEN signal, the drain D2 is connected to ground GND and the source S 2 is connected to the substrate B.
  • the transistor MD 2 When the transistor MD 2 is on, which corresponds to the signal SLEN set to 0 V, the transistor MD 2 behaves as a diode whose anode is connected to the substrate B and whose cathode is connected GND ground.
  • This additional diode is therefore in parallel with the substrate-source junction of the MSW transistor which tends to become conductive when the voltage V P goes to VDD.
  • Such an additional diode makes it possible, when the voltage V P goes to VDD, to ensure that the potential V B does not rise above 0.5-0.6 V and to accentuate the evacuation of the charges from the substrate B.
  • the Applicant has determined, by simulation, the gain in consumption in the case where the electronic circuit CL corresponds to a ring oscillator having 141 stages and constituted by fast switching MOS transistors (that is to say having a threshold voltage low, for example of the order of 240 mV) realized in SOI-PD technology with a gate width of 130 nanometers, and for a supply voltage of 1.2 V.
  • the MSW power switch used is of the type allowing a penalty in time less than 2%.
  • the transistors MD 1 , MD 2 of the circuit 45 are transistors of the low leakage type (high threshold voltage of the order of 350 mV).
  • the figure 9 represents the evolution of the ratio as a function of temperature.
  • Curve 46 corresponds to the evolution of the ratio obtained when the substrate of transistor MSW is left floating.
  • the curve 48 corresponds to the evolution of the ratio obtained when the substrate B of the transistor MSW is permanently connected to the ground GND.
  • the curve 50 corresponds to the change in the ratio obtained when the bias circuit 45 is associated with the transistor MSW.
  • the bias circuit 45 makes it possible to obtain a sharp increase in the consumption gain compared with what was obtained in a conventional manner.
  • the consumption gain tends to decrease when the temperature increases.
  • the consumption gain increases with temperature.
  • the figure 10 represents a bias circuit 50 according to a fourth embodiment of the invention in which, compared with the circuit 45 of the figure 8 , an N-channel MOS transistor MSL has been added whose drain D 3 is connected to the drain D 1 of the transistor MD 1 and whose source S 3 is connected to the gate G 1 of the transistor MD 1 .
  • the circuit 50 also comprises a P-channel MOS MAC transistor whose drain D 4 is connected to the substrate B of the transistor MSW and whose source S 4 is connected to the gate G 1 of the transistor MD 1 .
  • the gates G 3 , G 4 of the transistors MSL and MAC receive the signal SLENB which is complementary to the signal SLEN.
  • the signal SLEN is in the low state, for example at 0 V and the signal SLENB is in the high state, for example at VDD.
  • the MAC transistor is off and the MSL transistor is on.
  • the transistor MD 2 is passing and diode mounted.
  • the circuit 50 is then identical to the circuit 45. Its operation therefore corresponds to what has been described previously.
  • the signal SLEN is in the high state and the signal SLENB is in the low state.
  • the transistors MD 2 and MSL are then blocked.
  • the MAC transistor is on and substantially equivalent to a closed switch.
  • the gate G 1 of the transistor MD 1 is therefore connected to the substrate B of the transistor MSW.
  • the transistor MD 1 then functions as a current limiter and is equivalent to a diode whose anode is connected to the substrate B and the cathode to the gate G.
  • the voltages Vp and V SL are at VDD.
  • the transistor MD 1 makes it possible to bring V B to a value greater than 0 V while ensuring that the potential V B remains below 0.6 V so that there is no direct bias of the substrate junction -Source of the MSW transistor.
  • the fact of setting the voltage V P to VDD initially raises the potential V B by capacitive coupling, the potential V B being maintained thereafter at a positive value via the transistor MD 1 .
  • An MSW transistor is thus obtained, the substrate of which is positively biased in the active state. This makes it possible to reduce the threshold voltage of the transistor and to improve the conduction of the transistor MSW in the active state. For the same current to be driven, it is then possible to reduce the dimensions of the transistor MSW with respect to a MOS transistor whose substrate would be kept grounded in the active state. The use of a MSW transistor of reduced dimensions makes it possible to reduce the leakage currents in the inactive state.
  • the circuit 50 makes it possible to reduce the area occupied by the transistor MSW by approximately 15%.
  • the circuit 50 makes it possible to obtain an MSW transistor with two dynamically modulated threshold voltages, a first low threshold voltage in the active state (the substrate B being positively biased) providing better conduction and a second high threshold voltage in the inactive state (the substrate being negatively biased) to reduce the leakage current.
  • the figure 11 represents a sixth embodiment of the bias circuit 55 according to the invention used to reduce the leakage currents of several MSW power transistors.
  • the power transistors MSW are divided into groups of power transistors GT i , i being an integer between 1 and n, each group GT i being associated with an electronic circuit BL i constituted, for example, of fast switching transistors.
  • the gates of the transistors MSW of each group of transistors GT i are connected to a partial polarization circuit PH i .
  • Each circuit PH i comprises the MOS transistors MD 1 , MD 2 , MSL, MAC, and the capacitors C 1 , C 2 of the circuit 50.
  • Each partial circuit PH i is connected to a first line 56 connected to the voltage source SP, not shown, and at a second line 58 connected to the voltage source SL, not shown.
  • Unique voltage sources SP and SL are therefore connected to each circuit PH i .
  • the surface increase due to the use of the polarization circuit according to the invention is thus reduced.
  • a transistor MSW in order to avoid a degradation of the transistor MSW, for example by breakdown of the oxide layer due to a potential difference between the drain and the gate of the transistor MSW greater than the supply voltage, it is possible to use a transistor MSW with a thick gate oxide, suitable for operation at high supply voltages.
  • a thick gate oxide transistor is, for example, of the GO2 type, the thickness of the gate oxide being approximately 2.7 nm, the other transistors of the circuit having an oxide thickness of the order 1.5 nm.
  • the voltage source SP can provide a signal other than rectangular. It can be a constant signal at 0 V periodically comprising triangular pulses.
  • the present invention has been described for the biasing of the substrate of an N-channel MOS transistor.
  • the present invention can be applied to the polarization of the substrate of a P-channel MOS transistor whose source is connected. to a source of a high reference potential, for example VDD.
  • the transistor substrate is put, in the inactive state, at a potential greater than the potential of the source by varying V P between 0 V (pulses of short durations) and VDD.
  • the potential of the gate can be brought to a potential greater than the potential of the source in the inactive state.
  • the potential of the substrate can be brought to a potential lower than the potential of the source in the active state.

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Description

Domaine de l'inventionField of the invention

La présente invention concerne un dispositif et un procédé de polarisation du substrat d'un transistor à effet de champ à semiconducteur métal-oxyde, ou transistors MOS.The present invention relates to a device and a method for biasing the substrate of a metal oxide semiconductor field effect transistor, or MOS transistors.

Exposé de l'art antérieurPresentation of the prior art

De façon théorique, lorsque la tension entre la grille et la source d'un transistor MOS à canal N est supérieure à une tension de seuil, un courant est susceptible de s'écouler entre le drain et la source du transistor en fonction de la tension drain-source appliquée. Le transistor est alors passant ou dit à l'état actif. Lorsque la tension grille-source est inférieure à la tension de seuil, le transistor est bloqué ou dit à l'état inactif et est équivalent à un interrupteur ouvert. Toutefois, en pratique, on observe à l'état inactif le passage d'un courant, appelé courant de fuite, entre le drain et la source du transistor MOS.In theory, when the voltage between the gate and the source of an N-channel MOS transistor is greater than a threshold voltage, a current is likely to flow between the drain and the source of the transistor as a function of the voltage. drain-source applied. The transistor is then conducting or said in the active state. When the gate-source voltage is lower than the threshold voltage, the transistor is blocked or said in the idle state and is equivalent to an open switch. However, in practice, there is observed in the inactive state the passage of a current, called leakage current, between the drain and the source of the MOS transistor.

Pour certaines applications, on souhaite obtenir des circuits électroniques dont la consommation est la plus faible possible. Il s'agit par exemple des téléphones portables, des consoles de jeu portables, etc., qui sont alimentées par des batteries. Il est alors nécessaire de réduire les courants de fuite des transistors de tels circuits électroniques pour diminuer la consommation du circuit électronique à l'état inactif.For some applications, it is desired to obtain electronic circuits whose consumption is the lowest possible. This is for example mobile phones, portable game consoles, etc., which are powered by batteries. It is then necessary to reduce the currents of leakage of the transistors of such electronic circuits to reduce the consumption of the electronic circuit in the inactive state.

Plusieurs facteurs influent sur l'amplitude du courant de fuite d'un transistor à l'état inactif. En particulier, pour un transistor MOS à canal N, le courant de fuite est d'autant plus important que la tension de seuil du transistor est faible, que la tension entre le substrat (en anglais body ou bulk) et la source du transistor est élevée ou que la tension entre la grille et la source du transistor est élevée.Several factors influence the magnitude of the leakage current of a transistor in the inactive state. In particular, for an N-channel MOS transistor, the leakage current is all the more important as the threshold voltage of the transistor is low, the voltage between the substrate (in English body or bulk) and the source of the transistor is high or that the voltage between the gate and the source of the transistor is high.

Un procédé classique de réduction du courant de fuite d'un transistor MOS à canal N dont la source est reliée à la masse consiste à polariser le substrat du transistor MOS à canal N à un potentiel inférieur au potentiel de la source. Pour un transistor MOS à canal P dont la source reçoit une tension d'alimentation, un tel procédé consiste à polariser le substrat du transistor à un potentiel supérieur au potentiel de la source. Un tel procédé est appelé procédé de polarisation inverse du substrat (en anglais reverse bulk biasing).A conventional method of reducing the leakage current of an N-channel MOS transistor whose source is connected to ground is to bias the substrate of the N-channel MOS transistor to a potential lower than the potential of the source. For a P-channel MOS transistor whose source receives a supply voltage, such a method consists of biasing the transistor substrate to a potential greater than the potential of the source. Such a process is called reverse bulk biasing (reverse bulk biasing).

Le principal inconvénient d'un tel procédé est que la polarisation du substrat du transistor est généralement réalisée par une source de tension connectée, à l'état inactif, au substrat du transistor. La réalisation d'une telle source de tension peut être relativement complexe. En outre, le fonctionnement d'une telle source de tension se traduit par une consommation supplémentaire qui limite la diminution de la consommation totale due à la réduction du courant de fuite du transistor.The main drawback of such a method is that the polarization of the transistor substrate is generally performed by a voltage source connected, in the inactive state, to the transistor substrate. The realization of such a voltage source can be relatively complex. In addition, the operation of such a voltage source results in additional consumption which limits the decrease in total consumption due to the reduction of the leakage current of the transistor.

Le brevet US 4 491 746 décrit un dispositif de polarisation d'une couche semiconductrice d'un circuit intégré.The patent US 4,491,746 discloses a device for biasing a semiconductor layer of an integrated circuit.

Résumé de l'inventionSummary of the invention

La présente invention vise à pallier tout ou partie des inconvénients des dispositifs et procédés connus de polarisation du substrat d'un transistor MOS.The present invention aims to overcome all or part of the disadvantages of known devices and methods for biasing the substrate of a MOS transistor.

La présente invention vise plus particulièrement un dispositif de polarisation du substrat d'un transistor MOS qui a une consommation propre réduite.The present invention more specifically relates to a device for biasing the substrate of a MOS transistor which has a reduced power consumption.

Selon un autre objet de l'invention, le dispositif de polarisation a une structure relativement simple et peut être réalisé à coût réduit.According to another object of the invention, the polarization device has a relatively simple structure and can be realized at reduced cost.

La présente invention vise également plus particulièrement un procédé de polarisation du substrat d'un transistor MOS dont la mise en oeuvre entraîne une consommation supplémentaire réduite.The present invention also aims more particularly at a method of polarizing the substrate of a MOS transistor whose implementation results in a reduced additional consumption.

Pour atteindre tout ou partie de ces objets, la présente invention prévoit un circuit de polarisation du substrat d'un transistor MOS, le substrat du transistor MOS étant entouré d'un caisson assurant une isolation électrique du substrat. Le circuit comprend un élément capacitif reliant le substrat du transistor MOS à une source d'une tension alternative à une première valeur pendant une première durée et à une seconde valeur pendant une seconde durée inférieure à la moitié de la première durée.To achieve all or part of these objects, the present invention provides a polarization circuit of the substrate of a MOS transistor, the substrate of the MOS transistor being surrounded by a box providing electrical insulation of the substrate. The circuit comprises a capacitive element connecting the substrate of the MOS transistor to a source of an alternating voltage at a first value for a first duration and at a second value for a second duration less than half of the first duration.

Selon un exemple de réalisation de la présente invention, l'élément capacitif comprend une électrode reliée directement au substrat.According to an exemplary embodiment of the present invention, the capacitive element comprises an electrode directly connected to the substrate.

Selon un exemple de réalisation de la présente invention, la source est adaptée à fournir la tension alternative à la première valeur pendant la première durée et à la seconde valeur pendant la seconde durée inférieure à 1/10 de la première durée.According to an exemplary embodiment of the present invention, the source is adapted to supply the AC voltage to the first value during the first duration and to the second value during the second duration less than 1/10 of the first duration.

Selon un exemple de réalisation de la présente invention, le transistor MOS est un transistor à canal N, la seconde valeur étant la tension nulle et la première valeur étant supérieure à la chute de tension en direct de la jonction substrat-source du transistor MOS.According to an exemplary embodiment of the present invention, the MOS transistor is an N-channel transistor, the second value being the zero voltage and the first value being greater than the direct voltage drop of the substrate-source junction of the MOS transistor.

Selon un exemple de réalisation de la présente invention, le circuit comprend un moyen adapté à relier le substrat et la grille du transistor MOS lorsque le transistor MOS est à l'état inactif.According to an exemplary embodiment of the present invention, the circuit comprises means adapted to connect the substrate and the gate of the MOS transistor when the MOS transistor is in the inactive state.

Selon un exemple de réalisation de la présente invention, le circuit comprend un transistor MOS supplémentaire dont les bornes principales relient le substrat à la grille du transistor MOS et un moyen adapté à relier la grille du transistor supplémentaire à la grille du transistor MOS lorsque le transistor MOS est à l'état inactif.According to an exemplary embodiment of the present invention, the circuit comprises an additional MOS transistor of which the main terminals connect the substrate to the gate of the MOS transistor and means adapted to connect the gate of the additional transistor to the gate of the MOS transistor when the MOS transistor is in the inactive state.

Selon un exemple de réalisation de la présente invention, le moyen est adapté à relier la grille du transistor MOS supplémentaire au substrat du transistor MOS lorsque le transistor MOS est à l'état actif.According to an exemplary embodiment of the present invention, the means is adapted to connect the gate of the additional MOS transistor to the substrate of the MOS transistor when the MOS transistor is in the active state.

Selon un exemple de réalisation de la présente invention, le transistor MOS est formé au niveau d'un support de type SOI, GeOI ou SON.According to an exemplary embodiment of the present invention, the MOS transistor is formed at a support of the SOI, GeOI or SON type.

Selon un exemple de réalisation de la présente invention, le transistor MOS comprend une première borne principale reliée à une borne d'un circuit électronique et une seconde borne principale reliée à une source d'un potentiel de référence, l'ensemble constitué par le transistor MOS, l'élément capacitif et la source de la tension alternative formant une pompe des charges du substrat du transistor MOS, le transistor MOS jouant par ailleurs le rôle d'interrupteur pour le circuit électronique.According to an exemplary embodiment of the present invention, the MOS transistor comprises a first main terminal connected to a terminal of an electronic circuit and a second main terminal connected to a source of a reference potential, the assembly consisting of the transistor MOS, the capacitive element and the source of the AC voltage forming a charge pump of the substrate of the MOS transistor, the MOS transistor also acting as a switch for the electronic circuit.

La présente invention prévoit également un procédé de polarisation du substrat d'un transistor MOS, le substrat du transistor MOS étant entouré d'un caisson assurant une isolation électrique du substrat. Le procédé consiste à relier le substrat du transistor MOS à une source d'une tension alternative par un élément capacitif, la tension alternative étant à une première valeur pendant une première durée et à une seconde valeur pendant une seconde durée inférieure à la moitié de la première durée.The present invention also provides a method for polarizing the substrate of a MOS transistor, the substrate of the MOS transistor being surrounded by a box providing electrical insulation of the substrate. The method consists of connecting the substrate of the MOS transistor to a source of an alternating voltage by a capacitive element, the alternating voltage being at a first value for a first duration and at a second value for a second duration less than half the time. first duration.

Selon un exemple de réalisation de la présente invention, la seconde durée est inférieure à 1/10 de la première durée.According to an exemplary embodiment of the present invention, the second duration is less than 1/10 of the first duration.

Selon un exemple de réalisation de la présente invention, le procédé consiste, en outre, à prévoir un transistor MOS supplémentaire dont les bornes principales relient le substrat à la grille du transistor MOS et à relier la grille du transistor supplémentaire à la grille du transistor MOS lorsque le transistor MOS est à l'état inactif et à relier la grille du transistor MOS supplémentaire au substrat du transistor MOS lorsque le transistor MOS est à l'état actif.According to an exemplary embodiment of the present invention, the method further comprises providing an additional MOS transistor whose main terminals connect the substrate to the gate of the MOS transistor and to connect the gate of the additional transistor to the gate of the MOS transistor when the MOS transistor is in the inactive state and to connect the gate of the additional MOS transistor to the substrate of the MOS transistor when the MOS transistor is at the active state.

Brève description des dessinsBrief description of the drawings

Ces objets, caractéristiques et avantages, ainsi que d'autres de la présente invention seront exposés en détail dans la description suivante d'exemples de réalisation particuliers faite à titre non-limitatif en relation avec les figures jointes parmi lesquelles :

  • la figure 1 est une coupe schématique d'un transistor MOS à canal N réalisé au niveau d'un substrat de type SOI ;
  • la figure 2 est un premier exemple de réalisation d'un dispositif de polarisation du substrat d'un transistor MOS selon l'invention ;
  • la figure 3 représente des courbes d'évolution de potentiels lors de la mise en oeuvre du procédé de polarisation selon l'invention ;
  • la figure 4 représente l'évolution du courant de fuite du circuit de la figure 2 en fonction du rapport cyclique d'une tension du circuit ;
  • la figure 5 illustre le principe de détermination de la période d'une tension utilisée par le circuit de la figure 2 ;
  • la figure 6 représente un deuxième exemple de réalisation du dispositif de polarisation selon l'invention ;
  • la figure 7 est un schéma d'un circuit électrique équivalent au dispositif représenté en figure 6 ;
  • la figure 8 représente un troisième exemple de réalisation du dispositif de polarisation selon l'invention ;
  • la figure 9 représente trois courbes d'évolution du gain en consommation pour trois procédés de réduction des courants de fuite ; et
  • les figures 10 et 11 représentent respectivement des quatrième et cinquième exemples de réalisation du dispositif de polarisation selon l'invention.
These and other objects, features, and advantages of the present invention will be set forth in detail in the following description of particular embodiments given in a non-limiting manner in relation to the attached figures among which:
  • the figure 1 is a schematic section of an N-channel MOS transistor made at a SOI substrate;
  • the figure 2 is a first embodiment of a device for polarizing the substrate of a MOS transistor according to the invention;
  • the figure 3 represents curves of evolution of potentials during the implementation of the polarization method according to the invention;
  • the figure 4 represents the evolution of the leakage current of the circuit of the figure 2 according to the duty cycle of a circuit voltage;
  • the figure 5 illustrates the principle of determining the period of a voltage used by the circuit of the figure 2 ;
  • the figure 6 represents a second embodiment of the polarization device according to the invention;
  • the figure 7 is a diagram of an electrical circuit equivalent to the device represented in figure 6 ;
  • the figure 8 represents a third embodiment of the polarization device according to the invention;
  • the figure 9 represents three curves of evolution of the gain in consumption for three methods of reduction of the currents of leakage; and
  • the Figures 10 and 11 respectively represent fourth and fifth exemplary embodiments of the polarization device according to the invention.

Description détailléedetailed description

Par souci de clarté, de mêmes éléments ont été désignés par de mêmes références aux différentes figures et, de plus, comme cela est habituel dans la représentation des circuits intégrés, les diverses figures ne sont pas tracées à l'échelle. Dans la suite de la description, les potentiels de noeuds d'un circuit électronique sont mesurés par rapport à la masse du circuit électronique, le potentiel de la masse étant pris égal à 0 V.For the sake of clarity, the same elements have been designated by the same references in the various figures and, moreover, as is customary in the representation of the integrated circuits, the various figures are not drawn to scale. In the remainder of the description, the node potentials of an electronic circuit are measured with respect to the mass of the electronic circuit, the potential of the mass being taken equal to 0 V.

La présente invention vise à modifier le potentiel du substrat d'un transistor MOS à l'état inactif pour diminuer le courant de fuite du transistor, la modification du potentiel du substrat étant obtenue par un procédé qui entraîne seulement une très faible consommation supplémentaire. La présente invention s'applique à un transistor pour lequel le potentiel du substrat est susceptible d'être modifié. La présente invention peut donc s'appliquer à un transistor MOS à substrat isolé, par exemple un transistor MOS réalisé au niveau d'un substrat de type silicium sur isolant ou SOI (Silicon On Insulator), d'un substrat de type germanium sur isolant ou GeOI (Germanium On Insulator) ou d'un substrat de silicium à film ultra-mince ou SON (Silicon On Nothing). Le substrat du transistor est au moins partiellement entouré d'un caisson d'un matériau isolant assurant une isolation électrique du substrat. La présente invention peut également s'appliquer à un transistor MOS réalisé au niveau d'une tranche de silicium pour lequel le substrat du transistor est électriquement isolé du reste de la tranche, par exemple par l'intermédiaire d'un caisson ayant un type de dopant adapté entourant le transistor. Dans ce dernier cas, la polarisation du caisson est adaptée à assurer l'isolation du substrat du transistor, c'est-à-dire que le caisson est polarisé en inverse vis-à-vis des autres jonctions adjacentes pour assurer une isolation électrique du substrat du transistor.The present invention aims to modify the potential of the substrate of a MOS transistor in the inactive state to reduce the leakage current of the transistor, the modification of the potential of the substrate being obtained by a process which results in only a very low additional consumption. The present invention applies to a transistor for which the potential of the substrate is likely to be modified. The present invention can therefore be applied to an insulated substrate MOS transistor, for example a MOS transistor produced at a silicon on insulator or SOI (Silicon On Insulator) substrate, a germanium on insulator substrate. or GeOI (Germanium On Insulator) or an ultra-thin film silicon substrate or SON (Silicon On Nothing). The transistor substrate is at least partially surrounded by a box of an insulating material providing electrical insulation of the substrate. The present invention can also be applied to a MOS transistor formed at a silicon wafer for which the transistor substrate is electrically isolated from the remainder of the wafer, for example by means of a box having a type of adapted dopant surrounding the transistor. In the latter case, the polarization of the box is adapted to ensure the isolation of the transistor substrate, that is to say that the box is polarized in reverse vis-à-vis other adjacent junctions to provide electrical isolation of the transistor substrate.

Par rapport à la technologie pour laquelle les substrats des transistors MOS ne sont pas flottants, l'avantage de la technologie SOI partiellement désertée ou PD-SOI, en termes de performances, est lié à la modulation dynamique de la tension de seuil des transistors. Cette modulation dynamique est due à la variation du potentiel du substrat flottant des transistors. L'inconvénient d'un procédé classique de réduction des courants de fuite d'un transistor MOS est que le substrat n'est plus laissé flottant. A l'état actif, on perd l'avantage de la modulation dynamique de la tension de seuil du transistor. L'intérêt de l'invention est de pouvoir contrôler la polarisation du substrat en mode inactif tout en laissant la possibilité de laisser le substrat flottant en mode actif. Pour cela, le potentiel du substrat flottant du transistor est contrôlé par la modulation de sa charge.Compared to the technology for which the substrates of the MOS transistors are not floating, the advantage of the partially deserted SOI technology or PD-SOI, in terms of performance, is related to the dynamic modulation of the threshold voltage of the transistors. This dynamic modulation is due to the variation of the potential of the floating substrate of the transistors. The disadvantage of a conventional method of reducing the leakage currents of a MOS transistor is that the substrate is no longer floating. In the active state, the advantage of the dynamic modulation of the threshold voltage of the transistor is lost. The advantage of the invention is to control the polarization of the substrate in idle mode while leaving the possibility of leaving the floating substrate in active mode. For this, the potential of the floating substrate of the transistor is controlled by the modulation of its load.

La figure 1 représente, de façon très schématique, une coupe d'un transistor MOS à canal N réalisé au niveau d'un substrat de type SOI. Un support 10, par exemple une tranche de silicium dopée de type P est recouverte d'une couche isolante 12, par exemple de l'oxyde de silicium. Des zones actives 13 de silicium monocristallin séparées par des régions isolantes 14, 16 sont réalisées sur la couche isolante 12. Le transistor MOS est réalisé au niveau de l'une des zones actives 13 et comprend deux régions 18, 20 dopées de type N séparées par une région 22 dopée de type P. Les régions 18, 20 correspondent au drain et à la source du transistor MOS et la région 22 correspond au substrat du transistor MOS. La région 22 est recouverte d'une couche isolante 24, correspondant à l'oxyde de grille, elle-même recouverte d'une région conductrice 26, correspondant à la grille du transistor. Un tel transistor est dit réalisé selon une technologie SOI Partiellement Déserté, ou SOI-PD, dans la mesure où le substrat 22 du transistor est laissé flottant.The figure 1 represents, very schematically, a section of an N-channel MOS transistor produced at a SOI-type substrate. A support 10, for example a p-type doped silicon wafer, is covered with an insulating layer 12, for example silicon oxide. Active areas 13 of monocrystalline silicon separated by insulating regions 14, 16 are formed on the insulating layer 12. The MOS transistor is formed at one of the active areas 13 and comprises two separate regions 18, 20 doped N-type by a p-type doped region 22. The regions 18, 20 correspond to the drain and the source of the MOS transistor and the region 22 corresponds to the substrate of the MOS transistor. The region 22 is covered with an insulating layer 24, corresponding to the gate oxide, itself covered with a conductive region 26, corresponding to the gate of the transistor. Such a transistor is said to be made according to SOI technology Partially deserted, or SOI-PD, insofar as the substrate 22 of the transistor is left floating.

La présente invention va être maintenant décrite dans le cadre d'une application particulière pour la réduction du courant de fuite d'un transistor MOS de puissance utilisé comme interrupteur d'un circuit électronique. Un transistor MOS de puissance est un transistor MOS susceptible d'accepter des courants élevés à l'état actif et dont le courant de fuite à l'état inactif est faible par rapport aux courants de fuite des transistors MOS classiquement utilisés dans les circuits électroniques et dits à commutation rapide. Un transistor MOS de puissance peut, de façon classique, être utilisé comme interrupteur pour réduire la consommation d'un circuit électronique à l'état inactif. Pour ce faire, on dispose généralement le transistor MOS de puissance entre le circuit électronique et la masse. Le transistor MOS de puissance est bloqué lorsque le circuit électronique est à l'état inactif (ou en stand-by) pour limiter les pertes électriques totales. La présente invention permet de polariser le substrat du transistor MOS de puissance pour réduire le courant de fuite du transistor utilisé comme interrupteur et donc de réduire encore davantage la consommation du circuit électronique à l'état inactif. Toutefois, il est clair que la présente invention peut s'appliquer de façon générale à n'importe quel type de transistor MOS dont on veut réduire le courant de fuite à l'état inactif.The present invention will now be described in the context of a particular application for reducing the leakage current of a power MOS transistor used as a switch of an electronic circuit. A power MOS transistor is a MOS transistor capable of accepting high currents in the active state and whose leakage current in the inactive state is low compared to the leakage currents of the MOS transistors conventionally used in the electronic circuits and so-called fast switching. A power MOS transistor can conventionally be used as a switch to reduce the consumption of an electronic circuit in the inactive state. To do this, the power MOS transistor is generally available between the electronic circuit and the ground. The power MOS transistor is blocked when the electronic circuit is in the inactive state (or in stand-by) to limit the total electrical losses. The present invention makes it possible to polarize the substrate of the power MOS transistor in order to reduce the leakage current of the transistor used as a switch and thus to further reduce the consumption of the electronic circuit in the inactive state. However, it is clear that the present invention can generally be applied to any type of MOS transistor whose inactive leakage current is to be reduced.

La figure 2 représente un premier exemple de réalisation d'un circuit 30 de polarisation du substrat d'un transistor MOS de puissance MSW, à canal N, disposé entre une borne de sortie O d'un circuit électronique CL et une source d'un potentiel de référence GND, par exemple la masse. Le circuit électronique CL comprend, par exemple, des transistors MOS à tension de seuil faible qui ont des vitesses de commutation supérieures à celle du transistor MOS de puissance MSW. Le transistor MSW comprend une source S, un drain D, un substrat B et une grille G. Le transistor MSW est, par exemple, réalisé au niveau d'un substrat de type SOI et a la structure représentée en figure 1. La source S est reliée à la masse GND et le drain D est relié à la borne de sortie O. La grille G est reliée à une borne d'une source de tension SL dont l'autre borne est reliée à la masse GND. On appelle VSL la tension aux bornes de la source de tension SL.The figure 2 represents a first exemplary embodiment of a substrate biasing circuit 30 of an N-channel power MOS transistor MSW disposed between an output terminal O of an electronic circuit CL and a source of a reference potential. GND, for example mass. The electronic circuit CL comprises, for example, low threshold voltage MOS transistors which have switching speeds higher than that of the power MOS transistor MSW. The transistor MSW comprises a source S, a drain D, a substrate B and a gate G. The transistor MSW is, for example, made at a SOI type substrate and has the structure represented in FIG. figure 1 . Source S is connected to ground GND and drain D is connected to the output terminal O. The gate G is connected to a terminal of a voltage source SL whose other terminal is connected to ground GND. V SL is called the terminal voltage of the voltage source SL.

Selon le premier exemple de réalisation, le circuit 30 comprend un condensateur C1 dont une électrode est reliée directement au substrat B et dont l'autre électrode est reliée à une borne d'une source de tension SP. L'autre borne de la source de tension SP est reliée à la masse GND. On appelle VP la tension aux bornes de la source de tension SP. A titre d'exemple, le condensateur C1 comprend deux électrodes métalliques séparées par un matériau diélectrique. Dans ce cas, par rapport à la structure représentée en figure 1, la région 22 comprend une extension, non représentée, permettant la réalisation d'un plot de contact afin de relier le substrat du transistor à une électrode du condensateur C1. Selon un autre exemple, le condensateur C1 comprend deux électrodes de silicium polycristallin, ou une première électrode métallique et une seconde électrode de silicium polycristallin. Par rapport à la structure représentée en figure 1, la région 22 peut comprendre une extension, non représentée, directement en contact avec la seconde électrode. Selon un autre exemple, le condensateur C1 comprend une électrode métallique ou en silicium polycristallin et une électrode correspondant à une région de silicium dopée, qui est, par exemple, au contact du substrat. Les sources de tension SP et SL peuvent correspondre à tout type de circuit électronique adapté à fournir les tensions VP et VSL recherchées. En particulier, les tensions VP et VSL peuvent être obtenues à partir d'une source de tension unique.According to the first exemplary embodiment, the circuit 30 comprises a capacitor C 1 , one electrode of which is directly connected to the substrate B and the other electrode of which is connected to a terminal of a voltage source SP. The other terminal of the voltage source SP is connected to GND ground. The voltage at the terminals of the voltage source SP is called V P. By way of example, the capacitor C 1 comprises two metal electrodes separated by a dielectric material. In this case, compared to the structure represented in figure 1 , the region 22 comprises an extension, not shown, for producing a contact pad for connecting the transistor substrate to an electrode of the capacitor C 1 . In another example, the capacitor C 1 comprises two polycrystalline silicon electrodes, or a first metal electrode and a second polycrystalline silicon electrode. With respect to the structure represented in figure 1 the region 22 may comprise an extension, not shown, directly in contact with the second electrode. According to another example, the capacitor C 1 comprises a metal electrode or polycrystalline silicon and an electrode corresponding to a doped silicon region, which is, for example, in contact with the substrate. The voltage sources SP and SL may correspond to any type of electronic circuit adapted to provide the voltages V P and V SL sought. In particular, the voltages V P and V SL can be obtained from a single voltage source.

A l'état inactif, la tension VP correspond à une tension rectangulaire périodique variant, par exemple, entre la tension nulle et la tension d'alimentation VDD. La période de la tension VP est par exemple de l'ordre de 100 ms. Le rapport cyclique α de la tension VP correspond au rapport entre la durée pendant laquelle la tension VP est égale à VDD et la durée pendant laquelle la tension VP est égale à 0 V. Selon le premier exemple de réalisation, le rapport cyclique α est inférieur à 1, par exemple inférieur à 1/2, de préférence inférieur à 1/10, voire inférieur à 1/100, par exemple de l'ordre de 1/500 pour un circuit réalisé par une technologie SOI. A titre d'exemple, pour le noeud technologique 130 nm SOI-PD, le rapport cyclique α peut être inférieur à 1/500.In the inactive state, the voltage V P corresponds to a periodic rectangular voltage varying, for example, between the zero voltage and the supply voltage VDD. The period of the voltage V P is for example of the order of 100 ms. The duty cycle α of the voltage V P corresponds to the ratio between the duration during which the voltage V P is equal to VDD and the duration during which the voltage V P is equal to 0 V. According to the first exemplary embodiment, the duty ratio α is less than 1, for example less than 1/2, preferably less than 1/10, or even less than 1/100 , for example of the order of 1/500 for a circuit realized by an SOI technology. By way of example, for the 130 nm SOI-PD technology node, the duty cycle α may be less than 1/500.

La figure 3 représente une courbe d'évolution 32 du potentiel du substrat B, appelé VB, du transistor MSW à l'état inactif, une courbe d'évolution 33 qui correspond à un agrandissement de la courbe d'évolution 32 du potentiel VB pour les premières périodes du signal VP lors de la mise à l'état inactif du transistor MSW et une courbe d'évolution 34 du signal VP. La courbe 32 est tracée à l'échelle. Par contre, les courbes 33 et 34 ne sont pas tracées à l'échelle.The figure 3 represents an evolution curve 32 of the potential of the substrate B, called V B , of the transistor MSW in the inactive state, an evolution curve 33 which corresponds to an enlargement of the evolution curve 32 of the potential V B for the first periods of the signal V P during the inactive state of the transistor MSW and an evolution curve 34 of the signal V P. Curve 32 is drawn to scale. On the other hand, curves 33 and 34 are not drawn to scale.

Selon le premier exemple de réalisation, le circuit 30 permet, à l'état inactif, de diminuer globalement le potentiel VB du substrat B du transistor MSW à un potentiel négatif de façon à diminuer le courant de fuite du transistor MSW. La présente invention utilise le fait que pour un transistor MOS dont le substrat B n'est pas directement relié à une source d'un potentiel constant, le potentiel VB dépend de la quantité de charge QB stockée au niveau du substrat B.According to the first exemplary embodiment, the circuit 30 makes it possible, in the inactive state, to reduce overall the potential V B of the substrate B of the transistor MSW to a negative potential so as to reduce the leakage current of the transistor MSW. The present invention uses the fact that for a MOS transistor whose substrate B is not directly connected to a source of a constant potential, the potential V B depends on the amount of charge Q B stored at the level of the substrate B.

Pour le circuit 30 représenté en figure 2, le potentiel VB est obtenu, à un instant donné, à partir de la relation suivante : V B = Q B + C D ⁢ V D + C S ⁢ V S + C G ⁢ V G + C 1 ⁢ V P / C T

Figure imgb0001

où VD, VS et VG correspondent respectivement au potentiel du drain D, de la source S et de la grille G, où CD, CS et CG correspondent respectivement à la capacité de drain, de source et de grille et où CT correspond à la somme des capacités CG, CS, CD et C1.For the circuit 30 represented in figure 2 , the potential V B is obtained, at a given moment, from the following relation: V B = Q B + VS D ⁢ V D + VS S ⁢ V S + VS BOY WUT ⁢ V BOY WUT + VS 1 ⁢ V P / VS T
Figure imgb0001
where V D , V S and V G respectively correspond to the potential of the drain D, the source S and the gate G, where C D , C S and C G respectively correspond to the drain, source and gate capacity, and where C T is the sum of the capacitances C G , C S , C D and C 1 .

La quantité de charge QB varie en fonction du taux de charge et du taux de décharge du substrat B à un instant donné. Le taux de charge du substrat B est représentatif des phénomènes entraînant la génération de porteurs (par exemple la formation d'un courant tunnel, des phénomènes d'ionisation par impact, etc.), c'est-à-dire entraînant une augmentation de QB. Le taux de décharge du substrat B est représentatif des phénomènes entraînant la recombinaison de porteurs (par exemple la formation d'un courant de jonction drain-substrat ou source-substrat), c'est-à-dire entraînant une diminution de QB. De façon générale, les phénomènes entraînant la recombinaison de porteurs sont beaucoup plus rapides que les phénomènes entraînant la génération de porteurs d'un facteur pouvant varier de 100 à 1000.The amount of charge Q B varies as a function of the charge rate and the discharge rate of the substrate B at a given instant. The charge rate of the substrate B is representative of the phenomena leading to the generation of carriers (for example the formation of a tunnel current, impact ionization phenomena, etc.), that is to say causing an increase in Q B. The rate of discharge of the substrate B is representative of the phenomena leading to carrier recombination (for example the formation of a drain-substrate or source-substrate junction current), that is to say causing a decrease in Q B. In general, the phenomena leading to the recombination of carriers are much faster than the phenomena leading to the generation of carriers with a factor that can vary from 100 to 1000.

A l'équilibre statique, la quantité de charges QB est sensiblement constante et fixée par les potentiels VB, VD, VS, VG et la tension Vp. Lorsqu'on modifie les valeurs des potentiels VD, VS, VG, la charge QB évolue, pendant une phase de transition plus ou moins longue, vers un nouvel équilibre statique. Pendant cette phase de transition, le transistor MSW se trouve à un état intermédiaire entre deux états d'équilibre.At static equilibrium, the quantity of charges Q B is substantially constant and fixed by the potentials V B , V D , V S , V G and the voltage Vp. When changing the values of potential V D, V S, V G, the charge Q B changes, for a longer or shorter transition phase, to a new static equilibrium. During this transition phase, the MSW transistor is in an intermediate state between two equilibrium states.

La présente invention consiste à commander la quantité de charge QB en faisant varier la tension VP. Plus précisément, la présente invention utilise le fait que la durée nécessaire à la charge du substrat est beaucoup plus longue que la durée nécessaire à la décharge du substrat de sorte qu'il suffit, pour commander la quantité de charge QB, de mettre la tension VP à VDD de façon périodique pendant une durée très brève. La majorité du temps, la tension VP est laissée à 0 V, la quantité de charge QB évoluant alors peu et fixant le potentiel VB à une valeur sensiblement constante et négative. De ce fait, sauf au niveau des impulsions de la tension VP, le potentiel VB est pratiquement en permanence constant et négatif.The present invention consists in controlling the amount of charge Q B by varying the voltage V P. More specifically, the present invention utilizes the fact that the time required for charging the substrate is much longer than the time required for the discharge of the substrate so that it is sufficient, to control the amount of charge Q B , to put the voltage V P to VDD periodically for a very short time. Most of the time, the voltage V P is left at 0 V, the amount of charge Q B evolving then little and setting the potential V B to a substantially constant and negative value. As a result, except for the pulses of the voltage V P , the potential V B is substantially permanently constant and negative.

A titre d'exemple, on suppose initialement que les potentiels VD, VS et VG sont nuls, que la tension VP est nulle et que le transistor MSW a atteint un état d'équilibre correspondant à une quantité de charge QB0 initiale. Lorsque la tension VP passe à VDD, le potentiel VB augmente en raison du couplage capacitif dû au condensateur C1 (portion ascendante 35 de la courbe 33). Toutefois, l'augmentation de VB par rapport à VS qui est à zéro tend à rendre passante la jonction entre le substrat B et la source S du transistor MSW. Des charges négatives sont alors injectées dans le substrat B ce qui entraîne la diminution de la quantité de charge QB de QB0 à QB1 en raison des phénomènes de recombinaison de porteurs.By way of example, it is initially assumed that the potentials V D , V S and V G are zero, that the voltage V P is zero and that the transistor MSW has reached a state of equilibrium corresponding to a quantity of charge Q B0 initial. When the voltage V P goes to VDD, the potential V B increases due to the capacitive coupling due to the capacitor C 1 (upward portion 35 of the curve 33). However, the increase of V B with respect to V S which is zero tends to make pass the junction between the substrate B and the source S of the MSW transistor. Negative charges are then injected into the substrate B, which causes the quantity of charge Q B to decrease from Q B0 to Q B1 because of the carrier recombination phenomena.

Lorsque la tension VP passe de VDD à 0 V, le potentiel VB diminue en raison du couplage capacitif dû au condensateur C1 (portion descendante 36 de la courbe 33). La jonction substrat-source du transistor MSW n'est alors plus passante de sorte que les phénomènes de recombinaison de porteurs tendent à s'arrêter. La charge QB devrait augmenter lentement de QB1 à QB0 en raison des phénomènes de génération de porteurs. Toutefois, ces phénomènes étant lents par rapport à la fréquence de commutation de VP, tout se passe comme si la quantité de charges restait constante et égale à QB1. Le potentiel VB se stabilise donc à la valeur correspondant à QB1 donnée par la relation (1) et varie peu avant le prochain passage de VP de 0 V à VDD (portion constante 37 de la courbe 33). Comme QB1 est inférieur à QB0, le potentiel VB a diminué. Ce phénomène se répète pour les premiers cycles de la tension VP de sorte que le potentiel VB diminue au niveau des portions constantes 37.When the voltage V P goes from VDD to 0 V, the potential V B decreases due to the capacitive coupling due to the capacitor C 1 (downward portion 36 of the curve 33). The substrate-source junction of the MSW transistor is no longer conducting so that the carrier recombination phenomena tend to stop. The charge Q B should increase slowly from Q B1 to Q B0 due to carrier generation phenomena. However, since these phenomena are slow with respect to the switching frequency of V P , everything happens as if the quantity of charges remained constant and equal to Q B1 . The potential V B thus stabilizes at the value corresponding to Q B1 given by the relation (1) and varies shortly before the next passage of V P from 0 V to VDD (constant portion 37 of the curve 33). Since Q B1 is less than Q B0 , the potential V B has decreased. This phenomenon is repeated for the first cycles of the voltage V P so that the potential V B decreases at the level of the constant portions 37.

Après plusieurs cycles successifs de la tension VP, le potentiel VB a suffisamment diminué de sorte que lorsque la tension VP passe de 0 V à VDD, le potentiel VB n'est pas élevé suffisamment pour rendre complètement passante la jonction substrat-source mais seulement légèrement passante pour compenser la génération de charges. La quantité de charge QB n'évolue alors sensiblement plus et le potentiel VB se maintient, lorsque VP est à 0 V, à une valeur négative par exemple entre -0,5 V à -1 V.After several successive cycles of the voltage V P , the potential V B has sufficiently decreased so that when the voltage V P goes from 0 V to VDD, the potential V B is not high enough to make the substrate junction completely passable. source but only slightly passing to compensate for the generation of charges. The quantity of charge Q B then increases substantially more and the potential V B is maintained, when V P is at 0 V, at a negative value for example between -0.5 V to -1 V.

L'ensemble constitué par la source de tension SP, le condensateur C1 et le transistor MSW se comporte donc comme une pompe de charges adaptée à diminuer la quantité de charge QB.The assembly consisting of the voltage source SP, the capacitor C 1 and the transistor MSW therefore behaves like a charge pump adapted to reduce the amount of charge Q B.

De façon générale, les valeurs entre lesquelles varie VP peuvent être différentes de 0 V et VDD. La seule condition est que la variation de VP entraîne par effet capacitif une variation du potentiel VB suffisante pour rendre passante la jonction substrat-source du transistor MSW, au moins au début du passage à l'état inactif.In general, the values between which V P varies can be different from 0 V and VDD. The only condition is that the variation of V P causes, by capacitive effect, a variation of the potential V B sufficient to make the substrate-source junction of the transistor MSW pass, at least at the beginning of the transition to the inactive state.

La figure 4 représente l'évolution du courant de fuite I1 du circuit 30 en fonction du rapport cyclique α. Pour déterminer le rapport cyclique α qui permet l'obtention du courant de fuite le plus faible, on peut procéder par essais successifs. Pour ce faire, on peut attribuer plusieurs valeurs de rapport cyclique à la tension VP, déterminer les courants de fuite correspondants et choisir le rapport cyclique qui donne le courant de fuite minimal. On peut également utiliser les logiciels de simulation utilisés en CAO (Conception Assistée par Ordinateur) tel que le simulateur de type SPICE (acronyme anglais pour Simulation Program with Integrated Circuit Emphasis), par exemple les simulateurs ELDO ou HSIM.The figure 4 represents the evolution of the leakage current I 1 of the circuit 30 as a function of the duty cycle α. To determine the cyclic ratio α which makes it possible to obtain the lowest leakage current, it is possible to proceed by successive tests. To do this, several duty cycle values can be assigned to the voltage V P , determine the corresponding leakage currents and choose the duty cycle that gives the minimum leakage current. One can also use simulation software used in CAD (Computer Aided Design) such as simulator type SPICE (acronym for Simulation Program with Integrated Circuit Emphasis), for example ELDO or HSIM simulators.

La période du signal VP est déterminée pour que la consommation dynamique du circuit 30 soit la plus faible. Une partie de la consommation dynamique est due à la commutation de la tension VP sur un front montant ou descendant. Pour réduire la consommation dynamique, la période du signal VP est choisie la plus grande possible pour limiter le nombre de commutations de la tension VP.The period of the signal V P is determined so that the dynamic consumption of the circuit 30 is the lowest. Part of the dynamic consumption is due to the switching of the voltage V P on a rising or falling edge. To reduce the dynamic consumption, the period of the signal V P is chosen as large as possible to limit the number of switching of the voltage V P.

La figure 5 représente l'évolution du potentiel VB en fonction du temps lorsqu'on applique un front descendant sur VP (passage d'une valeur haute à une valeur basse). L'échelle des abscisses est une échelle logarithmique. Par couplage capacitif, lorsque la tension VP diminue, on observe une diminution du potentiel VB qui se stabilise à une valeur basse. On détermine alors la durée T pendant laquelle VB reste sensiblement constant à la valeur basse avant d'augmenter. La période du signal VP peut correspondre à la durée T ainsi déterminée. On appelle F la fréquence du signal VP.The figure 5 represents the evolution of the potential V B as a function of time when a falling edge is applied to V P (transition from a high value to a low value). The abscissa scale is a logarithmic scale. By capacitive coupling, when the voltage V P decreases, there is a decrease in potential V B which stabilizes at a low value. The duration T during which V B remains substantially constant at the low value is then determined before increasing. The period of the signal V P may correspond to the duration T thus determined. The frequency of the signal V P is called F.

Lorsque le circuit 30 passe de l'état actif à l'état inactif (ou en stand-by), on peut, dans une phase initiale, accélérer la fréquence du signal VP par rapport à la fréquence F déterminée précédemment, afin de faire diminuer le potentiel VB du transistor MSW le plus rapidement possible. Ensuite, la fréquence du signal VP est remise à la fréquence F de façon à maintenir le potentiel VB à la valeur basse tout en réduisant la consommation dynamique du circuit 30.When the circuit 30 goes from the active state to the inactive (or stand-by) state, it is possible, in an initial phase, to accelerate the frequency of the signal V P with respect to the frequency F previously determined, in order to reduce the potential V B of the MSW transistor as quickly as possible. Then, the frequency of the signal V P is reset to the frequency F so as to maintain the potential V B at the low value while reducing the dynamic consumption of the circuit 30.

La figure 6 représente un deuxième exemple de réalisation d'un circuit de polarisation 40 selon l'invention. Le circuit 40 correspond au circuit 30 représenté en figure 2 dans lequel on a ajouté un transistor MOS MD1 à canal N, monté en diode, dont la grille G1 et le drain D1 sont reliés à la grille G du transistor MSW. La source S1 du transistor MD1 est reliée au substrat B du transistor MSW. Un condensateur C2 est prévu entre la grille G et la masse GND. Selon une variante du deuxième exemple de réalisation, le condensateur C2 n'est pas présent. A l'état inactif, la source de tension SL est à haute impédance et n'est pas représentée en figure 6. Le circuit 40 permet de mettre le substrat B à un potentiel négatif à l'état inactif, et, parallèlement, de mettre la grille G du transistor MSW à un potentiel négatif. En effet, le courant de fuite d'un transistor MOS à canal N est d'autant plus élevé que la tension entre la grille et la source est grande. On diminue ainsi encore davantage le courant de fuite du transistor MSW à l'état inactif.The figure 6 represents a second embodiment of a polarization circuit 40 according to the invention. The circuit 40 corresponds to the circuit 30 represented in figure 2 in which a diode-mounted N-channel transistor MOS MD 1 has been added whose gate G 1 and the drain D 1 are connected to the gate G of the transistor MSW. The source S 1 of the transistor MD 1 is connected to the substrate B of the transistor MSW. A capacitor C 2 is provided between the gate G and the ground GND. According to a variant of the second embodiment, the capacitor C 2 is not present. In the idle state, the voltage source SL is at high impedance and is not represented in figure 6 . The circuit 40 makes it possible to put the substrate B at a negative potential in the inactive state, and, in parallel, to set the gate G of the transistor MSW to a negative potential. Indeed, the leakage current of an N-channel MOS transistor is all the higher as the voltage between the gate and the source is large. This further reduces the leakage current of the transistor MSW to the inactive state.

La figure 7 représente un schéma électrique équivalent au circuit 40 représenté en figure 6 à l'état inactif. Le transistor MSW équivaut à une diode MSW' dont l'anode est connectée au substrat B et dont la cathode est connectée à la masse GND. Le transistor MD1 équivaut à une diode MD1' dont l'anode est connectée à la grille G et dont la cathode est connectée au substrat B. Selon un tel montage, le potentiel VG suit en moyenne le potentiel VB. Le condensateur C2, s'il est présent, permet de stabiliser le potentiel VG. La figure 7 correspond également au schéma d'une pompe de charge. Ceci signifie que le transistor MSW a deux fonctions : la première est celle d'interrupteur de puissance et la seconde est celle d'élément actif de la pompe de charge.The figure 7 represents a circuit diagram equivalent to the circuit 40 represented in figure 6 in the idle state. The MSW transistor is equivalent to a diode MSW 'whose anode is connected to the substrate B and whose cathode is connected to the ground GND. The transistor MD 1 is equivalent to a diode MD 1 'whose anode is connected to the gate G and whose cathode is connected to the substrate B. According to such an arrangement, the potential V G follows on average the potential V B. The capacitor C 2 , if present, stabilizes the potential V G. The figure 7 also corresponds to the diagram of a charge pump. This means that the MSW transistor has two functions: the first is that of the power switch and the second is that of the active element of the charge pump.

Selon une variante du circuit 40, le transistor MD1 peut être remplacé par une diode dont l'anode est connectée à la grille G et dont la cathode est connectée au substrat B.According to a variant of the circuit 40, the transistor MD 1 can be replaced by a diode whose anode is connected to the gate G and whose cathode is connected to the substrate B.

La figure 8 représente un circuit de polarisation 45 selon un troisième exemple de réalisation de l'invention dans lequel, par rapport au circuit 40 représenté en figure 6, on a ajouté, entre le substrat B et la masse GND, un transistor MOS MD2 à canal P dont la grille G2 est commandée par un signal SLEN, dont le drain D2 est relié à la masse GND et dont la source S2 est reliée au substrat B. Lorsque le transistor MD2 est passant, ce qui correspond au signal SLEN mis à 0 V, le transistor MD2 se comporte comme une diode dont l'anode est reliée au substrat B et dont la cathode est reliée à la masse GND. Cette diode supplémentaire se trouve donc en parallèle de la jonction substrat-source du transistor MSW qui tend à devenir passante lorsque la tension VP passe à VDD. Une telle diode supplémentaire permet, lorsque la tension VP passe à VDD, d'assurer que le potentiel VB ne s'élève pas au-delà de 0,5-0,6 V et d'accentuer l'évacuation des charges du substrat B.The figure 8 represents a bias circuit 45 according to a third embodiment of the invention in which, compared with the circuit 40 represented in FIG. figure 6 Was added between the substrate B and the ground GND, a MOS MD transistor 2 to P channel whose gate G 2 is controlled by a SLEN signal, the drain D2 is connected to ground GND and the source S 2 is connected to the substrate B. When the transistor MD 2 is on, which corresponds to the signal SLEN set to 0 V, the transistor MD 2 behaves as a diode whose anode is connected to the substrate B and whose cathode is connected GND ground. This additional diode is therefore in parallel with the substrate-source junction of the MSW transistor which tends to become conductive when the voltage V P goes to VDD. Such an additional diode makes it possible, when the voltage V P goes to VDD, to ensure that the potential V B does not rise above 0.5-0.6 V and to accentuate the evacuation of the charges from the substrate B.

La demanderesse a déterminé, par simulation, le gain en consommation dans le cas où le circuit électronique CL correspond à un oscillateur en anneau comportant 141 étages et constitué de transistors MOS à commutation rapide (c'est-à-dire ayant une tension de seuil faible, par exemple de l'ordre de 240 mV) réalisés en technologie SOI-PD avec une largeur de grille de 130 nanomètres, et pour une tension d'alimentation de 1,2 V. L'interrupteur de puissance MSW utilisé est du type permettant une pénalité en délai inférieure à 2 %. Les transistors MD1, MD2 du circuit 45 sont des transistors du type à faible fuite (tension de seuil élevée de l'ordre de 350 mV) . Le ratio de réduction de la consommation, R, est défini par la relation suivante: R = I cir / I sw

Figure imgb0002

où Icir correspond au courant de fuite à la borne de sortie O du circuit électronique CL lorsqu'il est connecté directement à la masse GND et ISW correspond au courant de fuite mesuré à la borne de sortie O lorsque le circuit électronique CL est relié à la masse GND via le transistor de puissance MSW.The Applicant has determined, by simulation, the gain in consumption in the case where the electronic circuit CL corresponds to a ring oscillator having 141 stages and constituted by fast switching MOS transistors (that is to say having a threshold voltage low, for example of the order of 240 mV) realized in SOI-PD technology with a gate width of 130 nanometers, and for a supply voltage of 1.2 V. The MSW power switch used is of the type allowing a penalty in time less than 2%. The transistors MD 1 , MD 2 of the circuit 45 are transistors of the low leakage type (high threshold voltage of the order of 350 mV). The ratio of reduction of the consumption, R, is defined by the following relation: R = I cir / I sw
Figure imgb0002
where I cir corresponds to the leakage current at the output terminal O of the electronic circuit CL when it is connected directly to ground GND and I SW corresponds to the leakage current measured at the output terminal O when the electronic circuit CL is connected GND ground via MSW power transistor.

La figure 9 représente l'évolution du ratio en fonction de la température. La courbe 46 correspond à l'évolution du ratio obtenue lorsque le substrat du transistor MSW est laissé flottant. La courbe 48 correspond à l'évolution du ratio obtenue lorsque le substrat B du transistor MSW est connecté en permanence à la masse GND. La courbe 50 correspond à l'évolution du ratio obtenue lorsque le circuit de polarisation 45 est associé au transistor MSW.The figure 9 represents the evolution of the ratio as a function of temperature. Curve 46 corresponds to the evolution of the ratio obtained when the substrate of transistor MSW is left floating. The curve 48 corresponds to the evolution of the ratio obtained when the substrate B of the transistor MSW is permanently connected to the ground GND. The curve 50 corresponds to the change in the ratio obtained when the bias circuit 45 is associated with the transistor MSW.

On remarque que le circuit de polarisation 45 selon la présente invention permet d'obtenir une forte augmentation du gain de consommation par rapport à ce qui était obtenu de façon classique. En outre, pour les courbes 46 et 48, le gain en consommation tend à diminuer lorsque la température augmente. Au contraire, pour la présente invention, le gain en consommation augmente avec la température.It will be noted that the bias circuit 45 according to the present invention makes it possible to obtain a sharp increase in the consumption gain compared with what was obtained in a conventional manner. In addition, for the curves 46 and 48, the consumption gain tends to decrease when the temperature increases. On the contrary, for the present invention, the consumption gain increases with temperature.

La figure 10 représente un circuit de polarisation 50 selon un quatrième exemple de réalisation de l'invention dans lequel, par rapport au circuit 45 de la figure 8, on a ajouté un transistor MOS MSL à canal N dont le drain D3 est connecté au drain D1 du transistor MD1 et dont la source S3 est connectée à la grille G1 du transistor MD1. Le circuit 50 comporte également un transistor MOS MAC à canal P dont le drain D4 est connecté au substrat B du transistor MSW et dont la source S4 est connectée à la grille G1 du transistor MD1. Les grilles G3, G4 des transistors MSL et MAC reçoivent le signal SLENB qui est le complémentaire du signal SLEN.The figure 10 represents a bias circuit 50 according to a fourth embodiment of the invention in which, compared with the circuit 45 of the figure 8 , an N-channel MOS transistor MSL has been added whose drain D 3 is connected to the drain D 1 of the transistor MD 1 and whose source S 3 is connected to the gate G 1 of the transistor MD 1 . The circuit 50 also comprises a P-channel MOS MAC transistor whose drain D 4 is connected to the substrate B of the transistor MSW and whose source S 4 is connected to the gate G 1 of the transistor MD 1 . The gates G 3 , G 4 of the transistors MSL and MAC receive the signal SLENB which is complementary to the signal SLEN.

Lorsque le circuit électronique CL est à l'état inactif, le signal SLEN est à l'état bas, par exemple à 0 V et le signal SLENB est à l'état haut, par exemple à VDD. Dans ce cas, le transistor MAC est bloqué et le transistor MSL est passant. De plus, le transistor MD2 est passant et monté en diode. Le circuit 50 est alors identique au circuit 45. Son fonctionnement correspond donc à ce qui a été décrit précédemment. Lorsque le circuit électronique CL est à l'état actif, le signal SLEN est à l'état haut et le signal SLENB est à l'état bas. Les transistors MD2 et MSL sont alors bloqués. Le transistor MAC est passant et équivaut sensiblement à un interrupteur fermé. La grille G1 du transistor MD1 est donc reliée au substrat B du transistor MSW. Le transistor MD1 fonctionne alors comme un limiteur de courant et équivaut à une diode dont l'anode est reliée au substrat B et la cathode à la grille G.When the electronic circuit CL is in the inactive state, the signal SLEN is in the low state, for example at 0 V and the signal SLENB is in the high state, for example at VDD. In this case, the MAC transistor is off and the MSL transistor is on. In addition, the transistor MD 2 is passing and diode mounted. The circuit 50 is then identical to the circuit 45. Its operation therefore corresponds to what has been described previously. When the electronic circuit CL is in the active state, the signal SLEN is in the high state and the signal SLENB is in the low state. The transistors MD 2 and MSL are then blocked. The MAC transistor is on and substantially equivalent to a closed switch. The gate G 1 of the transistor MD 1 is therefore connected to the substrate B of the transistor MSW. The transistor MD 1 then functions as a current limiter and is equivalent to a diode whose anode is connected to the substrate B and the cathode to the gate G.

A l'état actif, les tensions Vp et VSL sont à VDD. Le transistor MD1 permet d'amener VB à une valeur supérieure à 0 V tout en assurant que le potentiel VB reste inférieur à 0,6 V de façon qu'il n'y ait pas de polarisation en direct de la jonction substrat-source du transistor MSW. Le fait de mettre la tension VP à VDD permet d'élever initialement le potentiel VB par couplage capacitif, le potentiel VB étant maintenu par la suite à une valeur positive par l'intermédiaire du transistor MD1.In the active state, the voltages Vp and V SL are at VDD. The transistor MD 1 makes it possible to bring V B to a value greater than 0 V while ensuring that the potential V B remains below 0.6 V so that there is no direct bias of the substrate junction -Source of the MSW transistor. The fact of setting the voltage V P to VDD initially raises the potential V B by capacitive coupling, the potential V B being maintained thereafter at a positive value via the transistor MD 1 .

On obtient ainsi un transistor MSW dont le substrat est polarisé positivement à l'état actif. Ceci permet de diminuer la tension de seuil du transistor et d'améliorer la conduction du transistor MSW à l'état actif. Pour un même courant à conduire, on peut alors réduire les dimensions du transistor MSW par rapport à un transistor MOS dont le substrat serait maintenu à la masse à l'état actif. L'utilisation d'un transistor MSW de dimensions réduites permet de réduire les courants de fuite à l'état inactif. Le circuit 50 permet de diminuer d'environ 15 % la surface occupée par le transistor MSW. De façon plus générale, le circuit 50 permet d'obtenir un transistor MSW à deux tensions de seuil modulées dynamiquement, une première tension de seuil basse à l'état actif (le substrat B étant polarisé positivement) assurant une meilleure conduction et une seconde tension de seuil élevée à l'état inactif (le substrat étant polarisé négativement) permettant de réduire le courant de fuite.An MSW transistor is thus obtained, the substrate of which is positively biased in the active state. This makes it possible to reduce the threshold voltage of the transistor and to improve the conduction of the transistor MSW in the active state. For the same current to be driven, it is then possible to reduce the dimensions of the transistor MSW with respect to a MOS transistor whose substrate would be kept grounded in the active state. The use of a MSW transistor of reduced dimensions makes it possible to reduce the leakage currents in the inactive state. The circuit 50 makes it possible to reduce the area occupied by the transistor MSW by approximately 15%. More generally, the circuit 50 makes it possible to obtain an MSW transistor with two dynamically modulated threshold voltages, a first low threshold voltage in the active state (the substrate B being positively biased) providing better conduction and a second high threshold voltage in the inactive state (the substrate being negatively biased) to reduce the leakage current.

La figure 11 représente un sixième exemple de réalisation du circuit de polarisation 55 selon l'invention utilisé pour réduire les courants de fuite de plusieurs transistors de puissance MSW. Les transistors de puissance MSW sont répartis en groupes de transistors de puissance GTi, i étant un entier compris entre 1 et n, chaque groupe GTi étant associé à un circuit électronique BLi constitué, par exemple, de transistors à commutation rapide. Les grilles des transistors MSW de chaque groupe de transistors GTi sont connectées à un circuit partiel de polarisation PHi. Chaque circuit PHi comprend les transistors MOS MD1, MD2, MSL, MAC, et les condensateurs C1, C2 du circuit 50. Chaque circuit partiel PHi est relié à une première ligne 56 reliée à la source de tension SP, non représentée, et à une seconde ligne 58 reliée à la source de tension SL, non représentée. Des sources de tension uniques SP et SL sont donc connectées à chaque circuit PHi. De mêmes éléments des circuits de polarisation étant associés à plusieurs transistors, on diminue ainsi l'augmentation de surface due à l'utilisation du circuit de polarisation selon l'invention.The figure 11 represents a sixth embodiment of the bias circuit 55 according to the invention used to reduce the leakage currents of several MSW power transistors. The power transistors MSW are divided into groups of power transistors GT i , i being an integer between 1 and n, each group GT i being associated with an electronic circuit BL i constituted, for example, of fast switching transistors. The gates of the transistors MSW of each group of transistors GT i are connected to a partial polarization circuit PH i . Each circuit PH i comprises the MOS transistors MD 1 , MD 2 , MSL, MAC, and the capacitors C 1 , C 2 of the circuit 50. Each partial circuit PH i is connected to a first line 56 connected to the voltage source SP, not shown, and at a second line 58 connected to the voltage source SL, not shown. Unique voltage sources SP and SL are therefore connected to each circuit PH i . Like elements of the polarization circuits being associated with several transistors, the surface increase due to the use of the polarization circuit according to the invention is thus reduced.

Avantageusement, afin d'éviter une dégradation du transistor MSW, par exemple par claquage de la couche d'oxyde dû à une différence de potentiel entre le drain et la grille du transistor MSW supérieure à la tension d'alimentation, on peut utiliser un transistor MSW avec un oxyde de grille épais, adapté à fonctionner à des tensions d'alimentation élevées. Un tel transistor à oxyde de grille épais est, par exemple, du type GO2, l'épaisseur de l'oxyde de grille étant d'environ 2,7 nm, les autres transistors du circuit ayant une épaisseur d'oxyde de l'ordre de 1,5 nm.Advantageously, in order to avoid a degradation of the transistor MSW, for example by breakdown of the oxide layer due to a potential difference between the drain and the gate of the transistor MSW greater than the supply voltage, it is possible to use a transistor MSW with a thick gate oxide, suitable for operation at high supply voltages. Such a thick gate oxide transistor is, for example, of the GO2 type, the thickness of the gate oxide being approximately 2.7 nm, the other transistors of the circuit having an oxide thickness of the order 1.5 nm.

Bien entendu, la présente invention est susceptible de diverses variantes et modifications qui apparaîtront à l'homme de l'art. En particulier, la source de tension SP peut fournir un signal autre que rectangulaire. Il peut s'agir d'un signal constant à 0 V comportant périodiquement des impulsions triangulaires. En outre, la présente invention a été décrite pour la polarisation du substrat d'un transistor MOS à canal N. Toutefois, la présente invention peut s'appliquer à la polarisation du substrat d'un transistor MOS à canal P dont la source est reliée à une source d'un potentiel de référence haut, par exemple VDD. Dans ce cas, le substrat du transistor est mis, à l'état inactif, à un potentiel supérieur au potentiel de la source en faisant varier VP entre 0 V (impulsions de courtes durées) et VDD. En outre, le potentiel de la grille peut être amené à un potentiel supérieur au potentiel de la source à l'état inactif. De plus, le potentiel du substrat peut être amené à un potentiel inférieur au potentiel de la source à l'état actif.Of course, the present invention is susceptible of various variations and modifications which will be apparent to those skilled in the art. In particular, the voltage source SP can provide a signal other than rectangular. It can be a constant signal at 0 V periodically comprising triangular pulses. In addition, the present invention has been described for the biasing of the substrate of an N-channel MOS transistor. However, the present invention can be applied to the polarization of the substrate of a P-channel MOS transistor whose source is connected. to a source of a high reference potential, for example VDD. In this case, the transistor substrate is put, in the inactive state, at a potential greater than the potential of the source by varying V P between 0 V (pulses of short durations) and VDD. In addition, the potential of the gate can be brought to a potential greater than the potential of the source in the inactive state. In addition, the potential of the substrate can be brought to a potential lower than the potential of the source in the active state.

Claims (13)

  1. A circuit (30; 40; 45; 50; 55) for biasing the bulk (B) of a MOS transistor (MSW), characterized in that the bulk of the MOS transistor is surrounded by a well (12) providing an electric insulation of the substrate, the circuit comprising a capacitive element (C1) connecting the bulk (B) of the MOS transistor to a source (SP) capable of providing an A.C. voltage (Vp) at a first value for a first time period and at a second value (VDD) for a second time period shorter than half of the first time period.
  2. The circuit of claim 1, wherein the capacitive element (C1) comprises an electrode directly connected to the substrate (B).
  3. The circuit of claim 1, wherein the source (SP) is capable of providing the A.C. voltage (Vp) at the first value for the first time period and at the second value (VDD) for the second time period shorter than 1/10 of the first time period.
  4. The circuit of claim 1, wherein the MOS transistor (MSW) is an N-channel transistor, the second value being the zero voltage, and the first value being greater than the forward voltage drop of the bulk-source junction of the MOS transistor (MSW).
  5. The circuit of claim 1, comprising means (MD1) capable of connecting the bulk (B) and the gate (G) of the MOS transistor (MSW) when the MOS transistor is in the inactive state.
  6. The circuit of claim 1, comprising an additional MOS transistor (MD1) having its main terminals (S1, D1) connecting the bulk (B) to the gate (G) of the MOS transistor (MSW) and means (MSL, MAC) capable of connecting the gate (G1) of the additional transistor to the gate (G) of the MOS transistor (MSW) when the MOS transistor is in the inactive state.
  7. The circuit of claim 6, wherein the means (MSL, MAC) are capable of connecting the gate (G1) of the additional MOS transistor (MD1) to the bulk (B) of the MOS transistor (MSW) when the MOS transistor is in the active state.
  8. The circuit of claim 1, wherein the MOS transistor (MSW) is formed at the level of an SOI, GeOI or SON-type support.
  9. The circuit of claim 1, wherein the MOS transistor (MSW) comprises a first main terminal (D) connected to a terminal of an electronic circuit (CL) and a second main terminal (S) connected to a source of a reference voltage (GND), the assembly formed by the MOS transistor, the capacitive element (C1), and the source (SP) of the A.C. voltage (Vp) forming a pump of the charges of the MOS transistor bulk (B), the MOS transistor further behaving as a switch for the electronic circuit.
  10. A method for biasing the bulk (B) of a MOS transistor (MSW), characterized in that the bulk of the MOS transistor is surrounded by a well (12) providing an electric insulation of the substrate, the method comprising the connection of the MOS transistor bulk to a source (SP) of an A.C. voltage (Vp) by a capacitive element (C1), the A.C. voltage being at a first value for a first time period and at a second value (VDD) for a second time period shorter than half of the first time period.
  11. The method of claim 10, wherein the capacitive element (C1) comprises an electrode directly connected to the substrate (B).
  12. The method of claim 10, wherein the second time period is shorter than 1/10 of the first time period.
  13. The method of claim 10, further comprising the provision of an additional MOS transistor (MD1) having its main terminals (S1, D1) connecting the bulk (B) to the gate (G) of the MOS transistor (MSW) and the connection of the gate (G1) of the additional transistor to the gate (G) of the MOS transistor (MSW) when the MOS transistor is in the inactive state and the connection of the gate (G1) of the additional MOS transistor (MD1) to the bulk (B) of the MOS transistor (MSW) when the MOS transistor is in the active state.
EP07104336.8A 2006-03-17 2007-03-16 Device and method of adapting the potential of the substrate of an MOS transistor Not-in-force EP1835374B1 (en)

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EP3346606B1 (en) * 2009-10-23 2019-12-04 Telefonaktiebolaget LM Ericsson (publ) Passive mixer with reduced second order intermodulation
FR2968808A1 (en) * 2010-12-08 2012-06-15 Commissariat Energie Atomique ELECTRONIC CIRCUIT WITH NEUROMORPHIC ARCHITECTURE
US8542551B2 (en) 2011-07-29 2013-09-24 Taiwan Semiconductor Manufacturing Company, Ltd. Circuit and method for reducing leakage current

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JPS5758351A (en) 1980-09-24 1982-04-08 Toshiba Corp Substrate biasing device
JP2968836B2 (en) * 1990-11-30 1999-11-02 日本テキサス・インスツルメンツ株式会社 Semiconductor substrate potential generation circuit
KR940003153B1 (en) 1991-04-12 1994-04-15 금성일렉트론 주식회사 Back bias generater
US5686751A (en) * 1996-06-28 1997-11-11 Winbond Electronics Corp. Electrostatic discharge protection circuit triggered by capacitive-coupling
KR100243295B1 (en) * 1997-06-26 2000-02-01 윤종용 Back bias generator and method for generating the semiconductor device
US6225852B1 (en) * 1999-10-01 2001-05-01 Advanced Micro Devices, Inc. Use of biased high threshold voltage transistor to eliminate standby current in low voltage integrated circuits
KR101085698B1 (en) * 2004-09-08 2011-11-22 조지아 테크 리서치 코오포레이션 Frequency mixing device

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