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EP0373752A2 - Détecteur de lumière à semi-conducteur et sa méthode de fabrication - Google Patents

Détecteur de lumière à semi-conducteur et sa méthode de fabrication Download PDF

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Publication number
EP0373752A2
EP0373752A2 EP89310012A EP89310012A EP0373752A2 EP 0373752 A2 EP0373752 A2 EP 0373752A2 EP 89310012 A EP89310012 A EP 89310012A EP 89310012 A EP89310012 A EP 89310012A EP 0373752 A2 EP0373752 A2 EP 0373752A2
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Prior art keywords
layer
guard ring
semiconductor layer
junction
light detecting
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EP89310012A
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German (de)
English (en)
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EP0373752A3 (fr
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Hideto Intellectual Property Division Furuyama
Tetsuo Intellectual Property Division Sadamasa
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Toshiba Corp
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Toshiba Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F71/00—Manufacture or treatment of devices covered by this subclass
    • H10F71/127—The active layers comprising only Group III-V materials, e.g. GaAs or InP
    • H10F71/1272—The active layers comprising only Group III-V materials, e.g. GaAs or InP comprising at least three elements, e.g. GaAlAs or InGaAsP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02387—Group 13/15 materials
    • H01L21/02392—Phosphides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02461—Phosphides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02463—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02543—Phosphides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02546—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F30/00—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors
    • H10F30/20—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors
    • H10F30/21—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation
    • H10F30/22—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation the devices having only one potential barrier, e.g. photodiodes
    • H10F30/225—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation the devices having only one potential barrier, e.g. photodiodes the potential barrier working in avalanche mode, e.g. avalanche photodiodes
    • H10F30/2255—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation the devices having only one potential barrier, e.g. photodiodes the potential barrier working in avalanche mode, e.g. avalanche photodiodes in which the active layers form heterostructures, e.g. SAM structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F71/00—Manufacture or treatment of devices covered by this subclass
    • H10F71/127—The active layers comprising only Group III-V materials, e.g. GaAs or InP
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/544—Solar cells from Group III-V materials

Definitions

  • the present invention relates to a semiconductor light detector utilizing an avalanche effect and, more particularly, to a semiconductor light detector having an improved guard ring structure and a method of manufacturing the same.
  • an avalanche photo diode (to hereinafter be referred to as an APD) has been used as a high-sensitivity light detector in such fields as optical fiber communication systems.
  • An APD is a device utilizing avalanche-carrier multiplication of a semicon­ductor crystal, and has an avalanche region having a high electric field inside the device. For this reason, a guard ring structure is important to prevent local breakdown caused by electric field concentration in the avalanche region; in particular, in the peripheral portion of the avalanche region.
  • An optical communication system generally uses an APD which includes a light detection layer (light absorption layer) consisting of GaInAs (having a composition lattice-matched with InP) having high sensitivity in a low-loss range (wavelength; 1.3 to 1.5 ⁇ m) of a quartz optical fiber, carriers generated in the light receiving layer being subjected to avalanche multiplication by InP.
  • a light detection layer light absorption layer
  • GaInAs having a composition lattice-matched with InP
  • wavelength 1.3 to 1.5 ⁇ m
  • a guard ring is formed.
  • a p-n junction having a slow concentration gradient (to be referred to as a moderately graded junction hereinafter) is formed at the end portion of the front portion of the steeply graded junction.
  • the guard ring can suppress the local breakdown.
  • the depth of the moderately graded junction must be slightly larger than that of the steeply graded junction. If the steeply graded junction is too close to the moderately graded junction, the effect of the moderately graded junction is decreased.
  • a method of equivalently increasing the curvature of an impurity doped interface can effectively suppress the local breakdown.
  • a conventional APD wherein a guard ring is formed will be described hereinafter with reference to Figs. 1 to 4.
  • Fig. 1 is a sectional view showing an example of a conventional APD disclosed in Lecture Papers of the 46th Lectures of the Japan Society of Applied Physics, 1985, Autumn.
  • an n-InP buffer layer 2 an n ⁇ -GaInAs light absorbing layer 3, an n ⁇ -GaInAsP (composition having an absorption edge wavelength of 1.3 ⁇ m) intermediate layer 4, an n-InP avalanche multiplication/electric field relaxation layer 5, an n ⁇ -InP window layer 6, a p-type guard ring 8 for forming a moderately graded junction, a p-type light receiving region 9 for forming a steeply graded junction, an insulating layer 11, and a non-reflection coating layer 12 are sequentially formed on an n-InP substrate 1.
  • An electrode 13 is formed on an exposing surface of the light detection layer 9, and an electrode 14 is formed on a lower surface of the substrate 1.
  • a depletion layer extends under the p-type regions 8 and 9, and carriers generated in the light absorbing layer 3 are guided to a high electric field region concentrated in the p-n junction region and are subjected to avalanche multiplication.
  • the light detecting region 9 is generally formed close to the n-InP layer 5 to decrease the width of the high electric field region. Therefore, the junction defined by the guard ring 8 is formed to extend in the n-InP layer 5.
  • the impurity concentration of the n-InP layer 5 is relatively high, an effect of the moderately graded junction on the interface of the guard ring 8 tends to be insufficient, thus easily causing local breakdown.
  • a shallow guard ring is expanded in a longitudinal direction to prevent the local breakdown. This is equivalent to an increase in curvature of the peripheral portion of the guard ring.
  • the electric field value of the light detection layer 3 tends to increase because the moderately graded junction is deep under the steeply graded junction, and a current generated in a hetero­interface or a dark current due to a tunnel current in the light detection layer 3 tends to be increased.
  • the above problems are posed when the impurity concentration of the n-InP layer 5 is increased and the thickness thereof is decreased to achieve a high-speed operation.
  • Fig. 2 is a sectional view showing a prior art wherein the shape of the interface portion of the steeply graded junction is changed and the equivalent curvature of the interface is increased.
  • This prior art is disclosed in the Institute of Electronics and Communication Engineers of Japan, the National Meeting, Lecture Papers C - 172, 1988, Autumn.
  • a guard ring providing the moderately graded junction is not formed, but only the shape of the interface portion of the steeply graded junction prevents local breakdown.
  • This modernately grated junction is formed by thermal diffusion of Zn, Cd, or the like.
  • a central light detecting region (projection) is formed by selective forced diffusion of an impurity. As a result, a high electric field region is formed in the central projection, and the electric field concent­ration in the projection interface is decreased.
  • the nonuniformity of the light detection sensitivity undesirably tends to occur over the light detection region.
  • the front portion of the diffusion region approaches the n-InP layer 5 in order to achieve a high-­speed operation of the device, local breakdown in the front peripheral portion tends to occur again. As a result, this structure is not suitable for a high-speed APD.
  • Fig. 3 shows a prior art wherein a part of the n-InP layer 5 on which the guard ring is to be formed is removed, and another n ⁇ -InP layer 6 is grown again.
  • This prior art is disclosed in Japanese Patent Disclosure No. 61-220481.
  • the guard ring providing the moderately graded junction is formed in the front peripheral portion of the steeply graded junction.
  • the moderately graded junction can hardly affect the light detection layer 3.
  • a substantially ideal guard ring structure can be obtained by performing optimization. Such an excellent structure is suitable for a high-speed APD, and problems on its character­istics can be substantially solved.
  • a wafer size is limited, the flatness of the regrowth interface is easily damaged, and the number of factors to reduce a manufacturing yield is increased.
  • the thickness of the layer formed by the second crystal growth is large, i.e., 2 to 3 ⁇ m, cost is undesirably increased because of the second crystal growth.
  • Fig. 4 shows a prior art having the above advantages of the prior arts shown in Figs. l and 2.
  • This prior art is disclosed in Japanese Patent Disclosure No. 61-191082.
  • the thickness of the n ⁇ -InP layer 6 is slightly increased, and the central light detection region portion is removed by etching or ion milling to obtain a smooth profile. Thereafter, a moderately graded junction is formed.
  • the guard ring 8 providing the moderately graded junction is formed in the front peripheral portion of the steeply graded junction.
  • the n ⁇ -InP layer obtained by regrowth is not required, and the diffusion depth of the steeply graded junction may be relatively small. Therefore, the above problems are not posed.
  • the extremely high-­precision controllability of etching or ion milling is required, so that the manufacturing yield becomes low.
  • a semiconductor light detector comprising a first semiconductor layer of a first conductivity type having a multi-layer structure including a light absorbing layer and an avalanche multiplicating layer, an annular second semiconductor layer formed on the first semiconductor layer, a light detecting region formed by doping an impurity of a second conductivity type in a surface region of the first semiconductor layer in such a manner that a peripheral portion of the light detecting region is located outside an inner periphery of the second semiconductor layer, the light detecting region defining a first p-n junction with the first semiconductor layer, and a guard ring formed by doping an impurity of the second conductivity type in a surface region of the first semiconductor layer to surround the peripheral portion of the light detecting region, the guard ring defining a second p-n junction with the first semiconductor layer, the second p-n junction having a concentration gradient smaller than that of the first p-n junction, wherein a junction depth of the peripheral portion of the light detecting region is smaller than that
  • a method of manufacturing the semicon­ductor light detector comprising the steps of doping an impurity of a second conductivity type in a surface region of a first semiconductor layer of a first conduc­tivity type having a multi-layer structure including a light absorbing layer and an avalanche multiplicating layer to form a guard ring, the guard ring defining a second p-n junction, forming an annular second semiconductor layer on a surface of the first semiconductor layer corresponding to the guard ring, forming a masking layer on a peripheral portion of the second semiconductor layer and a surface of the first semiconductor layer outside the peripheral portion, and doping an impurity of a second conductivity type in the first semiconductor layer using the masking layer as a mask in such a manner that a diffusion depth of a central portion of the first semiconductor layer is larger than that of the guard ring, and that a diffusion depth of a peripheral portion of the first semiconductor layer is smaller than that of the guard ring so as to form a light
  • a method of manufacturing the semiconductor light detector comprising the steps of forming a first mask layer including an annular window on a surface of a first semiconductor layer of a first conductivity type having a multi-layer structure including a light absorbing layer and an avalanche multiplicating layer, selectively forming a spacing layer on the first semiconductor layer, the first semiconductor layer being exposed in the annular window, doping an impurity of a second conductivity type in a surface region of the first semiconductor layer through the spacing layer to form a guard ring, the guard ring defining a second p-n junction, forming a second masking layer on a surface of the first semiconductor layer outside the second semiconductor layer, and doping an impurity of the second conductivity type in the first semiconductor layer using the second masking layer as a mask in such a manner that a diffusion depth of a central portion of the first semiconductor layer is larger than that of the guard ring and that a diffusion depth of a peripheral portion of the first semiconductor layer is smaller than that
  • Fig. 5 is a sectional view showing a schematic structure of an APD according to a first embodiment of the present invention.
  • reference numeral 21 denotes an n-InP substrate.
  • an n-InP buffer layer 22 carrier concentration: 5 ⁇ 1016 cm ⁇ 3 or less; thickness: 0.5 ⁇ m
  • an n ⁇ -GaInAs light absorption layer 23 carrier concentration: 1 ⁇ 1015 cm ⁇ 3; thickness: 2 ⁇ m
  • an n-GaInAsP intermediate layer 24 (absorption edge wavelength: 1.3 ⁇ m; carrier concentration: 2 ⁇ 1016 cm ⁇ 3 thickness: 0.4 ⁇ m)
  • an n-InP multiplication layer 25 carrier concentration: 4 ⁇ 1016 cm ⁇ 3; thickness: 0.8 ⁇ m
  • an n ⁇ -InP layer 26 carrier concentration: 1 ⁇ 1015 cm ⁇ 3; thickness: 1.2 ⁇ m
  • an annular GaInAsP spacing layer 27 (absorption edge wavelength: 1.3 ⁇ m; undoped; thickness: 0.2 ⁇ m) is grown on the n ⁇ -InP layer 26.
  • a p-type region (guard ring) 28 is formed by implanting Be ions, and a p-type region (light detecting region) 29 is formed by diffusing Cd or Zn ions.
  • An insulating film 31, a non-reflection film 32, and an electrode 33 are formed on an upper surface of the above structure, and an electrode 34 is formed on a lower surface of the n-InP substrate. Note that the insulating film 31 and the non-reflection film 32 con­sist of silicon nitride films, and the electrodes 33 and 34 consist of AuZn and AuGe, respectively.
  • the conditions for Be ion implantation to form a moderately graded p-n junction is as follows. That is, the Be ions are implanted at an accelerated energy of 200 keV and a dose of 1 ⁇ 1013 cm- ⁇ 2. After the ion implantation, annealing is performed at 700°C for 20 minutes. In the diffusion of Cd or Zn to form a steeply graded p-n junction, e.g., vapor diffusion of Cd is performed at 560°C for 20 minutes by a closed ampoule (10 cc, 1 ⁇ 10 ⁇ 6 Toor at a room temperature) method using Cd3P2 (20 mg) as a source.
  • the central diffusion front of the light detecting region 29 is extremely close to the n-InP layer 25, and the depth of the peripheral diffusion front is smaller than that of the central portion.
  • the diffusion front of the guard ring 28 is defined between the central and peripheral portions of the diffusion front of the light detecting region 29.
  • an MOCVD method is employed as a crystal growth method of the layers 22 to 27. According to this method, the crystal is grown at 620°C.
  • a dark current of the element in the light detecting region having a diameter of 50 ⁇ m is 10 nA or less, thus obtaining an excellent APD.
  • the junction depth of the peripheral portion of a steeply graded p-n junction can be decreased, as compared with that of the central portion, by a depth substantially corresponding to the thickness of the spacing layer 27.
  • a sufficient guard ring effect can be obtained while flatness of the surface of the semiconductor multi-layer film is kept without a guard ring having a large junction depth. Therefore, a guard ring breakdown voltage can be improved, and a dark current can be decreased.
  • the above-mentioned layers 22 to 27 are formed on the n-InP substrate 21 by crystal growth.
  • an SiO2 film 35 having a thickness of about 8,000 ⁇ is formed on the GaInAsP spacing layer 27, and an annular window 35a is formed on the SiO2 film 35.
  • a resist pattern (not shown) is formed on the SiO2 film 35, and etching is performed for about one minute using the resist pattern as a mask and using an NH4F aqueous solution as a etchant.
  • Be ions are implanted in an annular region having an inner diameter of 55 ⁇ m, and an outer diameter of 80 ⁇ m. Then, annealing is performed. Therefore, a p-type region (guard ring) 28 is formed in the InP layer 26.
  • the SiO2 film 35 is removed. Thereafter, the GaInAsP spacing layer 27 is etched to form an annular layer which partially overlaps the window and has a diameter slightly smaller than that of the window.
  • the resultant spacing layer 27 may be selectively etched at 26°C for about one minute using an etching solution obtained by mixing sulfuric acid, a hydrogen peroxide aqueous solution, and water at a ratio of 4:1:1, in the order named.
  • the silicon nitride film 31 is deposited on the entire surface by plasma CVD. There­after, a circular diffusion window having a diameter of 60 ⁇ m is formed on the silicon nitride film 31. That is, the portion of the silicon nitride film 31, which is on the spacing layer 27 excluding the peripheral portion and surrounded by the spacing layer 27, is removed. Thermal diffusion of Cd or Zn is performed to form the p-type region (light detecting region) 29. At this time, as shown in Fig. 6D, the central diffusion front of the light detecting region 29 is extremely close to the n-InP layer 25, and the peripheral diffusion front of the light detecting region 29 is away from the layer 25 due to the presence of the spacing layer 27.
  • the depth of the central diffusion front of the light detecting region 29 can be larger than that of the diffusion front of the guard ring 28, and the depth of the peripheral diffusion front of the light detecting region 29 can be smaller than that of the diffusion front of the guard ring 28.
  • the depth of the peripheral diffusion front of the light detecting region 29 is smaller than that of the central diffusion front of the region 29, the depth of the diffusion front of the guard ring 28 can be larger than that of the peripheral diffusion front of the light detecting region 29 without extending into the n-InP layer 25. There­fore, a sufficient guard ring breakdown voltage can be obtained and a dark current can be minimized. In this case, only single crystal growth is required in the manufacturing steps, and the kind of growth technique is not limited.
  • a difference between the depth of the central diffusion front and that of the peripheral diffusion front is defined by the thickness of the spacing layer 27.
  • the crystal surface is substantially flat, and sufficient flatness can be kept as a planar type device. Therefore, the excellent device characteristics are obtained, and simple manufacturing and mounting are effectively performed.
  • Fig. 7 is a sectional view showing a schematic arrangement of an APD according to a second embodiment of the present invention.
  • the same reference numerals in Fig. 7 denote the same parts as in Fig. 5, and a detailed description thereof will be omitted.
  • a difference between the above-mentioned embodiment and this embodiment is that Be ions are implanted in the entire surface of a p-n junction region to form a guard ring in this embodiment. More specifically, ions are not implanted in an annular region, but are implanted in a circular region 48 having a diameter larger than that of a light detecting region 29. Only a change in pattern, i.e., removal of the central portion of the ion-implantation mask is required to allow the ion implantation to the entire surface of the p-n junction region.
  • the Be ions are implanted in the entire surface in this embodiment. However, in the central region, the depth of a moderately graded p-n junction obtained by implanting Be ions is smaller than that of a steeply graded p-n junction obtained by implanting Cd or Zn, so that the element characteristics are little affected.
  • a feature of this embodiment is as follows. That is, the overlap margin of the guard ring formed by diffusion of Be ions and the light detecting region formed by diffusion of Cd or Zn is increased to allow a decrease in size of the pattern, so that the entire p-n junction area is reduced, thus decreasing a parasitic capacitance.
  • Fig. 8 is a sectional view showing a schematic structure of an APD according to a third embodiment of the present invention.
  • reference numeral 51 denotes an n-Inp substrate.
  • an n-InP buffer layer 52 On the substrate 51, an n-InP buffer layer 52, an n ⁇ -GaInAsP light detecting layer 53 (having a composition lattice-matched with InP), an n ⁇ -GaInAsP first intermediate layer 54a (absorption wavelength: 1.3 ⁇ m), an n ⁇ -GaInAsP second intermediate layer 54b (absorption wavelength: 1.1 ⁇ m), an n-InP avalanche multiplication/electric field relaxation layer 55, an n ⁇ -InP window layer 56 are grown and formed, and an annular semiconductor spacing layer 57 in formed thereon.
  • the spacing layer 57 consists of, e.g., InP.
  • the spacing layer 57 may be a crystal of GaInAsP, GaInAs, or the like.
  • composition and thickness of the spacing layer 57 may be changed depend­ing on the structure design and process conditions.
  • the two intermediate layers are used in this embodiment unlike the above embodiments in order to decrease the discontinuity of the band gap between the light detecting layer 53 and the electric relaxation layer 55.
  • each semiconduc­tor layer has a concentration of 4 ⁇ 1016 cm ⁇ 3 and thickness of 0.5 ⁇ m
  • the light absorption layer 53 has a concentration of 5 ⁇ 1015 cm ⁇ 3 or less and a thickness of 2 ⁇ m
  • each of the first and second inter­mediate layers 54a and 54b has a concentration of 5 ⁇ 1015 cm ⁇ 3 and a thickness of 0.1 ⁇ m
  • the avalanche multiplication/electric field relaxation layer 55 has a concentration of 4 ⁇ 1016 cm ⁇ 3 and a thickness of 0.9 ⁇ m
  • the window layer 56 has a concentration of 5 ⁇ 1015 cm ⁇ 3 or less and a thickness of 1 ⁇ m
  • the spac­ing layer 57 has a concentration of 5 ⁇ 1015 cm ⁇ 3 or less and a thickness of 0.4 ⁇ m.
  • Reference numeral 58 denotes a p-­type region (guard ring) formed by implanting Be ions to define a moderately graded p-n junction; 59, a p-type region (light detecting region) formed by thermal diffusion of Cd to define a steeply graded p-n junction; 61, a passivation film (e.g., a silicon nitride film: thickness of 2,000 ⁇ ); 62, a non-reflection coating layer; and 63 and 64, electrodes (e.g., Ti/Pt/Au: 1,500/500/5,000 ⁇ , and ArGe/Au: 2,000/5,000 ⁇ ). Be in the p-type region 58 and Cd in the light detecting region 59 can be replaced by other acceptor impurities (e.g., Mg or Zn), or a means for doping the impurities may be replaced.
  • acceptor impurities e.g., Mg or Zn
  • Figs. 9A to 9D are sectional views showing the steps in manufacturing the device shown in Fig. 8.
  • One side of the guard ring is shown in Figs. 9A to 9D, and the semiconductor layers below the n-InP layer 55 are omitted.
  • the detailed structure elements of the layers are the same as in Fig. 8.
  • crystal growth of the semicon­ductor layers 52 to 56 shown in Fig. 8 is performed.
  • an MOCVD method is used as a crystal growth method. This crystal growth is performed at 620°C.
  • an SiO2 film 65 having a thickness of 1 ⁇ m is formed on the n ⁇ -InP layer 56 as a mask for perform­ing selective crystal growth and ion implantation.
  • An annular window 65a corresponding to a guard ring portion is formed.
  • the annular window 65a has an inner diameter of, e.g., 40 ⁇ m and an outer diameter of, e.g., 60 ⁇ m.
  • the annular window 65a is formed by normal photolitho­graphy and wet etching using an NH4F aqueous solution.
  • the InP spacing layer 57 is selectively grown in the annular window 65a formed in the SiO2 mask 65.
  • a polysilicon substance 57′ is often precipitated on the mask 65 depending on the crystal growth conditions, it can be disregarded in this case.
  • a refractory material having an ultimate conductivity wherein an impurity can be diffused can be employed as the material of the spacing layer 57. Therefore, an amorphous layer may be used as the spacing layer.
  • deposition may be performed by sputtering or CVD.
  • a Be ion implantation region 58′ is formed by ion implantation.
  • the implantation conditions are as follows.
  • the ion implantation is performed at an accelerated voltage of 200 keV and a dose of 1 ⁇ 1013 cm ⁇ 2.
  • the mask 65 is then removed. Thereafter, a thermal treatment (crystal annealing) is performed in an atmosphere containing extra P.
  • the mask 65 may be removed using an HF aqueous solution or an NH4F aqueous solution.
  • annealing is performed in an atmosphere of an H2 gas containing PH3 of 10,000 ppm at 750°C for 10 minutes after the mask 65 is removed. Note that this annealing may be performed while the mask 65 remains.
  • Another cover mask e.g., a glass layer consisting of PSG or ASG
  • cap annealing may be performed.
  • the annular projection 57 obtained by selective crystal growth and the p-type region (guard ring) self-aligned therewith are formed.
  • One photoetching process is performed before this step. Note that the diffusion front of the guard ring 58 is located near the interface between the layers 55 and 56.
  • the mask 61 for thermal diffusion of Cd is deposited by plasma CVD, and a window of the light detecting region (Cd diffusion portion) is formed by normal photolithography and dry etching using a CF4 gas.
  • the mask 61 finally remains as a passivation film.
  • the mask 61 need not be formed in this step.
  • the ion implantation and selective growth mask 65 having a two-layer structure of a silicon nitride layer (2,000 ⁇ ) and an SiO2 layer (8,000 ⁇ ) may be formed in the step shown in Fig. 9B, and the SiO2 layer may be selectively removed by etching using an NH4F aqueous solution after the ion-implantation process. At this time, the silicon nitride film formed on the inner peripheral portion and the interior of the annular projection is removed by photolithography.
  • the thermal diffusion is performed at 560°C for 10 minutes to diffuse Cd, thus forming the p-type region (light detecting region 59).
  • the depth of the central diffusion front of the light detecting region 59 is smaller than that of the peripheral diffusion front of the region 59.
  • Figs. 10A to 10C correspond to the above-mentioned step shown in Fig. 9D, and show a case wherein the position of the window of the light detecting region (Cd diffusion portion) in the Cd thermal diffusion mask 61 is gradually shifted relatively to the annular spacing layer 57.
  • the pattern shift can hardly affect the element structure when the shift width does not exceed the width of the firstly formed annular window.
  • a position at which a deformed region of the Cd diffusion overlaps the guard ring 58 is not changed, and a width at which the deep portion (bottom of the step) of the Cd diffusion front portion overlaps the guard ring 58 (i.e. a distance between the inner edge of the guard ring 58 and the stepped portion of the Cd diffusion region) is also kept constant. Therefore, the amount of dark current which tends to be generated in a region wherein the Cd diffusion front portion overlaps the guard ring is also kept constant.
  • the Cd diffusion mask 61 also serves as the first ion implantation mask, as described above, the Cd diffusion region includes the entire regions below the annular projection, and the outer periphery substantial­ly coincides with the outer periphery of the annular projection, and is self-aligned.
  • the structure of the device thus obtained is shown in Fig. 11.
  • the annular window of the mask also serves as a mask window for the impurity implanta­tion of the moderately graded junction (guard ring), their positions are self-alinged.
  • the steeply graded junction is deformed in the inner periphery of the semiconductor spacing layer obtained by selective growth. Therefore, the positions of the inner perphery of the guard ring and the steeply graded junction deformed portion are self-aligned.
  • an overlap margin of the patterns of the semiconductor spacing layer and the guard ring is not required as compared with a case wherein the semiconductor spacing layer and the guard ring are individually formed, so that the area of the p-n junction is reduced and the parasitic capacitance of the element can be decreased without degrading the guard ring performance.
  • the depth of the crystal growth of the semiconductor spacing layer is relatively small, an increase in cost caused by the crystal growth is cancelled by a decrease in steps of the mask alignment and an increase in yield of the elements achieved by providing a self-alignment process. Therefore, a precision of the projection step can be improved by the crystal growth, and hence the performance and repro­ducibility of the devices are improved, thus effectively improving the entire cost performance.
  • Fig. 12 is a sectional view showing a schematic structure of an APD according to a fourth embodiment of the present invention.
  • the same reference numerals in Fig. 12 denote the same parts as in Fig. 8, and a detailed description thereof will be omitted.
  • a bonding pad region is formed in the structure shown in Fig. 8 to perform wire-­bonding.
  • the bonding pad of the optical communication APD often has an area substantially equal to the p-n junction area of the element, and the parasitic capacitance of the bonding pad tends to cause a problem. Therefore, the thickness of an insulating film below the bonding pad is normally increased or a guard ring often extends below the bonding pad.
  • Fig. 12 shows the latter example wherein a dark current is improved as compared with the normal case.
  • two layers 57 and 67 are formed by selective crystal growth in the step shown in Fig. 9B in this embodiment, and the second layer 67 except for the bonding pad is selectively removed before the ion implantation step. Then, the following processes are performed in the same manner as in Figs. 9C and 9D, thus obtaining the structure shown in Fig. 12.
  • the junction depths of Be moderately graded junction and Cd steeply graded junction are small. For this reason, an electric field value is not unnecessarily increased in a light absorption layer 53 below the bonding pad, and an increase in dark current due to an increase in guard ring area can be suppressed.
  • Figs. 13A, 13B, 14A, and 14B show an improved example for preventing abnormal growth which tends to occur in the selective growth step in Fig. 9B.
  • a crystal material which has reached a portion covered with the mask performs thermal motion on the mask surface.
  • the crystal material stays in a low-­energy region on the mask surface or is reevaporated from the mask surface to perform energy storage. Therefore, in the original selective crystal growth wherein polycrystalline substances are not precipitated on the mask surface, it is preferable that all the crys­tal materials are reevaporated from the mask surface.
  • the crystal mate­rial often moves on the mask to reach the mask interface.
  • the crystal material which has reached the mask surface is supplied to the underlying crystal on the mask inter­face as an extra crystal material.
  • a deposition material flow tends to be tempo­rarily discontinued or stopped at the mask interface.
  • An increase in concentration of the crystal material molecules occurs or the moving molecules on the mask surface are undesirably drawn at the mask interface.
  • Figs. 13A and 13B show an example wherein the selective crystal growth is performed on the (001) surface of the InP substrate. This growth occurs in the ⁇ 110> and ⁇ 110> crystal orientation directions. Such abnormal growth causes a fault in photolithography, or poor or degraded device characteristics.
  • the selective crystal growth mask has a two-layer structure.
  • a selective crystal growth mask is obtained by stacking a silicon nitride film 68 on an SiO2 film 65.
  • the SiO2 film 65 has a thickness of 8,000 ⁇
  • the silicon nitride film 68 has a thickness of 2,000 ⁇ .
  • the silicon nitride film 68 is patterned by dry etching.
  • the SiO2 film 65 is patterned by an NH4F aqueous solution and an overhang of the silicon nitride film 68 is formed utilizing a difference of the etching rates between the SiO2 film 65 and the silicon nitride film 68.
  • selective crystal growth is performed to allow crystal growth without growth of a projection, as shown in Figs. 14A and 14B. This crystal growth can be performed because the molecules which have moved on the mask surface are easily vapored at the overhang. Even though slight abnormal growth is recognized, extreme projection growth can hardly occur.
  • the thickness of the crystal growth on the mask interface may become large or small, the thickness may be optimized in accordance with the conditions of the following process.
  • the present invention is not limited thereto, and a proper change may be made in accordance with the technical specifications.
  • a multi-layer structure consisting of InP-GaInAs-AlInAS, or Si-SiGe-Si can be employed.
  • the material of the spacing layer is not limited to a single crystal of GaInAs, GaInAsP or InP, and poly­crystalline or amorphous deposit or the other material such as AlGaAS and AlInAS can be employed.
  • semiconductor layers of an n conductivity type are formed in the above embodiments, p-type semiconduc­tor layers can be formed.
  • the guard ring and light detecting region have the n conductivity type. Si, Sn or the like can be used as an n-type impurity.
  • the peripheral junction depth is smaller than the central junction depth. Therefore, a sufficient guard ring effect can be obtained while surface flatness of the semiconductor multi-layered film is kept. There­fore, a high breakdown voltage of a guard ring can be obtained and a dark current can be minimized. As a result, a high manufacturing yield can be realized with on increase in the manufacturing cost.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Light Receiving Elements (AREA)
EP89310012A 1988-12-14 1989-09-29 Détecteur de lumière à semi-conducteur et sa méthode de fabrication Ceased EP0373752A3 (fr)

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JP63315619A JPH02159775A (ja) 1988-12-14 1988-12-14 半導体受光素子及びその製造方法
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0600746A1 (fr) * 1992-12-04 1994-06-08 Nec Corporation Photodiode à avalanche
EP1005067A2 (fr) * 1998-11-26 2000-05-31 Sony Corporation Procédé de croissance d'un semiconducteur de type composé de nitrure III-V, fabrication d'un dispositif semiconducteur et dispositif semiconducteur
FR3001578A1 (fr) * 2013-01-31 2014-08-01 New Imaging Technologies Sas Matrice de photodiode a zone dopee absorbant les charges

Families Citing this family (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB8817886D0 (en) * 1988-07-27 1988-09-01 British Telecomm Avalanche photodiode structure
US5114866A (en) * 1989-02-10 1992-05-19 Hitachi, Ltd. Fabricating an avalanche photo diode having a step-like distribution
JP2970815B2 (ja) * 1990-04-11 1999-11-02 株式会社東芝 半導体受光素子
JP3288741B2 (ja) * 1992-02-07 2002-06-04 住友電気工業株式会社 半導体受光素子の製造方法
US5461250A (en) * 1992-08-10 1995-10-24 International Business Machines Corporation SiGe thin film or SOI MOSFET and method for making the same
US5777364A (en) * 1992-11-30 1998-07-07 International Business Machines Corporation Graded channel field effect transistor
JPH08204224A (ja) * 1995-01-23 1996-08-09 Sumitomo Electric Ind Ltd 化合物半導体受光素子及びその製造方法
US5610416A (en) * 1995-02-16 1997-03-11 Hewlett-Packard Company Avalanche photodiode with epitaxially regrown guard rings
US6147391A (en) * 1996-05-07 2000-11-14 The Regents Of The University Of California Semiconductor hetero-interface photodetector
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US5866936A (en) * 1997-04-01 1999-02-02 Hewlett-Packard Company Mesa-structure avalanche photodiode having a buried epitaxial junction
US5757057A (en) * 1997-06-25 1998-05-26 Advanced Photonix, Inc. Large area avalanche photodiode array
US5831322A (en) * 1997-06-25 1998-11-03 Advanced Photonix, Inc. Active large area avalanche photodiode array
US6515315B1 (en) * 1999-08-05 2003-02-04 Jds Uniphase, Corp. Avalanche photodiode for high-speed applications
KR100366046B1 (ko) * 2000-06-29 2002-12-27 삼성전자 주식회사 에벌란치 포토다이오드 제조방법
GB2367945B (en) * 2000-08-16 2004-10-20 Secr Defence Photodetector circuit
JP4208172B2 (ja) * 2000-10-31 2009-01-14 シャープ株式会社 フォトダイオードおよびそれを用いた回路内蔵受光素子
JP3910817B2 (ja) * 2000-12-19 2007-04-25 ユーディナデバイス株式会社 半導体受光装置
DE10223202A1 (de) * 2002-05-24 2003-12-11 Fraunhofer Ges Forschung Photodiode
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JP2009010175A (ja) * 2007-06-28 2009-01-15 Sumitomo Electric Ind Ltd 受光素子およびその製造方法
US7834379B2 (en) * 2007-07-18 2010-11-16 Jds Uniphase Corporation Avalanche photodiode with edge breakdown suppression
US8216134B2 (en) 2007-12-12 2012-07-10 Medtronic, Inc. Implantable optical sensor and method for manufacture
US8290557B2 (en) * 2007-12-12 2012-10-16 Medtronic, Inc. Implantable optical sensor and method for use
US8165676B2 (en) 2007-12-21 2012-04-24 Medtronic, Inc. Optical sensor and method for detecting a patient condition
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US8275435B2 (en) * 2009-01-22 2012-09-25 Medtronic, Inc. Co-location of emitters and detectors and method of operation
US7948006B2 (en) * 2009-06-01 2011-05-24 Jds Uniphase Corporation Photodiode with high ESD threshold
US9105790B2 (en) * 2009-11-05 2015-08-11 The Boeing Company Detector for plastic optical fiber networks
US8983302B2 (en) * 2009-11-05 2015-03-17 The Boeing Company Transceiver for plastic optical fiber networks
WO2011093912A1 (fr) * 2010-01-29 2011-08-04 Medtronic, Inc. Capteur optique pour dispositif médical
US11804561B2 (en) 2019-03-20 2023-10-31 Sony Semiconductor Solutions Corporation Light receiving element, method of manufacturing light receiving element, and imaging apparatus

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2331884A1 (fr) * 1975-11-11 1977-06-10 Philips Nv Procede pour fabriquer un dispositif semi-conducteur, et dispositif fabrique de la sorte
EP0053513A2 (fr) * 1980-12-02 1982-06-09 Fujitsu Limited Photodiodes à avalanche
EP0159544A1 (fr) * 1984-03-22 1985-10-30 Nec Corporation Photodiode à avalanche et méthode pour sa fabrication

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5642385A (en) * 1979-09-12 1981-04-20 Nec Corp Hetero-structure semiconductor device
DE3172668D1 (en) * 1980-07-08 1985-11-21 Fujitsu Ltd Avalanche photodiodes
JPS57112083A (en) * 1980-12-29 1982-07-12 Fujitsu Ltd Manufacture of avalanche photodiode
JPS5854685A (ja) * 1981-09-28 1983-03-31 Kokusai Denshin Denwa Co Ltd <Kdd> アバランシ・ホトダイオ−ド及びその製造方法
JPS60220481A (ja) * 1984-04-17 1985-11-05 Nec Corp 文字認識装置
JPH0824199B2 (ja) * 1984-05-31 1996-03-06 富士通株式会社 半導体受光素子の製造方法
JPS61191082A (ja) * 1985-02-20 1986-08-25 Fujitsu Ltd 半導体受光素子
JPS61220481A (ja) * 1985-03-27 1986-09-30 Fujitsu Ltd 半導体受光装置の製造方法
US4725870A (en) * 1985-11-18 1988-02-16 American Telephone And Telegraph Company, At&T Bell Laboratories Silicon germanium photodetector
JPS62259481A (ja) * 1986-04-15 1987-11-11 Fujitsu Ltd 半導体受光装置
DE3728691A1 (de) * 1986-08-28 1988-03-10 Nissan Motor Lichtempfindlicher positionssensor
JPS63281480A (ja) * 1987-05-13 1988-11-17 Hitachi Ltd 半導体受光素子及びその製造方法
JP2666841B2 (ja) * 1987-07-28 1997-10-22 日本電気株式会社 アバランシェ型半導体受光素子の製造方法
DE3855924T2 (de) * 1987-08-19 1998-01-29 Nippon Electric Co Planare Avalanche-Photodiode mit Heterostruktur
JP2664158B2 (ja) * 1987-08-24 1997-10-15 株式会社日立製作所 半導体受光装置の製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2331884A1 (fr) * 1975-11-11 1977-06-10 Philips Nv Procede pour fabriquer un dispositif semi-conducteur, et dispositif fabrique de la sorte
EP0053513A2 (fr) * 1980-12-02 1982-06-09 Fujitsu Limited Photodiodes à avalanche
EP0159544A1 (fr) * 1984-03-22 1985-10-30 Nec Corporation Photodiode à avalanche et méthode pour sa fabrication

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
I.E.E.E. TRANSACTIONS ON ELECTRON DEVICES, vol. ED-34, no. 11, November 1987, pages 2265-2269, IEEE, New York, US; G.-C. CHI et al.: "Planar InP/InGaAsP three-dimensional graded junction avalanche photodiode" *

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0600746A1 (fr) * 1992-12-04 1994-06-08 Nec Corporation Photodiode à avalanche
US5406097A (en) * 1992-12-04 1995-04-11 Nec Corporation Avalanche photo-diode for producing sharp pulse signal
EP1005067A2 (fr) * 1998-11-26 2000-05-31 Sony Corporation Procédé de croissance d'un semiconducteur de type composé de nitrure III-V, fabrication d'un dispositif semiconducteur et dispositif semiconducteur
EP1005067B1 (fr) * 1998-11-26 2007-07-18 Sony Corporation Procédé de croissance d'un semiconducteur de type composé de nitrure III-V et fabrication d'un dispositif semiconducteur
FR3001578A1 (fr) * 2013-01-31 2014-08-01 New Imaging Technologies Sas Matrice de photodiode a zone dopee absorbant les charges
WO2014118308A1 (fr) * 2013-01-31 2014-08-07 New Imaging Technologies Matrice de photodiode a zone dopee absorbant les charges
US10068942B2 (en) 2013-01-31 2018-09-04 New Imaging Technologies Photodiode array having a charge-absorbing doped region

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EP0373752A3 (fr) 1990-08-16
JPH02159775A (ja) 1990-06-19
US4992386A (en) 1991-02-12
US5144381A (en) 1992-09-01

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