EP0371034A4

EP0371034A4 - Method and apparatus for data buffer management

Info

Publication number: EP0371034A4
Application number: EP19880905495
Authority: EP
Inventors: Kelly J. Beavers; E. Christopher Pisciotta
Original assignee: Exabyte Corp
Current assignee: Exabyte Corp
Priority date: 1987-07-02
Filing date: 1988-05-27
Publication date: 1993-02-24
Also published as: EP0371034A1; WO1989000312A1; JPH02504083A

Abstract

A data buffer management system (10) supervises the transmission of blocks of data between a first device (21), a data buffer (24), and a second device (26). In a write mode, blocks are transmitted to the second device (26) in an originally-intended sequence. If the second device (26) determines that a bad block was written thereto, the management system (10) rewrites the block in an alternate sequence. In a read mode, the management system (10) ignores bad blocks and duplicate blocks acquired from the second device (26) to transmit blocks of data to the first device (21) in the proper sequence.

Description

METHOD AND APPARATUS FOR

DATA BUFFER MANAGEMENT

BACKGROUND OF THE INVENTION

1. FIELD OF THE INVENTION This invention pertains to method and apparatus for managing the buffering of informational data between devices, such as the buffering of data between a host computer system and a peripheral storage device. 2. PRIOR ART AND OTHER CONSIDERATIONS.

As is well known, coded informational data is often transmitted in data blocks between a first device (such as a host computer) and a second device (such as a peripheral device which handles a storage medium) , with each data block having a fixed length such as a selected number of data bytes. Many modern peripheral devices have the capability of determining whether one or more errors occur in the transmission of a block of data between the devices, and of providing an indication that an erroneous or "bad" block has been transmitted.

As an example of the foregoing, some contemporary magnetic tape handling devices, e.g. "tape drives", are able to write a block of data during a first pass and then to read the just-written block during a second pass. Error detection circuitry associated with the tape handling device examines the block read during the second pass to determine whether the block as written on the storage medium is properly readable. If the block as read during the second pass is deemed by the error detection circuitry to contain errors, a signal indicative of the occurrence of the error is generated.

There are numerous reasons why a block of coded information may not be properly readable from a storage medium. One particularly acute reason is the presence of a defect in the storage medium. Although the block may be properly transmitted to the medium handling device for writing to a particular physical location on the medium, the medium may have a defect or blemish at that physical location which gives rise to an error. For example, upon the subsequent reading of the block written to the defective location, the defect may cause the block to be deemed erroneous or bad. Thus, as used herein a block is said to be erroneous or "bad" if the block is improperly written to a storage medium or if the block is not properly readable from a storage medium.

Quite often defects in a storage medium occur in patterns. For magnetic tape, for example, tape defects are often found to have an essentially horizontal pattern or grouping (e.g., the defect runs parallel to the direction of tape travel) .

In accordance with the prior art, upon the realization that a bad block was written at a particular physical location on a storage medium, an attempt is made to rewrite the block at the originally- intended physical location. Rewriting a block at the originally-intended physical location requires the interruption of the writing operation in order to relocate the originally-intended physical location. The relocation of the originally-intended physical location is particulary complicated and inefficient when dealing with sequential storage media such as magnetic tape. For relocation of a particular physical location on magnetic tape, the write operation must be temporarily terminated; the tape must be at least partially rewound; and the tape must be searched for the desired location before a block can be rewritten. After the block is rewritten, the tape must be advanced so that writing of further blocks can continue at their proper physical locations. In view of the foregoing, it is an object of the present invention to provide method and apparatus for rewriting blocks of coded data to a storage medium when the block, as initially or earlier written to the storage medium, has been determined to be bad. An advantage of the present invention is the provision of method and apparatus for controlling the physical locations on storage media whereat blocks are rewritten.

Another advantage of the present invention is the provision of method and apparatus for increasing the usable storage density of storage media without sacrificing data integrity.

A further advantage of the present invention is the provision of method and apparatus for reading a storage medium in a manner whereby rewritten blocks are properly considered in the transmission of data between devices.

SUMMARY A data buffer management system governs the transmission of blocks of data between a first device, a data buffer, and a second device. In one embodiment the first device is a host computer system, the second device is a storage medium-handling device, and the data buffer is a dynamic random access memory (DRAM) . The data buffer management system includes a micro-controller; "IPORT" circuitry for interfacing the first device with the management system; "DPORT" circuitry for interfacing the second device with the management system; and, circuitry for interfacing the data buffer with the management system. The transmission of data between the first device, the data buffer, and the second device is scheduled by the micro-controller in conjunction with sequencers included in both the IPORT circuitry and the DPORT circuitry.

The data transmission occurs on a buffer data bus which is connected to the first device, the data buffer, and the second device. Data transmission occurs in two modes. In a first mode, also known as an output or write mode, a block of data is transmitted from the first device to a memory location in the data buffer, and thence from that location in the data buffer to the second device. In a second mode, also known as an input or read mode, a block of data is transmitted from the second device to a memory location in the data buffer, and thence from that location in the data buffer to the first device.

The micro-controller uses the IPORT circuitry and the DPORT circuitry to generate the addresses of the particular memory locations in the data buffer involved in the transmission of a data block. Both the IPORT circuitry and the DPORT circuitry include, in addition to a sequencer, a set of registers and address generators. The set of registers includes a control register and a plurality of header registers. The header registers are employed, inter alia, in connection with the generation or retrieval of a block header which is included as part of the data block. The address generators included in the IPORT circuitry and the DPORT circuitry utilize information stored in the header registers in order to generate addresses for the particular memory locations in the data buffer at which the header associated with a data block and the data associated with the data block are to be stored. The gating of information between the various registers and generators is governed by the sequencer.

The micro-controller addresses the registers included in the IPORT circuitry and the DPORT circuitry for setting the contents of the registers. In addition to setting the contents of the header registers, the micro-controller circuitry sets the contents of the control register for each of the IPORT and DPORT circuits. In this regard, the sequencer included in each of the IPORT and DPORT circuits monitors the bits of the control register and performs various tasks in accordance with the status of those bits. One such task is the gating of information from the header registers to the address generators included in the interface circuitry (either IPORT or DPORT). In the write or output mode of operation, a data block is acquired from the first device and applied to the buffer data bus. The micro-controller sends information to the header registers comprising the IPORT so that a header can be generated for the data block. The micro-controller also sets bits in the IPORT control register to enable the IPORT sequencer to gate information from the IPORT header registers to the IPORT address generators. The IPORT address generators develop values correponding to the addresses in the data buffer at which the data block and the block header are to be stored. The IPORT sequencer then gates the block header to the address in the data buffer at which the block header is to be stored and applies the block data on the buffer data bus to the address in the data buffer at which the data is to be stored.

The micro-controller also schedules the transmission of the block of data from the data buffer to the second device so that the block is output in an originally-intended sequence to a channel associated with the second device. In this regard, the micro¬ controller puts the block identification number (BLOCK ID) of the block in a circular queue known as the READOUT queue. The data buffer management system is usable in connection with a second device of the type which is able to make a determination whether a block written thereto is a bad block. That is, the second device is capable of determining whether the data block was not properly written to the storage medium handled by the second device, or whether the block as written is not readable by the second device. In this regard, the second device provides a signal that the block just written was a bad block.

If the micro-controller receives an indication from the second device that the block just output to the channel associated with the second device was a bad block, the micro-controller reschedules the transmission of the block from its memory location in the data buffer so that the block is output in an alternate sequence to the second device. Rescheduling the transmission of the bad block involves re-entering the BLOCK ID of the bad block into the READOUT queue.

In an example wherein the second device is a tape drive, if the block were output to an originally- intended physical location and thereafter it were determined that the block was a bad block, the micro¬ controller reschedules the transmission of the block so that the block is also written at an alternate physical location on the tape which is not the orginally- intended location. In particular, the alternate physical location is chosen such that, if a tape defect occurred at the originally-intended physical location, it will not be likely that the same tape defect will extend to the alternate physical location. If, for example, a number M of blocks is written across the width of a tape, the number N of blocks written between the originally-intended physical location of the block and the alternate location is chosen such that N differs from M and is not related by an integer.

Separating the rewrite locations of a block in this manner results from re-entering the BLOCK ID of a bad block into a READOUT queue having a length suitable for storing N number of BLOCK IDs. In the read or input mode, DPORT header registers receive header information for a block and transmit the same to the micro-controller. The micro¬ controller examines the block header and determines whether the block is a valid block or an invalid (e.g. a duplicate) block. If the block is valid, the DPORT supervises transmission of the block to the data buffer and loads header data associated with the block into an allocation table. The allocation table has stored therein header data for every block currently stored in the data buffer. Thereafter the IPORT supervises the transmission of the block to the first (host) device.

The determination of whether a block is a duplicate block involves computing two parameters, DBID and DPID. The parameter DBID is the difference between a pointer Rptr (which points to the address in the buffer memory into which the most recently-acquired block has been written) and a pointer RDptr (which points to the address in the buffer memory from which the next-extracted block will be read) . The parameter PBID is computed by an equation that requires knowledge of a PHYSICAL BLOCK ID both for the block just acquired from the second device and for the next block to be transmitted to the host. These PHYSICAL BLOCK IDs are available from the DPORT header registers and the allocation table.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of a preferred embodiment as illustrated in the accompanying drawings in which reference characters refer to the same parts throughout the various views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention. FIG. 1 is a schematic view of a data buffer management system according to an embodiment of the invention;

FIG. 2 is a schematic view of a micro¬ controller included in the system of the embodiment of FIG. 1;

FIG. 3 is a schematic view of an interface port (IPORT) included in the system of the embodiment of FIG. 1;

FIG. 4 is a schematic view of a device port (DPORT) included in the system of the embodiment of FIG. 1;

FIG. 5A is a schematic view showing steps executed in a first stage of a write mode according to the invention; FIG. 5B is a schematic view showing steps executed in a second stage of a write mode according to the invention;

FIG. 6A is a schematic view showing steps executed in a first stage of a read mode according to the invention;

FIG. 6B is a schematic view showing steps executed in a second stage of a read mode according to the invention; FIG. 7 is a schematic view of steps executed to determine whether blocks of data obtained from a storage device used with the embodiment of FIG. 1 are valid blocks;

FIG. 8A is a schematic view of a READOUT queue which exists in a memory associated with the micro-computer of FIG. 2;

FIG. 8B is a schematic view of a BAD BLOCK queue stored in the memory of the micro-controller of FIG. 2; FIG. 8C is a schematic view of addresses included in a buffer memory connected to the management system of FIG. 1 and showing memory pointers when the invention is in a write mode;

FIG. 9 is a schematic view of addresses included in the buffer memory connected to the management system of FIG. 1 and showing memory pointers when the invention is in a read mode;

FIG. 10 is a schematic view illustrating a block of data on a magnetic tape; FIG. 10B is a table showing the format of a block header according to an embodiment of the invention;

FIG. 11 is a schematic view of blocks of data recorded on magnetic tape according to an embodiment of the invention; and, FIG. 12 is a schematic view depicting various memory locations of a random access memory included in the micro-controller of FIG. 2.

DETAILED DESCRIPTION OF THE DRAWINGS Fig. 1 shows a data buffer management system

10 comprising a micro-controller 12; a host interface port (IPORT) 16; a device port (DPORT) 18; and, a dynamic random access memory (DRAM) controller buffer interface 20. A first device, such as host computer system 21, is connected to the IPORT 16. A data buffer 24 is connected to the buffer interface 20. The data buffer 24 comprises a bank of DRAM chips configured as 256K by 9 bits wide. A second device 26, such as a helical scan tape drive, has a channel connected to the DPORT 18. A communication channel, disc drive, or other type device may be substituted for the tape drive as the second device 26. The first (host) device 21, the second device 26, and the data buffer management system 10 (including the buffer controller interface 20) are each connected to a bi-directional buffer data bus 28 and a buffer address bus 30. Priority access lines 31 and 32 connect the buffer interface 20 with the IPORT 16 and DPORT 18, respectively.

In the illustrated embodiment, the connection of the host device 21 to the host interface port

(IPORT) 16 is facilitated by a small computer system interface (SCSI) 22 included in system 21. The SCSI interface 22 is a conventional device such as a type WD33C93 SCSI chip manufactured by Western Digital, for example. The DRAM chips used in one embodiment are type 41256 RAM chips such as those manufactured by Texas Instruments. Such chips are fabricated as 256 K bytes by 1 bit wide and may be linked together to produce a 9 bit wide data bus. In the illustrated embodiment, 9 bits are used: 8 bits contain data while the 9th bit is used for parity checking.

The data buffer or buffer memory 24 (illustrated in Figs. 8C and 9) comprises 8K addresses whereat block header information is storable and 248K wherein block information is storable. The 248K are partitioned into 248 blocks, labelled blockO to block247 (Fig. 8C) . Each block contains 1024 bytes (IK) of memory. In the illustrated embodiment, IPORT 16,

DPORT 18 and buffer interface 20 are fabricated as a custom LSI chip. If desired, these functions can also be duplicated using discrete components. It should also be understood that alternative interface modules can be substituted for the SCSI interface 22 associated with the host 21 and that electrical hardware circuits can be substituted for the micro-controller 12 without affecting the scope of the invention.

Prior to discussing the structure of various components of the data buffer management system 10

(including the micro-controller 12, the IPORT 16, the DPORT 18, and the buffer interface 20), brief reference is made to Figs. 10A and 10B for an understanding of a storage medium format for an illustrative embodiment. Fig. 10A illustrates that a block of data is conceptualized as having a header 33 and informational data 34. In the illustrated embodiment, the header 33 comprises 16 bytes; the informational data 34 comprises 1024 bytes. The format of the header 33 for the illustrated embodiment is understood with reference to Fig. 10B.

STRUCTURE: MICRO-CONTROLLER The micro-controller 12 (Fig. 2) used in the illustrated embodiment comprises a microprocessor or CPU 36 (such as type 8032, 8-bit manufactured by Intel Corporation) ; an 8K by 8 bit random access memory (RAM) 38 (such as a type HM 6242 manufactured by Hitachi); and, a 16K by 8 bit programmable read only memory (PROM) 40 (such as a type 27128 manufactured by Intel Corporation). The microprocessor 36, RAM 38, and PROM 40 are connected inter alia by an internal data bus 42 and internal address bus 44.

The micro-controller 12 communicates with and controls the operation of the IPORT 16 and DPORT 18 using a control interface 45. Control interface 45 includes an external data bus 46 (8 bits); an external address bus 48 (8 bits); and, a plurality of other lines generally depicted by reference numeral 50. Examples of lines included in the group 50 are an address latch enable signal line; a chip select signal line; a write signal line; a read signal line; a reset signal line; interrupt signal lines; and interrupt acknowledge signal lines. These group 50 lines are connected to specific pins on the CPU 36. An address decoder built into the CPU 36 directs signals to registers of the IPORT 16 and DPORT 18.

STRUCTURES IPORT The IPORT 16 (Fig_* 3) comprises a plurality of header registers, including a "A" PAGE ID register 60; a "B" PAGE ID register 62; an "A" BLOCK ID register 64; a "B" BLOCK ID register 66; two DATA BYTE COUNT registers HI 68 and LO 70; and, three LOGICAL BLOCK ID registers HI, MD, LO, labelled 72,74,76, respectively. The IPORT 16 also comprises an IPORT sequencer 77; an IPORT data address generator 78; an IPORT header address generator 80; and, an IPORT control register 84. The registers included in IPORT 16 are connected to a plurality of busses, to be discussed below. The PAGE ID registers 60,62 are each 1 byte long and are used to inform the management system 10 of the size of the buffer memory 24. Valid values for this register are 0,1,2 or 3. With 256K memory, the register has a value of 0. If larger memory (i.e., 1 megabyte) is used for the buffer 24, the value in this register is adjusted to reflect which bank of 256K memory is being accessed. The correct memory page address is loaded by the micro-controller 12 into "A" PAGE ID register 60 and then transferred into "B" PAGE ID register 62 so as to increase the speed of the data buffer management system 10.

The BLOCK ID registers 64,66 are each 1 byte long and are used to construct the address of a block of data in the buffer memory 24. This value is written to the tape device 26 and tells the device 26 where in the buffer memory 24 to place data on a subsequent read operation of the device to the buffer. The "A" BLOCK ID register 64 is loaded by the micro-controller 12 and then transferred into "B" BLOCK ID register "B" 66 so as to increase the speed of the data buffer management system 10.

The DATA BYTE COUNT registers 68,70 total 10 bits. These registers inform the micro-controller 12 on a subsequent read operation of the device to the buffer how much data is in each 1024 memory block that is written to the device 26. If a data block is full, these registers contain the value 1024. If, for example, only 500 bytes of data are in a data block, the data byte count register 68,70 contains the value 500.

The LOGICAL BLOCK ID registers 72,74,76 total 24 bits and are used for logical operations of the buffer memory 24. For example, if the host 21 transfers data to the device 26 in 16K bytes per block segments, whereas the buffer memory 24 is arranged as IK blocks, the actual number of blocks per transfer is sixteen. The LOGICAL BLOCK ID registers 72, 74, 76 assign a unique number to this group of sixteen IK blocks to identify them as belonging to one 16K block of data received from the host 21. The next group of sixteen IK blocks received from the host 21 are then assigned another unique identifying LOGICAL BLOCK ID.

The IPORT header address generator 80 and the IPORT data address generator 78 generate buffer addresses for each data block, the blocks being labelled from blockO to block 278. The data address generator 78 generates a 20-bit value by concatenating the "B" BLOCK ID register 66 (in the most significant position) and the 10-bit value in the DATA BYTE COUNT registers 68,70.

The IPORT header address generator 80 generates a 20-bit value by concatenating of a string of five "l"'s (in bits 13 to 17), the value in the "B" BLOCK ID register 66, and a "0" (as the fourth bit).

Bits 18 and 19 of each generator selects which page of memory to use if more than 256K of memory is used for the buffer 24.

The IPORT control register 84 contains 8 bits which are used by the IPORT sequencer 77 to control the operation of the IPORT 16. The bits in the control register 84 are set by the CPU 36.

The format of the IPORT control register 84 will now be described. When FALSE, bit seven of control register 84 indicates that the system 10 is in read mode; otherwise bit seven indicates a write mode. When TRUE bit six enables the IPORT 16; when bit six is FALSE the IPORT 16 is disabled and reset. Bit five enables IPORT 16 to execute the mode (either read or write) specified by bit seven. Bit four is used to inform the CPU 36 of the status of the IPORT 16. Bit three informs the CPU 36 whether the IPORT 16 is busy or not. Bit two indicates when a parity error occurs. Bit one prevents data collision on the busses. That is, bit one determines whether the SCSI interface 22 and buffer memory 24 should have control of the buffer data bus 28, or whether control of the bus 28 should be given to the SCSI interface 22 and the CPU 36. Bit zero is used to .activate the buffer memory 24 after the management system's 10 power supply has stabilized. In this regard, when the management system 10 is initially turned on, the buffer memory is in a stand-by mode until the power supply stabilizes, at which point the memory 24 is activated. The IPORT sequencer 77 governs the timing of the execution of IPORT, particularly the timing of the gating of signals between various IPORT registers; between IPORT registers and the IPORT address generators 78,80; between the IPORT address generators 78,80 and the buffer address bus 30; and between the

IPORT registers and the buffer data bus 28. The IPORT sequencer 77 also receives indications from the host device 21 as to whether the host device 21 is requesting a block of data (in a read mode) or making a block of data available (in a write mode); apprises the micro-controller 12 of such indication (via an interrupt line included in the control interface 45); and, requests access to the buffer interface 20. The IPORT sequencer 77 thus comprises a plurality of switches and gates for performing the gating and signalling operations in the sequence and manner described herein. In view of the nature and sequence of IPORT operations described herein, the man skilled in the art will well understand how to connect gating and switch elements to accomplish the herein- described functions performed by the IPORT sequencer 77.

The IPORT sequencer 77 is shown in Fig. 3 as being connected by an IPORT sequencer communication bus 85 to each of the IPORT header registers, to the IPORT control register 84, and to the IPORT address generators 78,80. The IPORT sequencer 77 is also connected by an IPORT/SCSI communication bus 77a to the SCSI interface 22 and by an IPORT/BUFFER communication bus 77b to the buffer interface 20.

The control interface 45 from the micro¬ controller 12 is connected to the "A" PAGE ID register 60; "A" BLOCK ID register 64; DATA BYTE COUNT registers 68,70; LOGICAL BLOCK ID registers 72,74,76; and, the IPORT control register 84. The output of the "A" PAGE ID register 60 is connected to the input of the "B" PAGE ID register 62. Similarly, the output of the "A" BLOCK ID REGISTER 64 is connected to the input of the "B" BLOCK ID register 66. The use of both "A" and "B" registers permits quicker execution of the management system 10 as new data can be inputted into the "A" registers 60,64 while the "B" registers 62,66 handle current data.

The micro-controller 12 loads the "A" registers 60,64 and then instructs the IPORT 16, via bit 5 of the IPORT control register 82, to execute either a read or write function based on the status of bit 7 of the IPORT control registers. The IPORT sequencer 77 then gates the contents of the registers 60,64 to the registers 62,66, respectively. Since registers 60,64 are now empty, the micro-controller 12 can load therein new data, increasing the speed of execution. The output of the PAGE ID register 62 and BLOCK ID register 66 are connected to the IPORT data address generator 78 and to the IPORT header address generator 80 by lines 86,88 respectively.

The control interface 45 also supplies information to the DATA BYTE COUNT registers 68,70 and LOGICAL BLOCK ID registers 72,74,76. The output of these registers are connected to the above-described buffer data bus 28. The output of the DATA BYTE COUNT registers 68,70 are also connected to the IPORT data address generator 78 via lines 92,94, respectively. The output ports of the IPORT data generator

78 and the IPORT header address generator 80 are connected to the above-described buffer address bus 30. Bus 30 carries the IPORT-generated addresses to the buffer interface 20. STRUCTURE: DPORT

The DPORT 18 (Fig. 4) comprises a plurality of header registers, including two BLOCK TYPE ID registers 100,102; three PAGE ID registers 104,106,108; three BLOCK ID registers 110,112,114; two DATA BYTE COUNT registers 116,118; three LOGICAL BLOCK ID registers 120,122,124; and, six PHYSICAL BLOCK ID registers 126,128,130,132,134,136. In addition, the DPORT 18 includes a DPORT sequencer 137; a DPORT control register 140; a DPORT data address generator 142; and, a DPORT header address generator 144.

Of the registers included in DPORT 18, the PAGE ID; BLOCK ID; DATA BYTE COUNT; LOGICAL BLOCK ID registers; and, CONTROL register are similar to correspondingly-denominated registers in the IPORT 16 and thus their description is not repeated.

The BLOCK TYPE ID registers describe the attributes of a block. As shown in Fig. 10B, four bits of the BLOCK TYPE ID register are reserved for a retry count. One bit signifies the start of a logical flag. One bit signifies the end of a logical flag. The seventh bit is not used, while the eighth bit is always set to 1. During a write operation, the BLOCK TYPE ID registers are loaded with an 8-bit value by the micro-controller 12, which 8-bit value is later transferred as part of the header for recording onto the second device 26. During a read operation, these registers are loaded with a value received from the device 26 which may then be retrieved by the micro¬ controller 12. The PHYSICAL BLOCK ID registers describe the physical block location of data in the second device 26. During a write operation, the PHYSICAL BLOCK ID registers are loaded with a 24-bit value by the micro¬ controller 12, which value is later transferred as part of the header to the device 26. During a read operation, these registers are loaded with a value received from the device 26 which may then be retrieved by the micro-controller 12.

The DPORT control register 140 is connected to the control interface 45 and by line 32 to the buffer interface 20. The format and function of the DPORT control register 140 is analogous to that of the IPORT control register 84, it being understood that the DPORT control register 140 concerns the operation of DPORT elements rather than analogously-denominated IPORT elements.

A device read header bus 146 connects the second device 26 with DPORT registers 100,104,110,116,118,120,122, 124,126,128 and 130. Under control of the DPORT sequencer 137, the bus 146 serves to load these registers with information from the block header obtained from the device 26. The output ports of the registers are connected to the control interface 45. The BLOCK ID register 110 and the PAGE ID register 104 are also connected to the DPORT data address generator 142 via line 147A and 147B, respectively.

The control interface 45 is also connected to the BLOCK TYPE ID register 102; the "A" PAGE ID register 106; the "A" BLOCK ID register 112; and,

PHYSICAL BLOCK ID registers 132,134,136. As with the IPORT 16, the output of the "A" PAGE ID register 106 is connected to the "B" PAGE ID register 108 and the output of the "A" BLOCK ID register 112 is connected to the "B" BLOCK ID register 108 for the purpose of facilitating the operation of the management system 10.

The output of registers 102,108,114,132,134 and 136 are connected to a device write header bus 148. The device write header bus 148 is connected to the device 26 so that certain header information carried on bus 148 can be written as part of a block, header (Fig. 10) to a storage medium (such as a magnetic tape) handled by the second device 26. The output of the "B" PAGE ID register 108 is also connected to the DPORT data address generator 142 and to the DPORT header address generator 144 via line 150. Similarly, the output of the "B" BLOCK ID register 114 is connected to the DPORT data address generator 142 and to the DPORT header address generator 144 via line 152.

The DPORT sequencer 137 functions in an analogous manner as does IPORT sequencer 77. That is, the DPORT sequencer 137 examines the bits in the DPORT control register 140 and governs the timing of the execution of DPORT 18 based on those bit settings, particularly the timing of the gating of signals between various DPORT registers; between DPORT registers and the DPORT address generators 142,144; between the DPORT address generators 142,144 and the buffer address bus 30; between DPORT registers and the device write header bus 148; and between the device read header bus 146 and the DPORT header registers. The DPORT sequencer 137 also receives indications from the second device 26 as to whether the second device 26 is requesting a block of data (in a write mode) or make a block available (in a read mode); apprises the micro¬ controller 12 of such indications (via an interrupt line included in the control interface 45); and, requests access to the buffer interface 20. Like the IPORT sequencer 77, the DPORT sequencer 137 comprises a plurality of switches and gates for performing the signalling and gating operations in the sequence and manner described herein. In view of the nature and sequence of the DPORT operations described herein, the man skilled in the art will well understand how to connect the gating and switch elements to accomplish the herein-described function performed by the DPORT sequencer 137.

The DPORT sequencer 137 is shown in Fig. 4 as being connected by a DPORT sequencer communication bus 155 to each of the DPORT header registers, to the DPORT control register 140, and to the DPORT address generators 142,144. The DPORT sequencer 137 is also connected by a DPORT/DEVICE communication bus 137a to the second device 26 and by a DPORT/BUFFER communication bus 137b to the buffer interface 20. STRUCTURE: BUFFER INTERFACE The DRAM controller buffer interface 20 (Fig. 1) is capable of simultaneously interfacing in an asynchronous mode of operation with the IPORT 16 and DPORT 18. The buffer interface 20 is responsible for several functions including the determination of the priority of processing simultaneous requests. The buffer interface 20 determines which request is to be processed first and acts accordingly to allow one operation to precede the other. The buffer interface 20 also performs a memory refresh operation DRAM chips comprising buffer 24 when memory accesses are not occurring with respect to the IPORT 16 or DPORT 18. The buffer interface 20 is also responsible for turning on a write enable pin to the buffer memory 24, and for activating address strobes associated with the DRAM memory 24.

The buffer interface 20 is connected to the buffer address bus 30 and to the bi-directional buffer data bus 28. The buffer address bus 30 connects the buffer interface 20 to the address generators 78,80 of the IPORT 16 and to the address generators 142,144 of the DPORT. The buffer data bus 78 connects the buffer interface 20 to the IPORT 16, to device 26, and to the SCSI port 22 included in the host 21.

The buffer memory 24 is divided into 8K addresses whereat block header information is storable and 248K addresses wherein block informational data is storable. The 248K addresses are logically partitioned into 248 segments of 1,024 (IK) bytes each, which segments have loaded therein the blocks labelled blockO through block 247. The addresses of the buffer memory are managed by the IPORT address generator 78,80 and DPORT address generators 142,144.

OPERATION: OVERVIEW Data transmission occurs in two modes, each mode having two stages. In a first mode, also known as an output or write mode, a block of data is transmitted in a first stage from the first device 21 to a memory location in the data buffer 24, and thence in a second stage from the location in the buffer 24 to the second device 26. In a second mode, also known as an input or read mode, a block of data is transmitted in a first stage from the second device 26 to a memory location in the data buffer 24, and thence in a second stage from that location in the data buffer 24 to the first device 21.

In the write mode, header data generated in the micro-controller 12 is transferred on control interface 45 to the IPORT header registers. Under the control of IPORT sequencer 77, data stored in various ones of the IPORT 16 header registers is gated to The IPORT address generators 78,80 for the generation of a buffer data address data and a buffer header address.

The IPORT sequencer 77 also supervises the construction of a block header by gating the information in the IPORT 16 header registers, in a predetermined sequence, to the buffer data bus 28 to the address generated by the IPORT header address generator 80. Block informational data from the host device 21 is applied on the buffer data bus 28 to the address generated by the IPORT data address generator 78. Thus, informational data and header information for each data block is stored in the buffer memory 24.

During a second stage of the write mode, a block of data is transferred from physical addresses within the buffer memory 24 to the device 26 over the buffer read data bus 28. The DPORT header address generator 144 generates the address in buffer memory 24 from whence the block header is extracted; the DPORT data address generator 142 generates the address in buffer memory 24 from whence the block informational data is extracted. The block is written in an originally-intended sequence to the second device 26. If the block is determined to be a "bad" block, the block is rewritten in an alternate sequence.

A plurality of blocks must undergo write mode first stage processing before the second stage of the write mode commences. In this regard, N number of blocks must undergo the write mode first stage processing to esentially "prime" the management system 10. As a result of the priming, N number of BLOCK IDs are entered into a circular READOUT queue 184 (maintained in RAM 38) at addresses specified by a revolving pointer RDQwr. Once the READOUT queue 184 has been filled to capacity with the N number of BLOCK IDs, the second stage of the write mode can commence. During the second stage of the write mode, BLOCK ID values are extracted from locations in the READOUT queue 184 pointed to by a revolving pointer ROQrd. Thus, after the priming of the system 10, the system 10 executes the first stage of the write mode for a block must recently acquired from the host 21 at about the same time the system 10 is executing the second stage of the write mode for another block earlier acquired from the host 21.

In a first stage of the read mode, block header information is transferred from the device 26 over the device read header bus 146 and stored in the header registers of the DPORT 18. The contents of these header registers are applied to the micro¬ controller 12 via the control interface 45. The micro¬ controller 12 examines the block header information associated with each received block and determines whether the block is valid, e.g. determines that the block is not a duplicate block. The micro-controller 12 also stores the block header information for valid blocks in an allocation table in RAM 38. Invalid blocks are not transmitted to the data buffer 24. Block informational data for valid blocks is transferred directly from the device 26 to the buffer memory 24 and stored at physical addresses therein as specified by the DPORT Data Address Generator 142. In a second stage of the write mode, block informational data from the data buffer 24 is applied to the buffer data bus 28 for transmission to the first (host) device 21.

OPERATION: WRITE MODE

In the write mode, data is transferred from the host 21 to the device 26 in two stages. In a first stage, a block is transferred from the host 21 and stored temporarily in the buffer memory 24. In a 0 second stage, a block is read from the buffer memory 24 and transferred to the device 26. Steps associated with the write mode of the invention are shown in Figs. 5A and 5B.

It should be recalled that the first N number -*-⁵ of blocks are used to prime the management system by filling up the N-capacity READOUT queue 184, and that such priming must occur prior to commencement of the second stage of the write mode. In the illustrated embodiment, N has the value 11. In the ensuing

20 discussion, it is assumed that the priming has already been completed (by steps understandable from the ensuing discussion) and that the N number of BLOCK IDs have been entered into READOUT queues and the pointer ROQwr has been incremented accordingly. Thus, in the

25 ensuing discussion of the write mode, the two stages of the write mode can occur concurrently for different blocks.

As informational data enters the management system 10 through the SCSI Module Interface 22. The

30 data is divided into IK byte blocks in preparation for storage in the buffer memory 24 (see step 202 of Fig. 5A) . Each block becomes associated with header information including a sequential BLOCK ID. BLOCK IDs are numbered 0 through 247, corresponding to the 248 memory segments available in the data buffer 24. The BLOCK ID is generated by the micro-controller 12.

For each block of data, the micro-controller 12 generates data for the IPORT header registers and the IPORT control register 84 (step 204), including the BLOCK ID and PAGE ID data. This data is applied (at step 206) to the IPORT header registers and the IPORT control register 84 on the control interface 45. The BLOCK ID data and PAGE ID data are applied to the "A" BLOCK ID and to the "A" PAGE ID registers 60 and 64, respectively.

The IPORT sequencer 77 thereafter takes over the supervision of IPORT functions. At step 208 the sequencer 77 directs that data in "A" registers 60 and 64 be gated into respective "B" registers 62 and 66.

At step 210 the sequencer 77 gates data from the IPORT header registers 62 and 66 into the IPORT header address generator 80 and data from the IPORT header registers 62, 64, 68, and 70 into the IPORT data address generator 78. At step 212 the generators 80 and 78 generate values corresponding to the addresses in the data buffer 24 whereat the block data and the block header associated with the block are to be stored. At step 214 the sequencer 77 gates the header address generated by the IPORT header generator 80 to the buffer interface 20 via buffer address bus 30.

At step 216 the sequencer 77 gates the contents of IPORT registers 68,70,72,74 and 76 to the data buffer controller buffer interface 20 via the buffer data bus 28. The sequencer 77 gates the IPORT registers in a predetermined order as dictated by a pre-established header format such as that depicted in Fig. 10B. At step 218 the sequencer 77 gates the data address generated by the IPORT address generator 78 to the buffer interface 20 via the buffer address bus 30. At step 220 the block data from the first (host) device 21 is loaded into the buffer interface 20 via the buffer data bus 28.

The buffer interface 20 uses the header address generated by IPORT address generator 80 and the block data address generated by IPORT address generator 78 to write the block header and block data into the data memory 24 in the manner depicted by Fig. 8C. As mentioned before, block headers are stored in memory locations addressable in the last 8K of the memory 24, while the block data is stored in partitioned segments (iκ each) in a lower 248K of memory 24. The block data is written into the DRAM comprising the buffer memory 24 at the address pointed to by the pointer WRptr, which pointer WRptr is related to the address generated by the IPORT data address generator 78. The IPORT 16 continues to accept blocks from the SCSI Module Interface 22, to associate Block IDs with each block, and to store the blocks and headers in the buffer memory 24 in sequence to the BLOCK ID (BLOCK IDs sequence from 0,1,2...246,247,0,1,2, ..., 246,247,...) until the buffer 24 is full. A 'Buffer Full' condition exists when there are no unused Block IDs available, which occurs when there are no unused segments in the buffer memory 24. The Buffer Full condition causes the SCSI interface 22 to suspend data input until sufficient buffer space is available.

In the second stage of the write mode (depicted in Fig. 5B) when the second device 26 requests a block of data from the buffer management system 10, the micro-controller 12 increments the pointer ROQrd associated with the READOUT queue 184 maintained in RAM 38 (step 232). The pointer ROQrd is used to point to the BLOCK ID for the next block scheduled to be transmitted from the data memory 24 and the second device 26. Just after the system 10 has been primed, for example, the value of ROQrd will be "1" to point to the first block acquired from the host 21.

The micro-controller 12 generates data for the DPORT header registers and the DPORT control register 140 (step 234), including the BLOCK ID and PAGE ID data. This data is applied (at step 236) on the control interface 45 to the DPORT header registers and the DPORT control register 140. The BLOCK ID data and PAGE ID data are applied to the "A" BLOCK ID and to the "A" PAGE ID registers 106 and 112, respectively.

The DPORT sequencer 137 thereafter takes over the supervision of DPORT functions. At step 238 the sequencer 137 directs that data in "A" registers 106 and 112 be gated into respective "B" registers 108 and 114. At step 240 the sequencer 137 gates data from the DPORT header registers 108 and 114 into the DPORT header address generator 144 and data from the DPORT header registers 108 and 114 into the DPORT data address generator 142. At step 242 the generators 144 and 142 generate values corresponding to the addresses in the data buffer 24 whereat the block data and the block header associated with the block are stored.

At step 244 the sequencer 137 gates the header address generated by the DPORT header generator 144 to the buffer interface 20 via buffer address bus 30. At step 246 the buffer interface applies to the buffer data bus 28, and thus to second device 26, the partial block header obtained from a location corresponding to the address generated by the DPORT generator 144. At step 247 the sequencer 137 gates the remainder of the block header to the second device on the device write header bus 148.

At step 248 the sequencer 137 gates the data address generated by the DPORT address generator 142 to the buffer interface 20 via the buffer address bus 30. At step 250 the block data from the buffer interface 20 is applied to the second device 26 via the buffer data bus 28. The block data is extracted from the DRAM comprising the buffer memory 24, particularly from the address pointed to by the pointer RDptr, which pointer RDptr is related to the address generated by the DPORT data address generator 142 (see Fig. 9). The second device 26 then writes the entire block including the block header to the storage medium handled thereby. The device 26 reports back to the micro¬ controller 12 whether each block of data was processed correctly. If a block is processed correctly by the second device 26 (as determined at step 252), the address in the buffer memory 24 from which the block was extracted can be written over by another block received from the first (host) device 21. This ultimately occurs at step 253 by incrementing the pointer ROQwr and entering the BLOCK 10 of the block most recently transmitted from the host 21 to the buffer interface 2D into the READOUT queue 184.

If a block is not processed correctly, i.e., it is determined (at step 252) to be a bad block (for example, due to a recording or transmission error), the address in the data buffer 24 from which the block was extracted cannot yet be written over by another block received from the first device 21. To this end, at step 254 the BLOCK ID of the bad block is placed into a BAD BLOCK queue 186 if it has not already been so. Moreover, at step 256 the pointer ROQwr is incremented and the BLOCK ID of the bad block is re-entered into the READOUT queue at the location now pointed to by ROQwr. The BAD BLOCK queue 186 is located in RAM 38 of the micro-controller 12 (see FIG. 12). BLOCK IDs of bad blocks are only once entered into the BAD BLOCK queue 186, but can be repeatedly entered into the READOUT queue if necessary.

After "bad" blocks are written into the second device 26, the bad blocks are not recalled or erased as in prior art devices, but are instead, later rewritten, a plurality of times if necessary, at alternate physical locations on the storage medium. The rewritten blocks are identified with a Retry Count that is incremented each time the block is rescheduled in the READOUT queue until either the device 26 processes the block correctly or a maximum permissible number of retries is exceeded.

In the illustrated embodiment, the device 26 is a helical-scan magnetic tape recorder wherein blocks are written in helical stripes as shown in Fig. 11. In accordance with the present invention, rewritten blocks are scattered across a tape 170 to avoid tape defects which tend to lie in horizontal patterns in the direction of the tape travel. A tape format of M number of blocks per helical stripe is employed, where M=8. Accordingly, in order to avoid a tape defect pattern, the bad block should be rewritten N number of blocks away from its originally-intended physical location. In the illustrated embodiment N has the value 11 or greater, and more preferably that N be exactly 11 so that the alternate location will be 11 blocks away from the originally-intended location of the block. This combination insures that rewritten bad blocks will be positioned at least three blocks over from the previous copy of the bad block, reducing susceptibility to common tape defects. With other tape formats other combinations of parameters are usable.

In Fig. 11, blocks 1 through 4 inclusive were successfully processed by the second device 26. Block 5 is a bad block as indicated by shading in Fig. 11B. Thus, block 5 must be retransmitted to the tape 170 for writing at an alternate physical location. In order to rewrite a block such as block 5 of Fig. 11, the BLOCK ID for block 5 is re-entered into the READOUT queue 184 and entered into BAD BLOCK queue 186 in the manner aforedescribed. Block 6 to Block 15 are then processed onto original block locations 6 to 15. The next original block location (location 16) is separated eleven blocks from the bad original block 5. The contents of block 5 are retrieved from the buffer 24 and re-recorded on the tape 170 at physical position 16. Physical position 16 is thus referred to as an alternate physical location of block 5. If block 5 is successfully retransmitted, it is removed from the BAD BLOCK queue 186. This process repeats for the entire data transfer operation. Whenever a bad block is detected, it is re-recorded at an alternative location which, in the illustrated embodiment, is eleven blocks away from its originally-intended bad block location. BLOCK IDs and Retry Counts may be entered into the BAD BLOCK queue 186 until it is full, which causes the micro-controller 12 to temporarily suspend the data flow output from the buffer memory 24 until the bad blocks are correctly processed by the device 26.

Bad blocks are removed from the BAD BLOCK queue 186 when they are correctly processed by the device 26, which may not be the same order as the order in which the bad blocks occurred. In cases where bad blocks are removed from the middle of the queue, the queue is compressed to fill the space left after the bad block was removed.

The BAD BLOCK queue 186 also controls which buffer segments may be written by the IPORT 16, since bad blocks cannot be removed from the buffer 24 or overwritten by new blocks until the bad blocks are correctly processed by the device.

The WRITE operation is complete when the READOUT queue 184 is empty and all bad blocks have been removed from the BAD BLOCK queue 186. A completed WRITE operation is indicated to the device 26 by an ^•Out of data' signal, which terminates the transmission of a block to the device 26.

OPERATION: READ MODE In the read mode, blocks of data are transferred from the device 26 to the host 21 in two stages. In the first stage, a block of data is read from the device 26 and temporarily stored in the buffer memory 24. In the second stage, a block of data is removed from the buffer memory 24 and transferred to the SCSI Module Interface 22 associated with the host 21. As a block is successfully written to the host 21, the block is removed from the buffer memory 24, which vacates the addresses occupied by the block for receiving additional data from the device 26. Steps associated with the read mode are depicted in Figs. 6A and 6B.

In the read mode, blocks of data are streamed from the second device 26 into the buffer 24 in the order that the blocks are stored on the device 26. As a result of the ability of the data buffer management system of the present invention to rewrite blocks such as bad blocks, blocks may not be stored in strict BLOCK ID sequence on the storage medium. As shown in Fig. 11, blocks stored on the helically-recorded tape 170 may be out of sequence as a result of interleaved bad data blocks, good data blocks, and rewritten blocks. Prior to transmission to the first device 21 the blocks must be placed into a correct sequence regardless of the order in which they were read from the storage medium.

As used herein, a "valid" block is a block of data obtained from the storage medium which is transmissable to the data buffer 24 and from thence to the first (host) device 21. Thus, neither "bad" blocks or duplicate blocks are considered to be valid blocks.

In the above regard, one or more duplicates of a block can appear on the storage medium without the duplicate blocks necessarily being bad blocks. The second device 26 includes an error detector which detects the transmission of a suspected "bad" block to the device 26 during a write operation. The error detector included with the device 26 also communicates to the data buffer management system the occurrence of an error during a read operation. The threshold criteria employed by the error detector for evaluating whether a block is bad is more stringent for a write operation than for a read operation. Accordingly, the error detector of device 26 may require that a block to be rewritten several times before the more stringent error criteria is met. Yet, during a subsequent read operation, the error detector of device 26, using a less stringent error criteria, may consider many of the rewritten blocks as good blocks rather than bad blocks. Hence, the plurality of rewritten good blocks are duplicate blocks which should not be transmitted to the buffer 24 nor to the host device 21.

Valid data blocks are temporarily stored in the buffer memory 24 until processed by the IPORT 16. By providing temporary buffer storage and real-time processing of data blocks read from the device 26, the data blocks can be restored to the correct order without frequent interruptions of the read process. To begin the first stage of the read mode, at step 258 the DPORT sequencer 137 receives a signal from the second device 26 that a block of data is available. If the DPORT 18 is ready to handle a new block from the second device, i.e. if the DPORT 18 is finished writing the previous block to the data buffer 24, the DPORT sequencer 137 informs the micro¬ controller 12 that a new block is to be processed (step 260).

As a data block arrives from the device 26, at step 262 (see Fig. 6A) its associated header is transmitted on the device read header bus 146 for storage in the appropriate DPORT 18 registers.. In this regard, the DPORT sequencer 137 gates information into the header registers comprising the DPORT in a predetermined order in accordance with the pre- established format of the header (see FIG. 10B) . At step 264, the block header information is transmitted to the micro-controller 12.

The micro-controller 12 examines the data from these registers and, in the manner hereinafter described (with reference to Fig. 7), at step 266 determines whether the current data block is valid.

If a block is valid, at step 268 the micro¬ controller applies data to the DPORT control register 140. The DPORT sequencer 137 examines this register for instructions as to how the sequencer 137 is to govern the DPORT functions.

The DPORT sequencer 137 thereafter takes over the supervision of DPORT functions. At step 272 the sequencer 137 gates data from the DPORT header registers 110 and 104, into the DPORT data address generators 142 and 144. At step 274 the generator 142 generates values corresponding to the addresses in the data buffer 24 whereat the block data is to be stored. At step 276 the sequencer 137 gates the data address generated by the DPORT address generator 142 to the buffer interface 20 via the buffer address bus 30. At step 278 the buffer interface receives the block data information applied on the buffer data bus 28 and stores the same at the location corresponding to the value generated by the DPORT data address generator 142, which address corresponds to the pointer WRptr shown in Fig. 9.

As a block is written into the data buffer 24 in the manner aforedescribed at step 280, the micro¬ controller 12 enters BLOCK ID and other header information (including BLOCK PHYSICAL ID) with that block into an allocation table 281 maintained in RAM 38. The allocation table 281 contains header data for every block currently stored in the data buffer 24, including the BLOCK ID and PHYSICAL BLOCK ID values. Thus, as shown in FIG. 12, the allocation table 281 contains header information for 248 blocks.

In the second stage of the read mode, the first device 21 requests a block of data, which request is received at step 302 by the IPORT sequencer 77. At step 304 IPORT sequencer 77 informs the micro¬ controller 12 that the host device 21 has requested further data from the buffer management system 10. At step 306 the micro-controller 12 obtains the next BLOCK ID for the next block. The next BLOCK ID is obtained by searaching the allocation table 281 and selecting therefrom the next BLOCK ID corresponding to the next value in an increasing monotonic sequence. The micro-controller 12 generates data for the IPORT header registers and the IPORT control register 84 (step 308), including the BLOCK ID and PAGE ID data. This data is applied (at step 310) to the IPORT header registers and the IPORT control register 84 on the control interface 45. The BLOCK ID data and PAGE ID data are applied to the "A" BLOCK ID and to the "A" PAGE ID registers 60 and 64, respectively.

The IPORT sequencer 77 thereafter takes over the supervision of IPORT functions. At step 312 the sequencer 77 directs that data in "A" registers 60 and 64 be gated into respective "B" registers 62 and 66. At step 314 the sequencer 77 gates data from the IPORT header registers 62,64,68, and 70 into the IPORT data address generator 78. At step 316 the generator 78 generates a value corresponding to the addresses in the data buffer 24 whereat the block data associated with the block is stored. This value corresponds to the pointer RDptr. At step 318 the sequencer 77 gates the data address generated by the IPORT address generator 78 to the buffer interface 20 via the buffer address bus 30. At step 320 block data from the buffer interface 20 is applied to the first device 21 via the buffer data bus 28.

As mentioned before, as blocks arrive from the device 26 the micro-controller 12 determines whether the block is valid, i.e. whether the block belongs to a current buffer BLOCK ID group. Valid blocks are stored, whereas invalid blocks are immediately discarded.

Fig. 7 represents a flow chart of the steps performed to determine whether blocks obtained from the device 26 are valid. The micro-controller 12 first examines the buffer read address pointer RDptr and buffer write address pointer WRptr to produce a difference value DBID (Step 350). At step 351 the micro-controller 12 computes a physical distance DPID, the equation for which is discussed below. At Step 352 the difference value DBID is compared to a constant Buffer threshold, BTHRESH. An equation for calculating BTHRESH is discussed below. This comparison at step 352 determines the relative "distance" between the current IPORT BLOCK ID read position and the BLOCK ID of the block in question. If the value DBID is less than BTHRESH, the block belongs to a group of blocks currently undergoing processing (i.e. the current Buffer BLOCK ID Group). If the block is in the current group, the micro-controller 12 checks at step 353 whether the data buffer 24 is currently full.

The buffer 24 is full if the physical distance DPID is greater than or equal to a Maximum Buffer Block ID (MAXBUFID) . When the buffer 24 is full, the micro-controller 12 halts the device 26 read operation while the host 21 continues to remove data from the buffer 24 (Step 354). When sufficient space is available in the buffer 24, the read operation is resumed. At Step 356 the micro-controller 12 determines whether the block has already been stored in the buffer 24 by examining the allocation table 281 maintained in RAM 38. If the block has already been stored, then it is a redundant copy and is discarded (Step 358). Otherwise the block is stored in the data buffer 24 (step 360).

At step 362 the micro-controller 12 compares the value of BTHRESH with the physical distance DPID (the equation for which is given below). If this physical distance DPID is greater than or equal to BTHRESH, the block in question is a new block ahead of the current buffer read address pointer RDptr and Buffer Block ID Group. In this case, at Step 364 the micro-controller 12 examines the allocation table 281 in RAM 38 to determine whether the block has already been stored in the data buffer 24. If the block has been stored, it is discarded (step 358); otherwise it will be stored in the buffer 24 (step 360).

If at Step 362 it is determined that the physical distance DPID is less than BTHRESH, then the block is behind the current buffer read address pointer RDptr. In this case the block in question is a redundant copy of a block within the current Buffer Block ID Group, and is discarded (Step 358).

Since copies of data blocks can be rewritten many times at intervals determined by the retry schedule queue length, the physical distance DPID must be adjusted by the block's Retry Count to reflect the PHYSICAL BLOCK ID of the original copy. An equation for calculating the physical distance DPID is:

DPID = (DPORT PHYSICAL BLOCK ID) - (IPORT PHYSICAL

BLOCK ID) - K

where K = (Block Retry Count) x N, where N is the length of the READOUT queue.

Likewise, the value BTHRESH must be determined such that multiple copies of blocks within the current Buffer Block ID Group are properly identified as belonging to that group. The value of BTRHESH is determined by substracting a Maximum Block Offset (MBO) from a Maximum BLOCK ID. An equation for calculating BTHRESH is: BTHRESH = (Maximum BLOCK ID) - (Maximum Block Offset)

where MBO=[(Maximum Retry Number) x (N-l)].

In the illustrated embodiment, N=ll, the Maximum Retry Count is 12, and Maximum Block ID is 248 (actual physical values range from 0 through 247). Thus, a BTHRESH value of 128 is used.

Data is read out of the buffer memory 24 until the host 21 request is satisfied or a "Buffer

Iff Empty" condition is detected. A "Buffer Empty" condition exists when the micro-controller 12 requires the next BLOCK ID to schedule into the IPORT 16 registers and there are no segments in the buffer memory 24 containing data. This condition will cause ¹⁵ the SCSI interface 22 to suspend data output to the host 21 until a sufficient amount of data is available in the buffer memory 24.

While the invention has been particularly shown and described with reference to the preferred

20 embodiments thereof, it will be understood by those skilled in the art that various alterations in form and detail may be made therein without departing from the spirit and scope of the invention.

Claims

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. Apparatus for transmitting blocks of data between a first device and a second device, said second device being of a type that handles input/output operations with respect to a data channel and obtains an indication whether blocks are output on said data channel as bad blocks, said apparatus having scheduling means for scheduling the transmission of blocks of data between said first and said second device, said apparatus being characteri zed in that said scheduling means transmits blocks in an originally- intended sequence position to said second device and retransmits a bad block in an alternate sequence position other than said ori ginally- intended sequence position , and wherein said scheduling means transmits non-duplicative good blocks of data from said second device to said first device in a sequence uti lizable by said first device.

2. Apparatus for transmitting a block of data from a first device to a second device, said second device being a type of device that handles at least output operations to a data channel , said apparatus compri sing: a buffer having a plurali ty of addressable memory locations; data bus means for transf erring data from said first device to said buffer and f rom said buffer to said second device; means for scheduling the transmission of a block of data from said fir st device to a memory location in said buff er and from said memory location in said buffer whereby said block is output in an 5 originally-intended sequence position to said channel; means for receiving an indication whether said block output in its originally-intended sequence is a bad block; and, means for scheduling the retransmission of ^ said block f om said memory location in said buffer to said second device if said block is a bad block, said transmission occurring in a manner whereby said block is also output in an alternate sequence position other than said originally-intended sequence position for 5 said block.

3. The apparatus of claim 2, wherein said data channel is associated with a storage medium, wherein said second device handles write operations to said storage medium, wherein said originally-intended sequence

5 position is an originally-intended physical location for said block on said storage medium, wherein said alternate sequence position is an alternate physical location on said storage medium, and wherein said means for scheduling the retransmission of said block 0 determines said alternate physical location in a manner whereby said alternate physical location is sufficiently distanced physically from said originally- intended physical location such that, if any defect should occur at said originally-intended physical 5 location, said defect is not likely to occur at said alternate physical location.

4. The apparatus of claim 2, wherein each block transmitted from said first device to said second device has a block identifiction number associated therewith, wherein said means for scheduling the

5 transmission of a block from said buffer to said second device includes a readout queue whe rein are storable block identi fi cation numbers for blocks awaiting transmiss ion to said second device, and wherein said means for scheduling the transmission of a block f rom said buffer to said second device uses said readout queue to determine what block is next to be transmitted to said second device.

5. The apparatus of claim 4, wherein said means for scheduling the retransmiss ion of said block f rom said buffer to said second device includes a bad block queue wherein are storable block identi fication number s for those blocks cons idered by said second device to be bad blocks, and whe rein said means for scheduling the retransmission of said block enters block identi fication numbers f rom said bad block queue into locations in said readout queue in a manner whereby the transmission of a block associated with a block identi fi cation number from said bad block queue will cause the writing of said block to occur at an alternate physical location on said storage med ium whi ch is suf ficiently distanced f rom said ori ginally- intended physical location that any def ect occurring at said originally- intended physical location is not likely to occur at said alternate physical location .

6. Apparatus for transmitting a block of data to a first device from a second device, said second device being a type of device that handles at l east input operations from a data channel , said apparatus compris ing: a buffer having a plurali ty of addressabl e memory locations; data bus means for transf erring a block of data f rom said second device to said buffer and f rom sa id buffer to said fi rst device ; means for determining whether a block of data obtained by said second device is a duplicate of a previously-transmitted block of data; means for scheduling the transmission of a block of data from said second device to a memory location in said buffer so long as said block is not a duplicate block; and, means for scheduling the transmission of a block of data from said memory location in said buffer to said first device in a manner whereby said block is received in an expected sequence by said first device.

7. The apparatus of claim 6, further comprising: means for receiving an indication from said second device of whether a block of data obtained by said second device is a bad block; and wherein said means for scheduling the transmission of a block of data from said second device to a memory location in said buffer effects said transmission so long as said block is neither a duplicate block nor a bad block.

8. The apparatus of claim 7, wherein said data channel is associated with a storage medium; wherein said second device handles read operations from said storage medium; wherein each block obtained by said second device from said storage medium has a physical block identification number associated therewith which is indicative of a physical location on said storage medium from whence said block was obtained; and, wherein said means for determining whether a block of data obtained by said second device is a duplicate block utilizes the physical block identification number associated with a newly-obtained block. 9. The apparatus of claim 8 , wherein said means for determining whether a block of data obtained by said second device is a duplicate block comprises means for comparing the physical block identi fi cation number associated with the most newly-obtained block with and the physical block identi fi cation number associated with the block most recently transmitted to the first device.

10. A method for transmitting blocks of data between a first device and a second device, said second device being of a type that handles input/output operations with respect to a data channel and obtains an indication whether blocks are output on said data channel as bad blocks, said method including the scheduling of the transmission of blocks of data between said fir st and said second device, said method being characteri zed by the transmission of blocks in an originally- in tended sequence position to said second device and the retransmission of a bad block in an alternate sequence pos ition other than said ori ginally- intended sequence position , and by the transmission of non-duplicative good blocks of data f rom said second device to said first device in a sequence utili zable by said first device.

11. A method for transmitting a block of data from a first device to a second device, said second device being a type of device that handles at least output operations to a data channel , said method compris ing the steps of : providing a buffer having a plurali ty of addressable memory locations; providing data bus means for transf erring data f rom said fir st device to said buffer and f rom said buffer to said second device; scheduling the transmission of a block of data from said first device to a memory location in said buffer and from said memory location in said buff er whereby said block is output in an originally- intended sequence position to said channel; receiving an indication whether said block output in its originally- in tended sequence position is a bad block; and , scheduling the retransmission of said block from said memory location in said buffer to said second device if said block is a bad block, said transmission oc curing in a manner whereby said block is also output in an alternate sequence position to said channel other than said originally- in tended physical location for said block.

12. The method of claim 11 , wherein said data channel is associated with a storage medium; wherein said second device handles write operations to said storage medium; wherein said originally- intended sequence position is an ori ginally- intended physical location for said block on said storage medium; wherein said alternate sequence position is an alternate physical location on said storage medium; and, wherein said step of scheduling the retransmission of said block involves determining said alternate physical location in a manner whereby said alternate physical location is sufficiently distanced physically f rom said originally- intended physical location such that, if any defect should occur at said originally- intended physical location , said defect is not likely to occur at said alternate physical location.

13. The method of claim 11 , wherein each block transmitted f rom said fir st device to said second device has a block identi fiction number associated therewith; wherein said step of scheduling the transmission of a block from said buffer to said second device includes entering block identification numbers for blocks awaiting transmission to said second device into said readout queue; and, wherein said step of scheduling the transmission of a block from said buffer to said second device uses said readout queue to determine what block is next to be transmitted to said second device.

14. The method of claim 13, wherein said step of scheduling the retransmission of said block from said buffer to said second device includes entering block identification numbers for those blocks considered by said second device to be bad blocks into a bad block queue wherein are storable block identification numbers; and, wherein said step of scheduling the retransmission of said block involves entering block identification numbers from said bad block queue into locations in said readout queue in a manner whereby the transmission of a block associated with a block identification number from said bad block queue will cause the writing of said block to occur at an alternate physical location on said storage medium which is sufficiently distanced from said originally- intended physical location that any defect occurring at said originally- intended physical location is not likely to occur at said alternate physical location.

15. A method of transmitting a block of data to a first device from a second device, said second device being a type of device that handles at least input operations from a data channel, said method comprising the steps of: providing a buffer having a plurality of addressable memory locations ; providing data bus means for transferring a block of data from said second device to said buffer and f rom said buffer to said fir st devic e; determining whether a block of data obtained by said second device is a duplicate of a previously- transmitted block of data; scheduling the transmission of a block of data f rom said second device to a memory location in said buffer so long as said block is not a dupli cate block; and, scheduling the transmission of a block of data from said memory location in said buffer to said first device in a manner whereby said block is received in an expected sequence by said fir st device.

16. The method of claim 15, further comprising the steps of: receiving an indication from said second device of whether a block of data obtained by said second device is a bad block; scheduling the transmission of a block of data from said second device to a memory location in said buffer effects said transmission so long as said block is nei ther a duplicate block nor a bad block.

17. The method of claim 16, wherein said data channel is associated with a storage medium; wherein said second device handles read operations f rom said storage medium; wherein each block obtained by said second device from said storage medium has a physical block identifi cation number associated therewith which is indicative of a physical location on said storage medium from whence said block was obtained ; and . wherein said step of determining whether a block of data obtained by said second device is a dupli cate block utilizes the physical block identi fication number associated with a newly- obtained block.

18. The method of claim 17 , wherein said step of determining whether a block of data obtained by said second device is a duplicate block comprises comparing the physical block identifi cation number associated with the most newly-obtained block f rom said second device with and the physical block identifi cation number associated with the block most recently transmitted to the first device.