[go: up one dir, main page]

EP0344259A4 - Method and means of fabricating a semiconductor device package - Google Patents

Method and means of fabricating a semiconductor device package

Info

Publication number
EP0344259A4
EP0344259A4 EP19890900040 EP89900040A EP0344259A4 EP 0344259 A4 EP0344259 A4 EP 0344259A4 EP 19890900040 EP19890900040 EP 19890900040 EP 89900040 A EP89900040 A EP 89900040A EP 0344259 A4 EP0344259 A4 EP 0344259A4
Authority
EP
European Patent Office
Prior art keywords
die
semiconductor device
device package
conductive
conductive layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP19890900040
Other languages
French (fr)
Other versions
EP0344259A1 (en
Inventor
Jon Long
Rachel S. Sidorovsky
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
LSI Corp
Original Assignee
LSI Logic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by LSI Logic Corp filed Critical LSI Logic Corp
Publication of EP0344259A1 publication Critical patent/EP0344259A1/en
Publication of EP0344259A4 publication Critical patent/EP0344259A4/en
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • This invention relates to a method and means of fabricating a semiconductor device package.
  • Prior art semiconductor device packages are. fabricated in a sandwich mold configuration wherein the semiconductor device is encapsulated forming a package on both sides of the die.
  • the larger molded package tends to curl, which results in a defective or unusable device.
  • the package has any minute openings or cracks that allow moisture to penetrate to the elements of the semiconductor device, delamination of the semiconductor die can occur, which will render the device defective, or will cause the device to have a reduced operating life.
  • the use of a mold to construct the package increases the height and area of the package significantly.
  • a composite package assembly such as disclosed in the aforementioned copending patent applications, is formed with a rigid lead frame and a thin flexible tape-like structure.
  • the tape-like structure is configured with lead fingers that are connected to leads of the lead frame.
  • the semiconductor assembly which includes bond.wires, is encapsulated using a two section mold that requires a number of molding steps to encompass .the semiconductor device with the lead frame, tape-like structure, bond wires and conductive leads.
  • Conventional semiconductor molded packages which are standard in the semiconductor industry accommodate up to 160 conductive leads, which typically are spaced between 50 and 25 milli-inches from center to center. As the number of leads are increased, the number of bond wires that connect to the leads are increased accordingly. The increase in bond wires results in a larger package.
  • a major objective of the semiconductor industry is to make semiconductor devices with more conductive leads and yet to have a more compact package.
  • semiconductor die with more die pads can be used, which requires closer spacing of the leads of the semiconductor assembly.
  • higher circuit operating speeds- can be realized ' with improved operating reliability.
  • Another object is to provide a semiconductor package that affords a relatively large number of conductive leads and external pins.
  • a further object is to provide a semiconductor package that affords a high degree of protection frpm moisture.
  • a tape is formed of a patterned insulating layer and a conductive layer that is joined to the insulating layer.
  • a semiconductor die is attached to a pad on one surface of the tape and electri ⁇ cally connected to leads of the conductive layer.
  • An insulating coat is dispensed over the die and wire leads.
  • a tape element is adhered to the conductive layer.
  • a package frame or body frame is joined to the tape surrounding the semiconductor die and electrical connections and leads. The body frame serves to contain an encapsulant that is distributed over the top of the body frame, the die and conductive wires and leads.
  • conductive bumps in lieu of wire leads are used for electrical connection.
  • Tab bonding is employed to join the bumps which are formed on the die and the conductive layer.
  • Figure 1 is a sectional side view of a semiconductor assembly, in part, made in accordance with this invention.
  • Figure 2 depicts the attachment of a semiconductor die to the partial assembly of Figure 1;
  • Figure 3 illustrates the wire bonding of the die to conductive lead fingers of the assembly;
  • Figure 4 shows the application of a protective coating over the semiconductor die and bond wires
  • Figure 5 illustrates the partial assembly, turned upside down, for attaching an aligned backside tape, in accordance with this invention
  • Figure 6 illustrates the joinder of a frame body to the assembly
  • Figure 7 is a sectional view of a semiconductor device package, made in accordance with this invention.
  • Figure 8 is a top plan view, par ⁇ ly opened, depicting a semiconductor device package, made in accordance with this invention.
  • Figure 9 is a sectional view of a semiconductor device package, using tape automated bonding (TAB), to join and electrically connect the semiconductor die to the patterned conductive layer by means of conductive bumps; and
  • TAB tape automated bonding
  • FIG. 10 is an exploded view of the semiconductor device package of this invention. Similar numerals refer to similar elements throughout the drawing.
  • a wire bondable tape 10 is formed of a patterned insulating layer 12 made of Kapton (trademark of DuPont), for e:. ⁇ . ⁇ ple» and a gold plate layer 14 that is joined to the Kapton layer.
  • the gold plate layer is about 30-40 microinches thick, by way of example.
  • a thin copper film 16 is sputtered onto the Kapton layer 12 prior to deposition of the gold layer 14 to provide conductivity to the layer 12 and to facilitate adhesion of the gold to the Kapton material.
  • the layer 12 is etched and patterned with cavities for down bonding, as disclosed in copending U.S. Patent Application Serial No. 07/049,641, filed on May 13, 1987.
  • the patterned wire bondable tape is positioned in a fixture 18, to provide flatness to the tape.
  • Die attach epoxy 22, such as Amicon 990C (trademark of Amicon) is spread cr. a die attach pad 20 formed on one surface of the wire bondable tape.
  • a semiconductor die 24 is then aligned and placed on the die attach epoxy as illustrated in Fig. 2.
  • the die attached unit is placed in an oven for curing at a maximum cure temperature of about 150°C for a maximum cure time of about one hour.
  • the cured die attached unit is placed on a vacuum heater block (such as disclosed in copending U.S. Patent Application Serial Number 07/043,894 filed April 29, 1987) to hold the unit rigid and at a temperature of about 200°C. Then the unit is wire bonded thermosonically with 0 gold wires 26 as shown in Fig. 3 to make electrical connec ⁇ tion between the die 24 and lead fingers or conductive elements of the patterned gold layer 14.
  • a silicone gel 28, such as Dow Corning Ql-4939, having a 1 to 10 mixing ratio of curing agent to its base is then applied as a die coat 5 over the die, first starting in the corners and then distributing the gel in the middle of the die. The gel is permitted to flow to cover the die and wires ⁇ see Fig. 4) but. is contained within a prescribed area, as disclosed in the aforementioned copending patent application Serial No. 0 07/049,641.
  • the die coated unit is then cured in an oven at about 150°C for about one hour.
  • the unit is turned upside down and is positioned within an alignment fixture 30 as depicted in Fig. 5.
  • the fixture 18 is used to protect the die, wires 5 and die coat from damage.
  • a tape element 32 that has an adhesive 34 on one surface is set down on the lower surface or backside of the conductive layer 14 which is part of the wire bondable tape 10.
  • a metal block 36 that has been preheated on a hot plate at a temperature in the range of Q 100-150°C approximately is brought into contact with the tape element 32 for about 1 to 1.5 minutes to cause the adhesive 34 to flow and adhere to the backside of the conductive element 14, while the tape 10 is maintained in alignment.
  • the fixture 30 is replaced by a fixture (not -.
  • a package frame or body frame 40 preferably made of a polymer material such as Ryton (trademark of Phillips Chemical Co) is joined to the cured unit by means of an epoxy adhesive 42, which may be a B-stage adhesive such as RT-4B (trademark of RJR Polymers).
  • Ryton trademark of Phillips Chemical Co
  • RT-4B trademark of RJR Polymers
  • the body frame 40 is placed into the alignment fixture 48 so that the adhesive 42 makes contact with the gold plate layer 14 and the tape element 32.
  • a slight force is applied to the top perimeter of the frame by means of a block 50, as shown in Fig. 6.
  • the pressure is applied to the frame for about 15-30 seconds.
  • the unit with the attached frame is then cured at about 150°C for approximately one hour.
  • an electr ⁇ .Yic grade epoxy material 52 such as Hysol CNB 405-12 (trademark, of Hysol) is used to encapsulate the device, while the temperature of the unit is maintained at about 50-70°C.
  • the epoxy is distributed by a dispensing needle, for example, in a circular motion, starting at the perimeter or, corners inside the body frame and moving to the center of the die area. The epoxy is made to flow evenly so .that a substan- tially flat surface results and air bubbles are elimi ⁇ nated. •
  • the epoxy effectively encapsulates the top of the body frame and the elements contained within the frame, as shown in Fig. 7.
  • the epoxy encapsulant is then cured by placing the unit in an oven for 2-4 hours at a temperature between 130°C to 150°C.
  • the novel semiconductor device package of this invention the relationship of the body frame 40 to the patterned Kapton layer 12 is shown.
  • Sprocket holes 56 are provided with the wire bondable tape 10 to aid in the automated processing of the tape.
  • conductive bumps 54 are employed in lieu of bond wires 26, to provide a conductive path from the die pad 20 to the conductive layer 14, as illustrated in Fig. 9.
  • the bumps which may be made of gold, copper or solder, are formed and joined by a tape automated bonding (TAB) process, which is well known in the art.
  • TAB tape automated bonding
  • the use of the bumps reduces the space required for the bond wires.
  • the assembly provides a more compact package and allows a relatively high lead count, because there is no physical space limitation by a molded enclosure as found in the prior art. '
  • the exploded view of the semiconductor device package of this invention shows the body frame 40, which has a vertical dimension, which may be approximately 60 milli-inches for example, and the epoxy encapsulant body 52 as they relate to the wire bondable tape.
  • the assembly does not include a molded package surrounding the semiconductor elements and does not incorporate a conductive patterned lead frame which is part of the electrically conductive path.
  • the body frame or package frame of this invention eliminates the need for molding a package around the semiconductor device and may be made of plastic or nonconductive material.
  • the body frame is used to contain the epoxy encapsulant body which provides the desired protection to the components of the semicon- ductor device.
  • the novel plastic package eliminates the need for a molded enclosure, is greatly reduced in height and overall area, and realizes improved electrical performance and reliability.
  • the insulating area which is Kapton for example, from the conductive layer, with a conductive film therebetween. Moisture penetration is effectively minimized. Also there is no problem of die surface corrosion.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

A semiconductor device assembly is made without a molded package by using a tape having a patterned insulating layer (12) and a conductive layer (14) joined thereto. A semiconductor die (24) is seated on the conductive layer (14) and electrically connected to leads of the patterned conductive layer (14). A body frame (40) is positioned around the die (24) and electrical leads and connections, and an encapsulant material (28) is distributed over the frame (40) and within the frame (40) over the die (24) and electrical leads and connections.

Description

METHOD AND MEANS OF FABRICATING A SEMICONDUCTOR DEVICE PACKAGE
CROSS-REFERENCE TO COPENDING U.S. PATENT APPLICATION
U.S. Patent Application Serial No. 07/008,208, filed January 28, 1987, and assigned to the same assignee, discloses a support assembly for integrated circuits. ϋ.S Patent Application Serial No. 07/049,641, filed May 13, 1987, and assigned to the same assignee, discloses an integrated circuit device package wherein an insulating layer is etched' and patterned. The subject matters of the copending patent applications are incorporated herein for reference.
FIELD OF THE INVENTION
This invention relates to a method and means of fabricating a semiconductor device package.
BACKGROUND OF THE INVENTION
Prior art semiconductor device packages are. fabricated in a sandwich mold configuration wherein the semiconductor device is encapsulated forming a package on both sides of the die. When the package is cooled after the molding process, the larger molded package tends to curl, which results in a defective or unusable device. Also, if the package has any minute openings or cracks that allow moisture to penetrate to the elements of the semiconductor device, delamination of the semiconductor die can occur, which will render the device defective, or will cause the device to have a reduced operating life. Furthermore, the use of a mold to construct the package increases the height and area of the package significantly. A composite package assembly, such as disclosed in the aforementioned copending patent applications, is formed with a rigid lead frame and a thin flexible tape-like structure. The tape-like structure is configured with lead fingers that are connected to leads of the lead frame. The semiconductor assembly, which includes bond.wires, is encapsulated using a two section mold that requires a number of molding steps to encompass .the semiconductor device with the lead frame, tape-like structure, bond wires and conductive leads. Conventional semiconductor molded packages which are standard in the semiconductor industry accommodate up to 160 conductive leads, which typically are spaced between 50 and 25 milli-inches from center to center. As the number of leads are increased, the number of bond wires that connect to the leads are increased accordingly. The increase in bond wires results in a larger package.
A major objective of the semiconductor industry is to make semiconductor devices with more conductive leads and yet to have a more compact package. With a more compact package, semiconductor die with more die pads can be used, which requires closer spacing of the leads of the semiconductor assembly. As a result, higher circuit operating speeds- can be realized'with improved operating reliability.
SUMMARY OF THE INVENTION
An object of this invention is to provide a novel and improved semiconductor package which eliminates the need for a molding process to form a plastic package body. Another object of this invention is to provide a semiconductor package in which wire bonding can be eliminated.
Another object is to provide a semiconductor package that affords a relatively large number of conductive leads and external pins. A further object is to provide a semiconductor package that affords a high degree of protection frpm moisture.
In accordance with this invention, a tape is formed of a patterned insulating layer and a conductive layer that is joined to the insulating layer. A semiconductor die is attached to a pad on one surface of the tape and electri¬ cally connected to leads of the conductive layer. An insulating coat is dispensed over the die and wire leads. At the surface opposite to the die attach pad, a tape element is adhered to the conductive layer. A package frame or body frame is joined to the tape surrounding the semiconductor die and electrical connections and leads. The body frame serves to contain an encapsulant that is distributed over the top of the body frame, the die and conductive wires and leads.
In one embodiment, conductive bumps in lieu of wire leads are used for electrical connection. Tab bonding is employed to join the bumps which are formed on the die and the conductive layer. As a result, the semiconductor device package is made more compact and accommodates an increased number of leads and external pins.
DESCRIPTION OF THE DRAWINGS
The invention will be described in greater detail with reference to the drawings in which:
Figure 1 is a sectional side view of a semiconductor assembly, in part, made in accordance with this invention;
Figure 2 depicts the attachment of a semiconductor die to the partial assembly of Figure 1; Figure 3 illustrates the wire bonding of the die to conductive lead fingers of the assembly;
Figure 4 shows the application of a protective coating over the semiconductor die and bond wires;
Figure 5 illustrates the partial assembly, turned upside down, for attaching an aligned backside tape, in accordance with this invention;
Figure 6 illustrates the joinder of a frame body to the assembly;
Figure 7 is a sectional view of a semiconductor device package, made in accordance with this invention;
Figure 8 is a top plan view, par±ly opened, depicting a semiconductor device package, made in accordance with this invention;
Figure 9 is a sectional view of a semiconductor device package, using tape automated bonding (TAB), to join and electrically connect the semiconductor die to the patterned conductive layer by means of conductive bumps; and
Figure 10 is an exploded view of the semiconductor device package of this invention. Similar numerals refer to similar elements throughout the drawing.
DETAILED DESCRIPTION OF THE INVENTION
With reference to Fig. 1, in an implementation of the invention, a wire bondable tape 10 is formed of a patterned insulating layer 12 made of Kapton (trademark of DuPont), for e:.ώ.αple» and a gold plate layer 14 that is joined to the Kapton layer. The gold plate layer is about 30-40 microinches thick, by way of example. A thin copper film 16 is sputtered onto the Kapton layer 12 prior to deposition of the gold layer 14 to provide conductivity to the layer 12 and to facilitate adhesion of the gold to the Kapton material. The layer 12 is etched and patterned with cavities for down bonding, as disclosed in copending U.S. Patent Application Serial No. 07/049,641, filed on May 13, 1987. The patterned wire bondable tape is positioned in a fixture 18, to provide flatness to the tape. Die attach epoxy 22, such as Amicon 990C (trademark of Amicon) is spread cr. a die attach pad 20 formed on one surface of the wire bondable tape. A semiconductor die 24 is then aligned and placed on the die attach epoxy as illustrated in Fig. 2. The die attached unit is placed in an oven for curing at a maximum cure temperature of about 150°C for a maximum cure time of about one hour.
The cured die attached unit ,is placed on a vacuum heater block (such as disclosed in copending U.S. Patent Application Serial Number 07/043,894 filed April 29, 1987) to hold the unit rigid and at a temperature of about 200°C. Then the unit is wire bonded thermosonically with 0 gold wires 26 as shown in Fig. 3 to make electrical connec¬ tion between the die 24 and lead fingers or conductive elements of the patterned gold layer 14. A silicone gel 28, such as Dow Corning Ql-4939, having a 1 to 10 mixing ratio of curing agent to its base is then applied as a die coat 5 over the die, first starting in the corners and then distributing the gel in the middle of the die. The gel is permitted to flow to cover the die and wires {see Fig. 4) but. is contained within a prescribed area, as disclosed in the aforementioned copending patent application Serial No. 0 07/049,641. The die coated unit is then cured in an oven at about 150°C for about one hour.
After the die coat cure, the unit is turned upside down and is positioned within an alignment fixture 30 as depicted in Fig. 5. The fixture 18 is used to protect the die, wires 5 and die coat from damage. A tape element 32 that has an adhesive 34 on one surface is set down on the lower surface or backside of the conductive layer 14 which is part of the wire bondable tape 10. A metal block 36 that has been preheated on a hot plate at a temperature in the range of Q 100-150°C approximately is brought into contact with the tape element 32 for about 1 to 1.5 minutes to cause the adhesive 34 to flow and adhere to the backside of the conductive element 14, while the tape 10 is maintained in alignment. The fixture 30 is replaced by a fixture (not -. shown) having a wider window to ensure that the adhesive 34 will not stick to the fixture 30 during the curing process that follows. To accomplish the curing, the unit is placed in an oven with the die side or upper surface of the tape 10 facing down for about 1/2 hours at approximately 150βC. In accordance with this invention, a package frame or body frame 40, preferably made of a polymer material such as Ryton (trademark of Phillips Chemical Co) is joined to the cured unit by means of an epoxy adhesive 42, which may be a B-stage adhesive such as RT-4B (trademark of RJR Polymers). The unit is inserted into a fixture or tray 44, as shown in Fig. 6 with the die facing up. An insert 46 is positioned on top of the unit, and an alignment fixture 48. is located on top of the insert. While the unit is maintaine at a temperature between 120-150°C, the body frame 40 is placed into the alignment fixture 48 so that the adhesive 42 makes contact with the gold plate layer 14 and the tape element 32. A slight force is applied to the top perimeter of the frame by means of a block 50, as shown in Fig. 6. The pressure is applied to the frame for about 15-30 seconds. The unit with the attached frame is then cured at about 150°C for approximately one hour.
After the unit with the body frame cures, an electr^.Yic grade epoxy material 52, such as Hysol CNB 405-12 (trademark, of Hysol) is used to encapsulate the device, while the temperature of the unit is maintained at about 50-70°C. The epoxy is distributed by a dispensing needle, for example, in a circular motion, starting at the perimeter or, corners inside the body frame and moving to the center of the die area. The epoxy is made to flow evenly so .that a substan- tially flat surface results and air bubbles are elimi¬ nated. • The epoxy effectively encapsulates the top of the body frame and the elements contained within the frame, as shown in Fig. 7. The epoxy encapsulant is then cured by placing the unit in an oven for 2-4 hours at a temperature between 130°C to 150°C. In the top plan view of Fig. 8, the novel semiconductor device package of this invention, the relationship of the body frame 40 to the patterned Kapton layer 12 is shown. Sprocket holes 56 are provided with the wire bondable tape 10 to aid in the automated processing of the tape. Bond , fingers 58.couple the bond wires 26 to outer lead fingers to enable electrical connection to external connections or pins 60, as disclosed in the referenced copending applications. In another embodiment of the invention, conductive bumps 54 are employed in lieu of bond wires 26, to provide a conductive path from the die pad 20 to the conductive layer 14, as illustrated in Fig. 9. The bumps, which may be made of gold, copper or solder, are formed and joined by a tape automated bonding (TAB) process, which is well known in the art. The use of the bumps reduces the space required for the bond wires. By virtue of the elimination of bond wires, the assembly provides a more compact package and allows a relatively high lead count, because there is no physical space limitation by a molded enclosure as found in the prior art. '
With reference to Fig. 10, the exploded view of the semiconductor device package of this invention shows the body frame 40, which has a vertical dimension, which may be approximately 60 milli-inches for example, and the epoxy encapsulant body 52 as they relate to the wire bondable tape. The assembly does not include a molded package surrounding the semiconductor elements and does not incorporate a conductive patterned lead frame which is part of the electrically conductive path. The body frame or package frame of this invention eliminates the need for molding a package around the semiconductor device and may be made of plastic or nonconductive material. The body frame is used to contain the epoxy encapsulant body which provides the desired protection to the components of the semicon- ductor device. Although the description herein is directed to the processing of a single unit, it should be understood that the process is applicable to produce a multiplicity of units simultaneously. Also, the invention is not limited to the materials and parameters specified herein and modifications may be made within the scope of the invention.
There has been disclosed a novel design for a semicon¬ ductor device package and a process for implementing the package design. The novel plastic package eliminates the need for a molded enclosure, is greatly reduced in height and overall area, and realizes improved electrical performance and reliability. There is virtually no problem of delamination of. the insulating area, which is Kapton for example, from the conductive layer, with a conductive film therebetween. Moisture penetration is effectively minimized. Also there is no problem of die surface corrosion.

Claims

What is claimed is:
1. A semiconductor device package comprising: a tape including a patterned insulating layer and a conductive layer, said conductive layer being joined to said insulating layer; a semiconductor die secured to one surface of said 0 tape; an insulating element joined to said conductive layer; means for electrically coupling said semiconductor die to said conductive layer; 5 a body frame joined to said conductive layer and positioned about said semiconductor die and said electrical coupling means; and an encapsulant body disposed over said frame and within said frame over said die and said electrical o coupling means.
2. A semiconductor device package as in Claim 1, including a conductive film disposed between said patterned insulating layer and said conductive layer. 5
3. A semiconductor device package as in Claim 2, wherein said conductive film is formed from sputtered copper.
4. A semiconductor device package as in Claim 1, wherein said insulating layer is made of a flexible material.
5. A semiconductor device package as in Claim 3, wherein said insulating layer is made of Kapton. 6. A semiconductor device package as in Claim 1, wherein said conductive layer is made of gold plate.
7. A semiconductor device package as in Claim 1, including an insulating-element joined to the backside of said conductive layer.
8. A semiconductor device package as in Claim 1, wherein said coupling means comprise bond wires.
9. A semiconductor device package as in Claim 7, including a silicon gel disposed over said die and said bond wires.
10. A semiconductor device package as in Claim 1, including bond lead fingers coupled to said bond wires, and conductive pins coupled to said bond lead fingers for connection to external conductive leads.
11. A semiconductor device package as in Claim 1, wherein said electrical coupling means comprise conductive bumps.
12. A semiconductor device package as in Claim 10, wherein said insulating element is a backside element, and said body frame is connected to said backside element surrounding said conductive leads.
13. A semiconductor device package as in Claim 1, wherein said body frame has a height substantially greater than the thickness of said patterned insulating layer.
14. A process of making a semiconductor device package comprising the steps of: forming a patterned wire bondable tape by sputter¬ ing a conductive film on an insulating layer; etching the insulating layer and conductive film to define a pattern of conductive leads; depositing a patterned conductive layer on said conductive film; attaching a semiconductor die to said wire bondable tape; forming electrical connections between said die and said conductive layer; joining an insulating element to the backside of said conductive layer; depositing a protective insulating coating over said die and electrical connections; attaching a body frame to the upper surface of said conductive layer and insulating element, surrounding said die, electrical connections and coating; and encapsulating said body frame, coating, die and electrical connections with an insulating material.
■ 15. A process as in Claim 14, wherein said die is attached to said tape by a die attach epoxy and cured at a temperature of about 150°C for one hour or less.
16. A process as in Claim 14, including the step of forming said electrical connections are formed by thermosonically bonding wires between said die pads to conductive leads of said patterned conductive layer.
17. A process as in Claim 14, wherein said step of depositing a protective coating comprises applying a silicone gel to flow over said die and electrical connections and curing the gel coating. 18. A process as in Claim 14, including the step of causing a body frame adhesive to flow to said insulating element on said conductive leads.
EP19890900040 1987-10-30 1988-10-26 Method and means of fabricating a semiconductor device package Ceased EP0344259A4 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11522887A 1987-10-30 1987-10-30
US115228 1987-10-30

Publications (2)

Publication Number Publication Date
EP0344259A1 EP0344259A1 (en) 1989-12-06
EP0344259A4 true EP0344259A4 (en) 1991-04-24

Family

ID=22360053

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19890900040 Ceased EP0344259A4 (en) 1987-10-30 1988-10-26 Method and means of fabricating a semiconductor device package

Country Status (4)

Country Link
EP (1) EP0344259A4 (en)
JP (1) JP2664259B2 (en)
KR (1) KR920008256B1 (en)
WO (1) WO1989004552A1 (en)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4980753A (en) * 1988-11-21 1990-12-25 Honeywell Inc. Low-cost high-performance semiconductor chip package
FR2651923B1 (en) * 1989-09-14 1994-06-17 Peugeot INTEGRATED POWER CIRCUIT.
US5831836A (en) * 1992-01-30 1998-11-03 Lsi Logic Power plane for semiconductor device
US5386342A (en) * 1992-01-30 1995-01-31 Lsi Logic Corporation Rigid backplane formed from a moisture resistant insulative material used to protect a semiconductor device
JP3461204B2 (en) * 1993-09-14 2003-10-27 株式会社東芝 Multi-chip module
KR0139694B1 (en) * 1994-05-11 1998-06-01 문정환 Method of manufacturing semiconductor using solder ball and manufacture method
FR2738077B1 (en) * 1995-08-23 1997-09-19 Schlumberger Ind Sa ELECTRONIC MICRO-BOX FOR ELECTRONIC MEMORY CARD AND EMBODIMENT PROCESS
JP3435271B2 (en) * 1995-11-30 2003-08-11 三菱電機株式会社 Semiconductor device
DE19602436B4 (en) * 1996-01-24 2006-09-14 Infineon Technologies Ag Method for mounting a frame on a carrier material and device for carrying out the method
AR016969A1 (en) 1997-10-23 2001-08-01 Procter & Gamble PROTEASE VARIANTE, ADN, EXPRESSION VECTOR, GUEST MICROORGANISM, CLEANING COMPOSITION, ANIMAL FOOD AND COMPOSITION TO TREAT A TEXTILE
US6835550B1 (en) 1998-04-15 2004-12-28 Genencor International, Inc. Mutant proteins having lower allergenic response in humans and methods for constructing, identifying and producing such proteins
FR2798000B1 (en) * 1999-08-27 2002-04-05 St Microelectronics Sa METHOD FOR PACKAGING A CHIP WITH PARTICULARLY OPTICAL SENSORS AND SEMICONDUCTOR DEVICE OR PACKAGE CONTAINING SUCH A CHIP
AU2003210551A1 (en) 2002-01-16 2003-09-02 Genencor International, Inc. Multiply-substituted protease variants
NZ534198A (en) 2002-02-26 2005-11-25 Genencor Int Population based assessments and means to rank the relative immunogenicity of proteins
EP2500423B1 (en) 2003-02-26 2015-06-17 Danisco US Inc. Amylases producing an altered immunogenic response and methods of making and using the same
US7985569B2 (en) 2003-11-19 2011-07-26 Danisco Us Inc. Cellulomonas 69B4 serine protease variants
WO2005052161A2 (en) 2003-11-19 2005-06-09 Genencor International, Inc. Serine proteases, nucleic acids encoding serine enzymes and vectors and host cells incorporating same
BRPI0519766A2 (en) 2004-12-30 2009-03-10 Genencor Int Authentic acid proteases
EP3218928A4 (en) * 2014-11-12 2018-09-19 Intel Corporation Flexible system-in-package solutions for wearable devices

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2205800A1 (en) * 1972-11-09 1974-05-31 Honeywell Bull Soc Ind
FR2439478A1 (en) * 1978-10-19 1980-05-16 Cii Honeywell Bull FLAT HOUSING FOR DEVICES WITH INTEGRATED CIRCUITS
US4216577A (en) * 1975-12-31 1980-08-12 Compagnie Internationale Pour L'informatique Cii-Honeywell Bull (Societe Anonyme) Portable standardized card adapted to provide access to a system for processing electrical signals and a method of manufacturing such a card
EP0072673A2 (en) * 1981-08-13 1983-02-23 Minnesota Mining And Manufacturing Company Area tape for the electrical interconnection between electronic components and external circuitry
DE3222791A1 (en) * 1982-06-18 1983-12-22 Siemens AG, 1000 Berlin und 8000 München METHOD FOR PRODUCING SEMICONDUCTOR COMPONENTS

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3711625A (en) * 1971-03-31 1973-01-16 Microsystems Int Ltd Plastic support means for lead frame ends
US4089733A (en) * 1975-09-12 1978-05-16 Amp Incorporated Method of forming complex shaped metal-plastic composite lead frames for IC packaging
US4218701A (en) * 1978-07-24 1980-08-19 Citizen Watch Co., Ltd. Package for an integrated circuit having a container with support bars
US4380042A (en) * 1981-02-23 1983-04-12 Angelucci Sr Thomas L Printed circuit lead carrier tape
FI72409C (en) * 1984-03-09 1987-05-11 Lohja Ab Oy FOERFARANDE FOER INKAPSLING AV PAO EN BAERREMSA ANORDNADE HALVLEDARKOMPONENTER.

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2205800A1 (en) * 1972-11-09 1974-05-31 Honeywell Bull Soc Ind
US4216577A (en) * 1975-12-31 1980-08-12 Compagnie Internationale Pour L'informatique Cii-Honeywell Bull (Societe Anonyme) Portable standardized card adapted to provide access to a system for processing electrical signals and a method of manufacturing such a card
FR2439478A1 (en) * 1978-10-19 1980-05-16 Cii Honeywell Bull FLAT HOUSING FOR DEVICES WITH INTEGRATED CIRCUITS
EP0072673A2 (en) * 1981-08-13 1983-02-23 Minnesota Mining And Manufacturing Company Area tape for the electrical interconnection between electronic components and external circuitry
DE3222791A1 (en) * 1982-06-18 1983-12-22 Siemens AG, 1000 Berlin und 8000 München METHOD FOR PRODUCING SEMICONDUCTOR COMPONENTS

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO8904552A1 *

Also Published As

Publication number Publication date
KR920008256B1 (en) 1992-09-25
JP2664259B2 (en) 1997-10-15
JPH03503342A (en) 1991-07-25
WO1989004552A1 (en) 1989-05-18
KR890702249A (en) 1989-12-23
EP0344259A1 (en) 1989-12-06

Similar Documents

Publication Publication Date Title
US5087961A (en) Semiconductor device package
EP0344259A4 (en) Method and means of fabricating a semiconductor device package
EP0684644B1 (en) Method for manufacturing bump leaded film carrier type semiconductor device
JP2981141B2 (en) GRID ARRAY PLASTIC PACKAGE, METHOD OF MANUFACTURING THE SAME, PLASTIC LAMINATE USED FOR MANUFACTURING THE SAME, AND METHOD OF MANUFACTURING THE SAME
KR100241205B1 (en) Mold package for semiconductor device and method of manufacturing the same
EP0883180B1 (en) Semiconductor device and wiring tape for semiconductor device
US6020219A (en) Method of packaging fragile devices with a gel medium confined by a rim member
US6870272B2 (en) Methods of making microelectronic assemblies including compliant interfaces
US7285446B2 (en) Mounting structure of semiconductor chip, semiconductor device and method of making the semiconductor device
JPH1070362A (en) Method and structure for coupling board
WO1993004498A1 (en) Lead-on-chip integrated circuit fabrication method and apparatus
JPH09293749A (en) Forming method of connecting structure body
JPH10178145A (en) Semiconductor device and its manufacturing method and insulation substrate for semiconductor device
JP2625654B2 (en) Semiconductor device and manufacturing method thereof
JPH09199635A (en) Multilayer film for forming circuit substrate, multilayer circuit substrate using it, and package for semiconductor device
JPH09505444A (en) Multi-chip electronic package module using adhesive sheet
JP4334047B2 (en) Semiconductor device and manufacturing method thereof
US20020105792A1 (en) Wave strip injection form
JP3628058B2 (en) Resin-sealed semiconductor device
JP3655338B2 (en) Resin-sealed semiconductor device and manufacturing method thereof
JP3359824B2 (en) Method of manufacturing BGA type semiconductor device
JP2003249509A (en) Method for sealing semiconductor and sealed semiconductor
JPH03297152A (en) Manufacture of semiconductor device
WO1995010852A1 (en) Bonding of leads directly over chip active areas
JP3390507B2 (en) Semiconductor device sealing method and sealing device

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 19890628

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): DE FR GB IT NL

A4 Supplementary search report drawn up and despatched

Effective date: 19910306

AK Designated contracting states

Kind code of ref document: A4

Designated state(s): DE FR GB IT NL

17Q First examination report despatched

Effective date: 19921016

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION HAS BEEN REFUSED

18R Application refused

Effective date: 19930603