JP3359824B2 - Method of manufacturing BGA type semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a BGA type semiconductor device, and more particularly to a method of coating a semiconductor chip.

[0002]

2. Description of the Related Art Higher integration and higher density of semiconductor devices are strongly demanded along with higher performance of electric and electronic components. In response to this, the package structure of a multi-pin semiconductor device is correspondingly required. Has changed from a structure having bonding pads on two sides of a chip to a structure having bonding pads on all four sides.

Further, as a countermeasure for increasing the number of pins, for example, U
In SP5148265, an insulating film on which a wiring pattern is formed is disposed on the surface (functional surface side) of a semiconductor chip via an elastomer layer, and a plurality of solder balls are disposed on the surface of the insulating film in a grid pattern. A semiconductor device called a “ball grid array” has been proposed.

[0004] In this BGA type semiconductor device, the connection portion between the bonding pad of the semiconductor chip and the wiring pattern is covered with an insulating coating material such as a silicon resin by a potting method in order to prevent unnecessary electrical contact with the outside. Have been.

[0005] Incidentally, since this BGA type semiconductor device is formed based on one insulating film in which a plurality of wiring patterns are formed in a grid pattern, a plurality of chips are mounted, and after completion of a covering step, individual products are formed. A method of performing a dividing operation for performing the above operation is adopted. Conventionally, solder balls are projected on the back surface, and an insulating film with a wiring pattern on the front surface is attached to the surface of the semiconductor chip,
Potting and curing the coating material. Thereafter, the cutting operation is performed using a rotary grindstone used for cutting the silicon wafer.

[0006]

However, according to this dividing method, not only is the dividing device expensive, but also at the time of the dividing operation by the rotary blade, a fine powder of the coating material is scattered. there were. Furthermore, since the coating material used here has elasticity, there is a problem that fine powder is not sufficiently washed away even by washing.

[0007] Further, in the coating by the potting method, there is a problem that the coating material flows outside the coating region, and the coating is left behind in a minute gap.

Further, since potting is performed for each semiconductor chip, there is a problem that mass productivity is poor and the covering position accuracy is poor.

The present invention has been made in view of the above circumstances, and has as its object to provide a highly reliable coating method with high mass productivity.

[0010]

Therefore, the first BG of the present invention is provided.
The feature of the method of manufacturing the A-type semiconductor device is that a semiconductor chip having a plurality of bonding pads at a peripheral edge and a wiring pattern are provided and connected to the wiring pattern to protrude and electrically connect to the outside. And an insulating film comprising solder balls of the type described above, and the insulating film was adhered to the functional surface side of the semiconductor chip via an insulating member, and formed on the periphery of the semiconductor chip. In a method of manufacturing a BGA type semiconductor device in which the wiring pattern is connected to a plurality of bonding pads, a surface of the semiconductor chip and a connection portion with the wiring pattern are covered with a coating film by resin sealing using a mold. To include a molding step.

Preferably, in the molding step, a frame body including a plurality of openings having an opening area and a height equivalent to that of the semiconductor chip is provided corresponding to a position of the semiconductor chip. Fixing the frame to the insulating film so that the semiconductor chips are respectively arranged in the openings, and placing the frame between the lower mold and the upper mold of the mold. Mounting process,
A covering step of covering the connection portion between the wiring pattern and the bonding pad of the semiconductor chip with a coating film by press-filling an insulating coating material between the opening and the semiconductor chip. It is characterized by the following.

Preferably, the coating step includes a step of filling the coating material while vacuum-suctioning a region between the opening and the semiconductor chip from a lower mold side.

According to the method of the present invention, in forming a coating film, a large number of coatings can be simultaneously performed using a mold, and the mold is interposed between the semiconductor chips. While filling, the coating on the minute gap does not remain and a highly reliable coating can be achieved. In addition, mass productivity is remarkably improved, and coating position accuracy is also improved. Also, desirably, the frame body is sandwiched between the lower mold and the upper mold and molded, so that workability can be further improved and cost can be reduced. In addition, by filling the coating material while sucking the vacuum from the lower mold side, the filling can be performed more efficiently.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the drawings. In the method of manufacturing a BGA type semiconductor device according to the present invention, as shown in the conceptual diagram of FIG. 1, a mold 20 in which a large number of openings H corresponding to the size of a semiconductor chip 10 are arranged vertically and horizontally is prepared. A mounting body formed by connecting an insulating film 11 having a wiring pattern on the surface of a semiconductor chip 10 is placed in H, and a resin sealing is performed by filling a molding resin M such as a sealing elastomer. 3, a mold layer 1 as shown in FIG. 3 is provided at a connection portion between the bonding pad 10B of the semiconductor chip 10 and the wiring pattern 16S as shown in FIG.
3 is formed. Here, 20L is the lower mold,
20H is an upper mold, 20P is a plunger for injection molding, 1
2 is a solder ball, and 17 is an insulating elastomer.

[0015]

Next, this method will be described in detail with reference to process drawings. First, as shown in FIG. 4, a copper foil 15 is adhered to the surface of an insulating film 11 made of a polyimide tape, and a photoresist (not shown) is further applied to the surface and patterned by photolithography. Is formed.

Thereafter, a photoresist is further applied and photolithography is performed to form a resist pattern R as shown in FIG. In the following drawings, one half of one unit is shown, and a large number of such units are arranged at predetermined intervals.

Thereafter, as shown in FIG. 6, a gold plating layer 16 is formed on the surface of the copper foil 15 exposed from the resist pattern R by electroless gold plating.

Then, a photoresist is applied from the back side, photolithography is performed, and the insulating film 11 is etched using this as a mask to form a connection piece (beam lead) 16S at the tip of the wiring pattern as shown in FIG. A window W and a via V are formed in the electrical connection region between the peripheral region and the solder ball 12 (see FIG. 8).

As shown in FIG. 8, solder balls 12 are formed in the vias V except for the connection piece forming portions so as to be connected to the pattern of the copper foil 15 and protrude from the surface.

Then, as shown in FIG. 9, copper etching is performed to remove copper exposed in the window by etching.
As a result, the area of the window W has only the gold pattern as the connection piece 16S, and is in a flexible state. The central portion has a two-layer structure of a copper foil pattern 15 and a gold plating layer 16 and is connected to the connection pieces 16S, respectively, and functions as a wiring pattern.

Further, as shown in FIG. 10, an insulating elastomer (silicone elastomer) 17 is applied on the surface of the insulating film 11 on which the wiring pattern 16 is formed by a printing method, baked and cured.

Thereafter, an adhesive is applied onto the insulating elastomer layer 17 and is positioned on the diced semiconductor chip 10 as shown in FIG. The conductive film 11 is fixed.

Thereafter, as shown in FIG. 12, the connection piece 16S is thermocompression-bonded to the bonding pad on the peripheral portion of the semiconductor chip 10 using a bonding tool BT, so that the connection between the wiring pattern 15 and the semiconductor chip 10 is made. Make the electrical connection. At this time, since the gold connection piece 16S is thin,
It is cut at the same time as thermocompression bonding.

As shown in FIG. 13, the photosensitive film 3 covers the window W of the insulating film 11.
Attach 0. Then, a fine hole o is formed in this.

Thereafter, as shown in FIGS. 14 (a) and 14 (b) (FIG. 14 (a) is a sectional view taken along a line aa in FIG. 14 (b)), the solder ball forming region A lower mold 20L having a plurality of recesses 21 is prepared, and a plurality of openings H having an opening area and a height equivalent to that of the semiconductor chip are provided corresponding to the position of the semiconductor chip. Is prepared. Then, the frame 22 is arranged so that the semiconductor chips are respectively arranged in the openings.
Then, the insulating film connected to the semiconductor chip is fixed, this is placed on the lower mold 20L, and the upper mold 20H is further installed.

Then, an insulating coating material M is filled between the opening and the semiconductor chip. 25 is a filling hole of the coating material. In this state, by applying pressure as shown in FIG. 15, the connection portion between the wiring pattern of the semiconductor chip and the bonding pad is covered with a coating material. At this time, by filling the coating material while vacuum-sucking from the lower mold 20L side through the fine holes o formed in the film shown in FIG.
The coating material is filled well.

Finally, as shown in FIG. 16, after the coating is completed and the mold is removed, the film is removed or the film is brought into close contact by heat treatment, and is applied using a punch having the same shape as the opening of the frame. By pressing, the insulating film 11 is cut and cut into individual pieces, and as shown in FIG. 17, a semiconductor device covered with a coating material and protected is completed.

According to the method of the embodiment of the present invention, since the coating material is molded using a mold, a dense and high-quality coating is performed, and there is no need to use a dicing machine or a cleaning device. In addition, the manufacturing cost is reduced, and the fine powder of the coating material is not scattered.

In the above embodiment, the insulating film (TAB substrate) on which the solder balls are formed is bonded to the semiconductor chip. However, after the bonding and coating are completed, the solder balls are formed. Is also good. As a second embodiment of the present invention, this embodiment will be described with reference to the process sectional views of FIGS.

As shown in FIG. 18 to FIG. 21, up to the step of forming a window W and a via V in an electrical connection area between the solder ball 12 and a peripheral area where a connection piece (beam lead) is formed. Are formed in the same manner as the steps shown in FIGS. 4 to 7 of the first embodiment.

Then, as shown in FIG.
The copper foil pattern 15 exposed inside is removed by etching. At this time, the via V is covered and protected with a resist (not shown) or the like.

Thereafter, as shown in FIG. 23, an insulating elastomer (silicone elastomer) 17 is applied on the wiring pattern forming surface side of the insulating film by a printing method.
Bake and cure.

Thereafter, an adhesive is applied on the insulating elastomer layer 17 and then positioned on the diced semiconductor chip 10 as shown in FIG. Insulating film 11
Is fixed.

Thereafter, as shown in FIG. 25, the connection piece 16S is thermocompression-bonded to the bonding pad on the peripheral portion of the semiconductor chip 10 using a bonding tool BT, so that the connection between the wiring pattern 15 and the semiconductor chip 10 is made. Make the electrical connection. At this time, since the gold connection piece 16S is thin,
It is cut at the same time as thermocompression bonding. Then, as shown in FIG. 26, the photosensitive film 3 is then placed on the insulating film 11.
Attach 0. Thereafter, as shown in FIG. 27, the frame 22 is attached to the insulating film 11 on which the semiconductor chip is mounted in the same manner as in the first embodiment, and is set in a mold. Coating is performed similarly. Here, since no solder ball has been formed yet, the concave portion of the lower mold 20L is unnecessary. The other steps may be performed in exactly the same manner as in the first embodiment. Molding in this way,
The connection area between the connection piece and the bonding pad is covered with the coating material 13.

Thereafter, as shown in FIG. 28, photolithography is performed to expose the photosensitive film 30 to light.
As shown in FIG. 9, a hole h is formed in the solder ball forming region. Then, as shown in FIG. 30, a flux is printed on the copper foil 15 exposed in the hole h, and Pb 10%,
Solder ball 1 of 0.7 mm diameter made of 90% Sn solder
2 at 320 ° C for 10 seconds (peak temperature maintenance time)
Through the heating step described above, the surface is fixed to the copper pattern 15.
If necessary, use isopropyl alcohol (IP
A) and immersion in ultrasonic cleaning to remove excess flux. Finally, the photosensitive film is removed or brought into close contact by heat treatment, and if necessary, the surface of the solder ball is plated with a noble metal such as palladium.
As shown in FIG. 1, a BGA type semiconductor device in which the connection between the wiring pattern and the semiconductor chip is well covered and protected is completed.

Here, the solder balls 12 are formed on the entire surface so as to form a lattice, and the back surface of the semiconductor chip 10 is in a bare state. Thus, a low-cost and highly reliable semiconductor device is formed. In this method, since a photosensitive film is adhered, the releasability from a mold is improved.

Next, as a third embodiment of the present invention, the semiconductor chip is placed on the lower mold side without attaching a photosensitive film in the second embodiment, and is formed on an insulating film. The window W may be filled with the mold resin.

That is, in this method, up to the bonding step shown in FIG. 25, the semiconductor device is formed in exactly the same manner as in the second embodiment, but after the connection piece and the semiconductor chip are connected by bonding, the insulation shown in FIG. Film 1
1, a frame 22 is provided in the same manner as in the first and second embodiments.
Attach.

Then, as shown in FIG. 33, the window W of the insulating film 11 is set in the mold 20.
Is used as a resin filling port, and coating is performed in the same manner as in the first embodiment. Here, since the solder balls have not been formed yet, the concave portion of the lower mold is unnecessary. The other steps may be performed in exactly the same manner as in the first embodiment. Molding is performed in this manner, and the connection region between the connection piece 16S and the bonding pad is covered with the coating material 13 as shown in FIG.

Thus, a BGA type semiconductor device in which the connection between the wiring pattern and the semiconductor chip is well covered and protected is completed.

The pitch and diameter of the via holes are as follows:
For example, if the lattice pitch is 1 mm, the hole diameter can be changed to 0.55 mm, and if the lattice pitch is 1.5 mm, the hole diameter can be changed to 0.75 mm.

Further, the composition of the solder ball can be appropriately selected. For example, when eutectic solder of Pb 37% Sn 63% is used, the heating temperature in the fixing step may be about 230 ° C.

[0043]

As described above, according to the present invention, since the coating material is molded by using the mold, there is no need to use an expensive cutting device or cleaning device, and the manufacturing cost is reduced. In addition, since there is no scattering of fine powder of the coating material, there is no problem that the reliability is reduced due to the adhesion of impurities.

[Brief description of the drawings]

FIG. 1 is a conceptual diagram showing the present invention.

FIG. 2 is a manufacturing process diagram of the semiconductor device of the present invention.

FIG. 3 is a manufacturing process diagram of the semiconductor device of the present invention.

FIG. 4 is a manufacturing process diagram of the semiconductor device according to the first embodiment of the present invention;

FIG. 5 is a manufacturing process diagram of the semiconductor device according to the first embodiment of the present invention;

FIG. 6 is a manufacturing process diagram of the semiconductor device according to the first embodiment of the present invention;

FIG. 7 is a manufacturing process diagram of the semiconductor device according to the first embodiment of the present invention;

FIG. 8 is a manufacturing process diagram of the semiconductor device according to the first embodiment of the present invention;

FIG. 9 is a view showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention;

FIG. 10 is a view showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention;

FIG. 11 is a view showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention;

FIG. 12 is a view showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention;

FIG. 13 is a view showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention;

FIG. 14 is a view showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention;

FIG. 15 is a view showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention;

FIG. 16 is a view showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention;

FIG. 17 is a view showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention;

FIG. 18 is a view showing a manufacturing process of the semiconductor device according to the second embodiment of the present invention;

FIG. 19 is a view showing a manufacturing process of the semiconductor device according to the second embodiment of the present invention;

FIG. 20 is a view showing a manufacturing process of the semiconductor device according to the second embodiment of the present invention;

FIG. 21 is a view showing a manufacturing process of the semiconductor device according to the second embodiment of the present invention;

FIG. 22 is a view showing a manufacturing process of the semiconductor device according to the second embodiment of the present invention;

FIG. 23 is a view showing a manufacturing process of the semiconductor device according to the second embodiment of the present invention;

FIG. 24 is a view showing a manufacturing process of the semiconductor device according to the second embodiment of the present invention;

FIG. 25 is a view showing a manufacturing process of the semiconductor device according to the second embodiment of the present invention;

FIG. 26 is a view showing a manufacturing process of the semiconductor device according to the second embodiment of the present invention;

FIG. 27 is a diagram illustrating a manufacturing process of the semiconductor device according to the second embodiment of the present invention;

FIG. 28 is a diagram illustrating a manufacturing process of the semiconductor device according to the second embodiment of the present invention;

FIG. 29 is a diagram illustrating a manufacturing process of the semiconductor device according to the second embodiment of the present invention;

FIG. 30 is a view showing a manufacturing process of the semiconductor device according to the second embodiment of the present invention;

FIG. 31 is a view showing a manufacturing process of the semiconductor device according to the second embodiment of the present invention;

FIG. 32 is a view showing a manufacturing process of the semiconductor device according to the third embodiment of the present invention;

FIG. 33 is a view showing a manufacturing process of the semiconductor device according to the third embodiment of the present invention;

FIG. 34 is a view showing a manufacturing process of the semiconductor device according to the third embodiment of the present invention;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Semiconductor chip 11 Insulating film 12 Solder ball 13 Coating material 15 Copper foil 16 Gold plating layer 16S Connection piece 20U Upper die 20L Lower die 22 Frame H Opening

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-54-153866 (JP, A) JP-A-8-31868 (JP, A) JP-A-7-186187 (JP, A) JP-A-6-186187 209055 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/56 H01L 23/12

Claims (2)

(57) [Claims] 1. An insulating film having a wiring pattern formed thereon is attached to a functional surface side of a plurality of semiconductor chips having a plurality of bonding pads on a peripheral portion via an insulating member.
A BGA that is divided into individual semiconductor devices after connecting the bonding pad and the wiring pattern, is mounted on the insulating film, and is electrically connected to the outside via a plurality of solder balls connected to the wiring pattern. In the method for manufacturing a semiconductor device, a frame having a plurality of openings having an opening area and a height equivalent to that of the semiconductor chip is provided corresponding to the position of the semiconductor chip, and the semiconductor chip is provided in the opening. Fixing the frame to the insulating film so as to be arranged respectively; and mounting the frame fixed to the insulating film between the lower mold and the upper mold of the mold. Pressurizing and filling an insulating coating material between the opening and the semiconductor chip to cover a connection portion between the wiring pattern and the bonding pad. Method of manufacturing a BGA type semiconductor device for a coating step of coating with coating film, characterized in that by cutting the insulating film and a step of dividing into individual semiconductor devices. 2. The BGA according to claim 1, wherein in the covering step, the coating material is filled while vacuum-sucking a region between the opening and the semiconductor chip from a lower mold side. Of manufacturing a semiconductor device.