EP0325808B1 - Process for producing an electric connexion on a silicon semiconductor device - Google Patents
Process for producing an electric connexion on a silicon semiconductor device Download PDFInfo
- Publication number
- EP0325808B1 EP0325808B1 EP88202724A EP88202724A EP0325808B1 EP 0325808 B1 EP0325808 B1 EP 0325808B1 EP 88202724 A EP88202724 A EP 88202724A EP 88202724 A EP88202724 A EP 88202724A EP 0325808 B1 EP0325808 B1 EP 0325808B1
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- European Patent Office
- Prior art keywords
- layer
- contact
- titanium
- tungsten
- islands
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- 238000000034 method Methods 0.000 title claims description 48
- 239000004065 semiconductor Substances 0.000 title claims description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims description 11
- 230000008569 process Effects 0.000 title claims description 11
- 229910052710 silicon Inorganic materials 0.000 title claims description 11
- 239000010703 silicon Substances 0.000 title claims description 11
- 229910052751 metal Inorganic materials 0.000 claims description 30
- 239000002184 metal Substances 0.000 claims description 29
- 230000000295 complement effect Effects 0.000 claims description 26
- 229910052721 tungsten Inorganic materials 0.000 claims description 24
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 23
- 239000010937 tungsten Substances 0.000 claims description 23
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 19
- 230000012010 growth Effects 0.000 claims description 18
- 229910052750 molybdenum Inorganic materials 0.000 claims description 16
- 239000011733 molybdenum Substances 0.000 claims description 16
- 239000003870 refractory metal Substances 0.000 claims description 16
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 14
- 229910021332 silicide Inorganic materials 0.000 claims description 13
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 13
- 239000010936 titanium Substances 0.000 claims description 13
- 229910052719 titanium Inorganic materials 0.000 claims description 13
- 229910021341 titanium silicide Inorganic materials 0.000 claims description 12
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 10
- 238000006243 chemical reaction Methods 0.000 claims description 8
- 238000011049 filling Methods 0.000 claims description 8
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 6
- 239000010941 cobalt Substances 0.000 claims description 6
- 229910017052 cobalt Inorganic materials 0.000 claims description 6
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 230000009467 reduction Effects 0.000 claims description 6
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 5
- 239000001257 hydrogen Substances 0.000 claims description 5
- 229910052739 hydrogen Inorganic materials 0.000 claims description 5
- NXHILIPIEUBEPD-UHFFFAOYSA-H tungsten hexafluoride Chemical compound F[W](F)(F)(F)(F)F NXHILIPIEUBEPD-UHFFFAOYSA-H 0.000 claims description 5
- 239000007789 gas Substances 0.000 claims description 4
- 229910000077 silane Inorganic materials 0.000 claims description 4
- WSWMGHRLUYADNA-UHFFFAOYSA-N 7-nitro-1,2,3,4-tetrahydroquinoline Chemical compound C1CCNC2=CC([N+](=O)[O-])=CC=C21 WSWMGHRLUYADNA-UHFFFAOYSA-N 0.000 claims description 3
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 238000005234 chemical deposition Methods 0.000 claims 2
- 238000005554 pickling Methods 0.000 description 16
- 239000000463 material Substances 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 229910001080 W alloy Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 239000004922 lacquer Substances 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 230000006911 nucleation Effects 0.000 description 2
- 238000010899 nucleation Methods 0.000 description 2
- 230000002035 prolonged effect Effects 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 229910008479 TiSi2 Inorganic materials 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- WPPDFTBPZNZZRP-UHFFFAOYSA-N aluminum copper Chemical compound [Al].[Cu] WPPDFTBPZNZZRP-UHFFFAOYSA-N 0.000 description 1
- 230000003698 anagen phase Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- DFJQEGUNXWZVAH-UHFFFAOYSA-N bis($l^{2}-silanylidene)titanium Chemical compound [Si]=[Ti]=[Si] DFJQEGUNXWZVAH-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000005119 centrifugation Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 239000008367 deionised water Substances 0.000 description 1
- 229910021641 deionized water Inorganic materials 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 239000008246 gaseous mixture Substances 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 238000010348 incorporation Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000002045 lasting effect Effects 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000002791 soaking Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 238000012876 topography Methods 0.000 description 1
- 238000005019 vapor deposition process Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/019—Contacts of silicides
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/97—Specified etch stop material
Definitions
- a first stage aiming to fill at least substantially the contact openings with localized elements of a refractory metal, tungsten or molybdenum, obtained for example by growth selective or by deposit with uniformly covering property followed by a partial pickling, and a second step consisting simply in covering the structure with a metallic layer and cutting out the desired configuration there.
- the stopping of pickling in the bottom of these openings is constituted by the layer of silicide whose pickling selectivity with respect to the oxide of the insulating layer is not very high. There is therefore a risk that the silicide layer will be damaged during the pickling of the contact openings.
- the present invention aims in particular to remedy this difficulty and to provide a method in which the pickling operation of the contact openings is less critical and preserves the integrity of the silicide layer in contact with the semiconductor material.
- the depth of the stripping to be carried out is limited by the complementary metallic layer.
- the pickling selectivity of the insulating material - silicon dioxide for example - with respect to tungsten or molybdenum is excellent, so that the pickling operation can be prolonged without fear of a significant attack by the layer complementary metal in the bottom of these openings. This process makes it possible to safely make contact openings which, on the same substrate, have different depth limits as this results from an operation known as planarization of the insulating layer.
- the complementary metal layer is obtained directly in a localized form, it does not require the use of a particular etching mask. It can also be observed that this complementary metallic layer has a role which does not impose rigorous control of its thickness.
- the structure formed by the association of the complementary metal layer and localized elements of refractory metal has, due to its shape, better mechanical resistance against stresses and in particular stresses of thermal origin.
- the thickness of the complementary metallic layer is chosen between 20 and 150 nm and preferably between 50 and 100 nm.
- the method according to the invention is characterized in that, having chosen titanium as the refractory metal for producing said layer of silicide, a layer of titanium nitride is formed on its surface which is used as a basis for the selective growth of the complementary metallic layer.
- this titanium nitride layer is formed by a surface conversion treatment of the titanium silicide layer at a temperature between 700 and 1000 ° C., under a nitrogen atmosphere.
- a suitable base is thus produced for the growth of the complementary metal layer by means of the heat treatment which is used at the same time for annealing the layer of titanium silicide.
- the complementary metal layer is preferably produced by the chemical vapor deposition method, at a reduced pressure of between 0.05 and 2 torr (6.6 to 266 Pa), using the reduction with hydrogen from tungsten hexafluoride (or molybdenum hexafluoride), at a temperature between 300 and 500 ° C and a hexafluoride / hydrogen gas flow ratio between 1/1000 and 1/5.
- the protection of the titanium silicide layer with a layer of titanium nitride before the deposition of the complementary metal layer is no longer necessary.
- silane flow rate SiH4
- tungsten hexafluoride or molybdenum
- Figure 1 is a schematic and partial section showing an integrated circuit interconnection structure capable of being obtained by the method according to the invention.
- Figures 2 to 6 illustrate by partial views, in section, different steps of the method according to the invention for making electrical contacts on a semiconductor device.
- FIG. 1 shows an example of an interconnection structure making electrical contacts in an integrated circuit with silicon, with MOS transistors.
- a substrate 10 of a first type of conductivity has on its surface doped source and drain regions 11, 12, of a second type of conductivity, opposite to the first. These doped regions 11 and 12 have a periphery delimited by a localized layer of field oxide 13 and are separated from one another by a narrow channel 14 surmounted by a control grid 15 made of highly doped polycrystalline silicon.
- the grid 15 is isolated from the semiconductor material of the channel 14 by a layer of grid oxide 16.
- Portions of the polycrystalline silicon layer used to create the grid 15 can be maintained above the field oxide 13, to establish certain electrical connections; this is the case of the connecting strip shown in 17.
- contact zones have been made which expose most of the surface of the doped regions 11 and 12 as well as the surface of the grids 15 and connecting strips 17.
- contact islands 20a to 20d were formed comprising at least one layer of silicide of a refractory metal such as titanium or cobalt, and which were obtained by self-alignment with the contact zones, according to a technique well known to specialists in the field.
- An insulating layer 22 has contact openings 23, 24, 25, the bottom of which opens onto specific contact islands 20a, 20b, 20d.
- an interconnection configuration completes the structure of the device shown, this configuration comprising on the one hand localized elements 26 of tungsten or molybdenum at least partially filling the contact openings 23, 24, 25, and on the other hand portions 27, 28 of a so-called second level metallic layer, which can be made of aluminum for example, cut into a determined configuration, and which covers the localized elements 26 in order to make the desired electrical connections with the contact islands 20a, 20b, 20d.
- a so-called second level metallic layer which can be made of aluminum for example, cut into a determined configuration, and which covers the localized elements 26 in order to make the desired electrical connections with the contact islands 20a, 20b, 20d.
- the method according to the invention aims to produce an interconnection structure, in particular of the type shown schematically in FIG. 1 in which, before establishing the insulating layer 22, the contact islands 20a, 20b, 20c, 20d are covered with a complementary metallic layer obtained by selective growth of tungsten or molybdenum and which is therefore located at these islets.
- FIG. 2 shows schematically and simplified a contact island 20 arranged in a contact area 18 delimited on the surface of a semiconductor substrate 10 by means of a dielectric layer 19.
- the contact island 20 is obtained in a self-aligned manner with the contact zone 18 by depositing a layer of a refractory metal such as titanium, on the entire structure, then, by a suitable heat treatment, to locally react the titanium layer with the silicon surface portions which are not covered by the dielectric layer 19, and form a titanium silicide at the location of the contact zones 18, then finally by selective pickling the rest of the unreacted titanium layer. It is known and practically necessary, at this stage of the process, to stabilize the composition of the silicide layer of titanium in contact with the material of the contact zone by a second heat treatment, preferably carried out under a nitrogen atmosphere. This is why the contact island 20 finally consists of a layer of titanium silicide 201 surmounted by a thin layer of titanium nitride 202 obtained during the treatment mentioned by the action of nitrogen on the silicide. titanium.
- a treatment lasting 10 seconds at 850 ° C, under nitrogen leads to the formation of a layer of titanium nitride 202, 6 to 8 nm thick, on the surface of a layer titanium silicide 201 of the order of 30nm thick.
- the titanium nitride layer 202 serves as the nucleation base for the growth of tungsten, while the dielectric layer 19 on the contrary inhibits this growth.
- the complementary metal layer 30 is located at the contact islands 20 as indicated in FIG. 3, without having to resort to a photomask operation.
- the process of selective growth of tungsten is known as such. It preferably uses the vapor deposition method using the chemical reaction of reduction of tungsten fluoride (WF6) by hydrogen (H2), at a temperature between 300 ° C and 500 ° C, and under reduced pressure in the range of 6.6 to 266 Pa (0.05 to 2 torr).
- WF6 and H2 introduced during the reaction, are chosen in a ratio of between 1/1000 and 1/5.
- the complementary metal layer 30 can also, if desired, be produced by selective growth of molybdenum according to operating conditions very close to those indicated for tungsten. In the indicated reaction, of reduction of a tungsten or molybdenum hexafluoride by hydrogen, the layer of titanium silicide 201 is would be attacked if it were not protected by a layer of titanium nitride 202.
- the ratio between the silane flow rate and the flow rate of the hexafluoride used is chosen from the range of 1/5 to 3/1, a ratio of the order of 1/1 being particularly favorable, the selectivity of the deposit is good preserved, the attack of titanium silicide (or of silicon) is avoided whereas the incorporation of silicon in the deposited metal remains so weak that it is difficult to measure and can be considered as null, in practice.
- the thickness of the complementary metal layer 30 is not particularly critical, it is generally chosen between 20 and 150 nm and preferably between 50 and 100 nm.
- the complementary metal layer 30 no longer fully fulfills its role of pickling barrier and may have discontinuities resulting from the initial growth phase.
- an insulating layer 32 for example made of silicon dioxide, is then formed over the entire structure, using any suitable method, for example the vapor deposition method using the oxidation of a compound. silicon.
- the contact openings 33 are stripped in the insulating layer 32, preferably using the technique known as reactive ion etching, which makes it possible to obtain very small diameter openings having practically vertical edges.
- the location of the contact openings 33 is such that these openings expose a portion of the surface of the complementary metal layer 30 covering the contact islands.
- the ion etching of the insulating layer 32 preferably uses the gaseous mixture CF4 + O2 ionized as the chemical attack medium.
- the pickling selectivity of silicon oxide with respect to tungsten or molybdenum exceeds a ratio of 30: 1 so that the complementary metal layer 30 provides a very effective pickling stop.
- the etching of the insulating layer 32 ends on a contact island formed of a double layer of titanium nitride-titanium silicide.
- the pickling selectivity of silicon oxide with respect to these materials is only of a ratio close to 10: 1.
- the method according to the invention therefore makes it possible to complete the pickling of contact openings 33 without risk of under -Excessive etching and degradation of the titanium silicide layer.
- This advantage is particularly important when on the same substrate, contact openings of different depths have to be etched simultaneously, as shown in FIG. 1 for contact openings 23 and 25.
- the mask of photosensitive lacquer used to define the contact openings 33 (not shown in the figure), is eliminated for example by means of an oxygen plasma pickling.
- the structure at the stage shown in FIG. 4 is then subjected to an additional cleaning of its surface using the usual chemical baths in the material, such as, for example, soaking in nitric acid and then in dilute hydrofluoric acid, followed by careful rinsing in deionized water and drying by centrifugation.
- the usual chemical baths in the material such as, for example, soaking in nitric acid and then in dilute hydrofluoric acid, followed by careful rinsing in deionized water and drying by centrifugation.
- the purpose of the following operation is to fill, at least for a substantial part of their volume, the contact openings 33 with localized elements of a refractory metal such as tungsten or molybdenum.
- Localized elements 26 as illustrated in FIG. 5A can be obtained by a method of selective growth of tungsten or molybdenum under operating conditions which are substantially the same as for the production of the complementary metallic layer 30.
- the same metal tungsten for example, will be used to form the complementary metal layer 30 and the localized elements 26, this for reasons of simplicity and economy of equipment in particular.
- the additional metallic layer 30 could also be made of molybdenum and then localized elements 26 of tungsten grow, or vice versa if desired, depending on particular circumstances.
- the metal surface of the complementary layer 30 which is exposed in the contact openings 33 serves as a nucleation base for the selective growth of the localized elements 26, while on the free surface 34 of the insulating layer 32 the growth does not happen.
- the contact openings 33 have a diameter of 0.8 ⁇ m and a depth which can vary from 0.5 to 0.9 ⁇ m depending on the position of these openings.
- the duration of the growth is determined so that the shallowest contact openings are overfilled and have localized elements 26 the upper level of which forms a protrusion which slightly exceeds the level of the surrounding insulating layer and which widens laterally but without this being troublesome for the operation of the device.
- the localized elements 26 can also be obtained indirectly, for example according to a process which will be described with reference to FIGS. 5B and 5C.
- an adhesion layer 40 is deposited over the entire surface, including the interior surface of the contact openings 33, which is thin with respect to the dimensions of the contact openings, for example 100 nm d '' a titanium-tungsten alloy (10% Ti, 90% W by weight).
- a tungsten filler layer 41 is grown, also using a deposition process with conformal covering property, such as the vapor deposition process, at reduced pressure.
- the thickness of the filling layer 41 is here chosen sufficient to completely fill the contact openings 33, that is to say that it is of a value which is at least half the diameter of these openings.
- the adhesion layer and the filling layer are then removed from the surface of the insulating layer 32 so as to leave only the portions of these layers which are located inside the contact openings 33 and thus form localized metallic elements. 26 as shown in Figure 5C.
- This operation can be carried out by pickling in an SF6 plasma which attacks tungsten and the titanium-tungsten alloy faster than silicon oxide.
- the localized element 26 provides part of a metallic interconnection configuration. As indicated in FIG. 6, the other complementary part is produced by covering the surface 34 of the device with a metal layer 35, the portions of which other than those of the desired configuration are eliminated by selective pickling, localized by means of a mask. photosensitive lacquer for example.
- the surface 34 on which the metal layer 35 rests has preferably been made substantially planar, so that this metal layer 35 can be obtained without difficulty using current techniques.
- Many metals may be suitable for carrying out this operation and the choice will be guided by the requirements of mechanical adhesion to the surface of the insulating layer 32, by the search for a minimum of electrical conductivity, and of good resistance to the phenomenon of electromigration.
- a layer of aluminum or an aluminum-copper alloy, 0.8 to 1 ⁇ m thick is very suitable.
- parts of the metal layer 35 cover the contact openings 33 to provide the electrical connection with the localized elements 26.
- the device can be completed, if desired, and depending on its complexity, by at least one additional metallic interconnection configuration, established at a higher level.
- the method according to the invention is not limited to the fabrication of an interconnection structure on an integrated circuit with MOS transistors. It is more generally aimed at making contacts on all kinds of semiconductor devices with a silicon substrate and preferably when it is desired to use contact areas of very small dimensions and to practice thereon contact islands of refractory metal silicide self-aligned with said contact areas.
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- Electrodes Of Semiconductors (AREA)
Description
La présente invention concerne un procédé de fabrication d'une structure d'interconnexion électrique sur un dispositif semiconducteur à substrat de silicium, procédé qui comporte notamment les étapes consistant successivement :
- à créer à la surface du dispositif des zones de contact,
- à former des îlots de contact comprenant au moins une couche de siliciure d'un métal réfractaire tel que le titane ou le cobalt, recouvrant les zones de contact,
- à former sur l'ensemble une couche isolante dans laquelle sont pratiquées des ouvertures de contact où se trouvent exposées au moins des portions de la surface desdits îlots de contact,
- à réaliser une configuration métallique d'interconnexion en effectuant d'abord un remplissage au moins partiel des ouvertures de contact par des éléments localisés d'un métal réfractaire tel que le tungstène ou le molybdène, puis en recouvrant l'ensemble d'une couche métallique qui est ensuite découpée dans une configuration déterminée, des parties de cette configuration métallique recouvrant les ouvertures de contact et étant en contact électrique avec lesdits éléments localisés.
- to create contact areas on the surface of the device,
- to form contact islands comprising at least one layer of silicide of a refractory metal such as titanium or cobalt, covering the contact zones,
- forming on the assembly an insulating layer in which are made contact openings where at least portions of the surface of said contact islands are exposed,
- to achieve a metallic interconnection configuration by first performing at least partial filling of the contact openings with localized elements of a refractory metal such as tungsten or molybdenum, then by covering the whole with a metallic layer which is then cut into a determined configuration, parts of this metallic configuration covering the contact openings and being in electrical contact with said localized elements.
Des dispositifs semiconducteurs et notamment des circuits intégrés sont couramment fabriqués en utilisant de l'aluminium ou un alliage d'aluminium en tant que matériau pour la prise de contact avec la surface du silicium et pour établir les structures d'interconnexion. Cependant, une tendance constante de la technique se manifeste en faveur d'un accroissement de la complexité des fonctions intégrées ainsi que de leur rapidité de fonctionnement ce qui amène à donner aux éléments constitutifs de ces fonctions des dimensions de plus en plus petites.Semiconductor devices and in particular integrated circuits are commonly manufactured using aluminum or an aluminum alloy as a material for making contact with the silicon surface and for establishing interconnection structures. However, a constant trend in the technique manifests itself in favor of an increase in the complexity of the integrated functions as well as in their speed of operation, which leads to giving the constituent elements of these functions of increasingly smaller dimensions.
Dans ce contexte, il s'est avéré que l'aluminium présentait de sérieuses limitations d'emploi vis-à-vis de certains procédés de fabrication de circuits à très haute densité d'intégration, au moins en ce qui concerne la prise de contact sur des zones dopées du semiconducteur ayant une très faible épaisseur et des dimensions latérales réduites.In this context, it turned out that aluminum presented serious limitations of use with regard to certain methods of manufacturing circuits with very high integration density, at least as regards contacting on doped regions of the semiconductor having a very small thickness and reduced lateral dimensions.
C'est pourquoi, une technique de prise de contacts utilisant un siliciure d'un métal réfractaire, par exemple le siliciure de titane, en tant que matériau pour la prise de contact à la surface du semiconducteur, paraît actuellement préférée dans le domaine de l'intégration à très grande échelle notamment du fait que cette technique permet la création d'îlots de contacts auto-alignés avec les zones de contact prévues à la surface des dispositifs et, dans le cas de transistors MOS, également auto-alignés avec les grilles en silicium polycristallin si on le désire.This is why a contact making technique using a silicide of a refractory metal, for example titanium silicide, as a material for making contact on the surface of the semiconductor, currently appears to be preferred in the field of integration on a very large scale, in particular because this technique allows the creation of self-aligned contact islands with the contact zones provided on the surface of the devices and, in the case of MOS transistors, also self-aligned with the grids polycrystalline silicon if desired.
En ce qui concerne la réalisation des configurations d'interconnexion de niveau supérieur au premier niveau, les recherches se poursuivent pour déterminer quelles sont les techniques les plus convenables notamment en vue d'effectuer des liaisons électriques (verticales) entre les différents niveaux d'interconnexion, dont les dimensions soient de l'ordre de 1 micromètre de diamètre ou moins. En effet une telle réduction des dimensions est souhaitable pour atteindre les très hautes densités d'intégration envisagées. A ce sujet, une difficulté importante provient du fait que les ouvertures de contact dans la couche isolante de séparation sont relativement profondes par rapport à leur diamètre (rapport profondeur/diamètre voisin de l'unité et même supérieur) et que les technique de métallisation classiques ne sont plus utilisables pour remplir convenablement des ouvertures de contact ayant une telle géométrie.Regarding the realization of interconnection configurations higher than the first level, research is continuing to determine which techniques are the most suitable, in particular for making electrical (vertical) connections between the different interconnection levels. , whose dimensions are of the order of 1 micrometer in diameter or less. Indeed, such a reduction in dimensions is desirable in order to achieve the very high integration densities envisaged. In this regard, an important difficulty stems from the fact that the contact openings in the insulating separation layer are relatively deep with respect to their diameter (depth / diameter ratio close to the unit and even greater) and that the conventional metallization techniques are no longer usable for properly filling contact openings having such a geometry.
Parmi les méthodes envisagées pour résoudre cette difficulté, il a été proposé de réaliser la configuration métallique d'interconnexion en deux étapes, une première étape visant à remplir au moins substantiellement les ouvertures de contact avec des éléments localisés d'un métal réfractaire, tungstène ou molybdène, obtenus par exemple par croissance sélective ou encore par dépôt à propriété uniformément recouvrante suivi d'un décapage partiel, et une deuxième étape consistant simplement à recouvrir la structure d'une couche métallique et d'y découper la configuration désirée.Among the methods envisaged to solve this difficulty, it has been proposed to carry out the metallic configuration of interconnection in two stages, a first stage aiming to fill at least substantially the contact openings with localized elements of a refractory metal, tungsten or molybdenum, obtained for example by growth selective or by deposit with uniformly covering property followed by a partial pickling, and a second step consisting simply in covering the structure with a metallic layer and cutting out the desired configuration there.
Des résultats d'essais relatifs à plusieurs procédés de prise de contact et notamment en vue de mettre en oeuvre le procédé mentionné en préambule, sont publiés dans un article intitulé : "The contact properties to TiSi₂ and the adhesion within sub-micron contact holes of etched back CVD W/adhesion layer films", de R.C. Ellwanger, J.E. Schmitz, R.A. Wolters et A.J. van Dijk. "Proceedings of the workshop on tungsten and other refractory metals for VLSI applications", II, 1986.Test results relating to several contacting methods and in particular with a view to implementing the method mentioned in the preamble, are published in an article entitled: "The contact properties to TiSi₂ and the adhesion within sub-micron contact holes of etched back CVD W / adhesion layer films ", by RC Ellwanger, JE Schmitz, RA Wolters and AJ van Dijk. "Proceedings of the workshop on tungsten and other refractory metals for VLSI applications", II, 1986.
Dans le procédé en question, l'opération consistant à réaliser les ouvertures de contact dans la couche isolante est assez critique.In the process in question, the operation consisting in making the contact openings in the insulating layer is quite critical.
En effet, l'arrêt du décapage dans le fond de ces ouvertures est constitué par la couche de siliciure dont la sélectivité de décapage vis à vis de l'oxyde de la couche isolante n'est pas très élevée. Il y a donc des risques que la couche de siliciure soit endommagées lors du décapage des ouvertures de contact.In fact, the stopping of pickling in the bottom of these openings is constituted by the layer of silicide whose pickling selectivity with respect to the oxide of the insulating layer is not very high. There is therefore a risk that the silicide layer will be damaged during the pickling of the contact openings.
La présente invention a notamment pour but de remédier à cette difficulté et de fournir un procédé dans lequel l'opération de décapage des ouvertures de contact est moins critique et préserve l'intégrité de la couche de siliciure en contact avec le matériau semiconducteur.The present invention aims in particular to remedy this difficulty and to provide a method in which the pickling operation of the contact openings is less critical and preserves the integrity of the silicide layer in contact with the semiconductor material.
En effet, selon l'invention, un procédé de fabrication d'une structure d'interconnexion électrique sur un dispositif semiconducteur à substrat de silicium, procédé qui comporte notamment les étapes consistant successivement :
- à créer à la surface du dispositif des zones de contact,
- à former des îlots de contact comprenant au moins une couche de siliciure d'un métal réfractaire tel que le titane, ou le cobalt, recouvrant les zones de contact,
- à former sur l'ensemble une couche isolante dans laquelle sont pratiquées des ouvertures de contact où se trouvent exposées au moins des portions de la surface desdits îlots de contact,
- à réaliser une configuration métallique d'interconnexion en effectuant d'abord un remplissage au moins partiel des ouvertures de contact par des éléments localisés d'un métal réfractaire tel que le tungstène ou le molybdène, puis en recouvrant l'ensemble d'une couche métallique qui est ensuite découpée dans la configuration déterminée, des parties de cette configuration métallique recouvrant les ouvertures de contact et étant en contact électrique avec lesdits éléments localisés, est caractérisé en ce qu'avant d'établir la couche isolante, les îlots de contact sont recouverts d'une couche métallique complémentaire, obtenue par croissance sélective de tungstène ou de molybdène, qui est localisée auxdits îlots.
- to create contact areas on the surface of the device,
- to form contact islands comprising at least one layer of silicide of a refractory metal such as titanium or cobalt, covering the contact zones,
- forming on the assembly an insulating layer in which are made contact openings where there are exposed at least portions of the surface of said contact islands,
- to achieve a metallic interconnection configuration by first performing at least partial filling of the contact openings with localized elements of a refractory metal such as tungsten or molybdenum, then by covering the whole with a metallic layer which is then cut into the determined configuration, parts of this metallic configuration covering the contact openings and being in electrical contact with said localized elements, is characterized in that before establishing the insulating layer, the contact islands are covered a complementary metal layer, obtained by selective growth of tungsten or molybdenum, which is located at said islands.
Ainsi lors du décapage des ouvertures de contact dans la couche isolante, la profondeur du décapage à réaliser est limitée par la couche métallique complémentaire. Or la sélectivité de décapage du matériau isolant, - dioxyde de silicium par exemple - vis-à-vis du tungstène ou du molybdène est excellente, de sorte que l'opération de décapage peut être prolongée sans crainte d'une attaque notable de la couche métallique complémentaire dans le fond de ces ouvertures. Ce procédé permet d'effectuer en toute sécurité des ouvertures de contact qui, sur le même substrat, présentent des limites de profondeur différentes comme cela résulte d'une opération dite de planarisation de la couche isolante.Thus during the stripping of the contact openings in the insulating layer, the depth of the stripping to be carried out is limited by the complementary metallic layer. However, the pickling selectivity of the insulating material - silicon dioxide for example - with respect to tungsten or molybdenum is excellent, so that the pickling operation can be prolonged without fear of a significant attack by the layer complementary metal in the bottom of these openings. This process makes it possible to safely make contact openings which, on the same substrate, have different depth limits as this results from an operation known as planarization of the insulating layer.
D'autre part, comme la couche métallique complémentaire est obtenue directement sous une forme localisée, elle ne nécessite pas l'emploi d'un masque particulier de gravure. On peut également observer que cette couche métallique complémentaire a un rôle qui n'impose pas un contrôle rigoureux de son épaisseur.On the other hand, as the complementary metal layer is obtained directly in a localized form, it does not require the use of a particular etching mask. It can also be observed that this complementary metallic layer has a role which does not impose rigorous control of its thickness.
Enfin, la structure formée par l'association de la couche métallique complémentaire et des éléments localisés en métal réfractaire présente en raison de sa forme, une meilleure résistance mécanique contre les contraintes et notamment les contraintes d'origine thermique.Finally, the structure formed by the association of the complementary metal layer and localized elements of refractory metal has, due to its shape, better mechanical resistance against stresses and in particular stresses of thermal origin.
En pratique, l'épaisseur de la couche métallique complémentaire est choisie entre 20 et 150nm et de préférence entre 50 et 100nm.In practice, the thickness of the complementary metallic layer is chosen between 20 and 150 nm and preferably between 50 and 100 nm.
Dans un premier mode particulier de mise en oeuvre, le procédé selon l'invention est caractérisé en ce que ayant choisi le titane en tant que métal réfractaire pour la réalisation de ladite couche de siliciure, on forme à sa surface une couche de nitrure de titane que l'on utilise comme base pour la croissance sélective de la couche métallique complémentaire.In a first particular embodiment, the method according to the invention is characterized in that, having chosen titanium as the refractory metal for producing said layer of silicide, a layer of titanium nitride is formed on its surface which is used as a basis for the selective growth of the complementary metallic layer.
De préférence cette couche de nitrure de titane est formée par un traitement de conversion en surface de la couche de siliciure de titane à une température comprise entre 700 et 1000°C, sous atmosphère d'azote. On réalise ainsi une base convenable pour la croissance de la couche métallique complémentaire au moyen du traitement thermique qui sert en même temps au recuit de la couche de siliciure de titane.Preferably, this titanium nitride layer is formed by a surface conversion treatment of the titanium silicide layer at a temperature between 700 and 1000 ° C., under a nitrogen atmosphere. A suitable base is thus produced for the growth of the complementary metal layer by means of the heat treatment which is used at the same time for annealing the layer of titanium silicide.
Selon ce mode de mise en oeuvre, la couche métallique complémentaire est de préférence réalisée par la méthode de dépôt chimique en phase vapeur, à une pression réduite comprise entre 0,05 et 2 torr (6,6 à 266 Pa), utilisant la réduction par l'hydrogène de l'hexafluorure de tungstène (ou de l'hexafluorure de molybdène), à une température comprise entre 300 et 500°C et un rapport de débit gazeux hexafluorure/hydrogène compris entre 1/1000 et 1/5.According to this embodiment, the complementary metal layer is preferably produced by the chemical vapor deposition method, at a reduced pressure of between 0.05 and 2 torr (6.6 to 266 Pa), using the reduction with hydrogen from tungsten hexafluoride (or molybdenum hexafluoride), at a temperature between 300 and 500 ° C and a hexafluoride / hydrogen gas flow ratio between 1/1000 and 1/5.
Dans un deuxième mode particulier de mise en oeuvre de l'invention, la protection de la couche de siliciure de titane par une couche de nitrure de titane avant le dépôt de la couche métallique complémentamire n'est plus nécessaire.In a second particular embodiment of the invention, the protection of the titanium silicide layer with a layer of titanium nitride before the deposition of the complementary metal layer is no longer necessary.
Il se caractérise par le fait que dans le procédé de réaction chimique en phase vapeur (LPCVD) qui vient d'être mentionné, on introduit en outre un débit de silane (SiH₄) dont la valeur par rapport au débit de l'hexafluorure de tungstène (ou de molybdène) est compris entre 1/5 et 3/1.It is characterized by the fact that in the chemical vapor reaction process (LPCVD) which has just been mentioned, a silane flow rate (SiH₄) is also introduced, the value of which relative to the flow rate of tungsten hexafluoride (or molybdenum) is between 1/5 and 3/1.
La descriprion qui va suivre en regard des dessins annexés, le tout donné à titre d'exemple non limitatif, fera bien comprendre comment l'invention peut être réalisée.The description which follows with reference to the appended drawings, all given by way of nonlimiting example, will make it clear how the invention can be implemented.
La figure 1 est une coupe schématique et partielle montrant une structure d'interconnexion de circuit intégré susceptible d'être obtenue par le procédé selon l'invention.Figure 1 is a schematic and partial section showing an integrated circuit interconnection structure capable of being obtained by the method according to the invention.
Les figures 2 à 6 illustrent par des vues partielles, en coupe, différentes étapes du procédé selon l'invention pour la prise de contacts électriques sur un dispositif semiconducteur.Figures 2 to 6 illustrate by partial views, in section, different steps of the method according to the invention for making electrical contacts on a semiconductor device.
La figure 1 indique un exemple de structure d'interconnexion effectuant la prise de contacts électriques dans un circuit intégré au silicium, à transistors MOS. Un substrat 10 d'un premier type de conductivité, porte à sa surface des régions dopées de source et de drain 11, 12, d'un deuxième type de conductivité, opposé au premier. Ces régions dopées 11 et 12 ont un pourtour délimité par une couche localisée d'oxyde de champ 13 et sont séparées entre elles par un étroit canal 14 surmonté d'une grille 15 de commande en silicium polycristallin fortement dopé. La grille 15 est isolée du matériau semiconducteur du canal 14 par une couche d'oxyde de grille 16.FIG. 1 shows an example of an interconnection structure making electrical contacts in an integrated circuit with silicon, with MOS transistors. A
Des portions de la couche de silicium polycristallin ayant servi à créer la grille 15 peuvent être maintenues au dessus de l'oxyde de champ 13, pour établir certaines liaisons électriques ; c'est le cas de la bande de liaison représentée en 17. A la surface du dispositif en cours de formation, des zones de contact on été réalisées qui exposent la majeure partie de la surface des régions dopées 11 et 12 ainsi que la surface des grilles 15 et des bandes de liaison 17. Ensuite ont été formés des îlots de contact 20a à 20d comprenant au moins une couche de siliciure d'un métal réfractaire tel que le titane ou le cobalt, et qui ont été obtenus par auto-alignement avec les zones de contact, selon une technique bien connue des spécialistes du domaine.Portions of the polycrystalline silicon layer used to create the
Une couche isolante 22 comporte des ouvertures de contact 23, 24, 25 dont le fond débouche sur des îlots de contact déterminés 20a, 20b, 20d.An
Enfin une configuration d'interconnexion complète la structure du dispositif représenté, cette configuration comportant d'une part des éléments localisés 26 de tungstène ou de molybdène remplissant au moins partiellement les ouvertures de contact 23, 24, 25, et d'autre part des portions 27, 28 d'une couche métallique dite de deuxième niveau, qui peut être réalisée en aluminium par exemple, découpée en une configuration déterminée, et qui recouvre les éléments localisés 26 en vue d'effectuer les liaisons électriques désirées avec les îlots de contact 20a, 20b, 20d.Finally, an interconnection configuration completes the structure of the device shown, this configuration comprising on the one hand localized
Comme il va être exposé dans ce qui suit, le procédé selon l'invention vise à réaliser une structure d'interconnexion notamment du type schématisé à la figure 1 dans lequel, avant d'établir la couche isolante 22, les îlots de contact 20a, 20b, 20c, 20d sont recouverts d'une couche métallique complémentaire obtenue par croissance sélective de tungstène ou de molybdène et qui se trouve de ce fait, localisée à ces îlôts.As will be explained below, the method according to the invention aims to produce an interconnection structure, in particular of the type shown schematically in FIG. 1 in which, before establishing the
Le procédé selon l'invention est décrit en référence aux figures 2 à 6. Il est à noter que l'exemple illustré sur ces figures doit être compris comme étant très général et désignant toute espèce de prise de contact sur un dispositif semiconducteur, que ce soit un contact avec le substrat, avec une région dopée portée par ce substrat, ou encore avec une couche de matériau polycristallin. La figure 2 montre de manière schématique et simplifiée un îlot de contact 20 disposé dans une zone de contact 18 délimitée à la surface d'un substrat semiconducteur 10 au moyen d'une couche diélectrique 19.The method according to the invention is described with reference to FIGS. 2 to 6. It should be noted that the example illustrated in these figures must be understood as being very general and designating any kind of contact making on a semiconductor device, whether this either a contact with the substrate, with a doped region carried by this substrate, or with a layer of polycrystalline material. FIG. 2 shows schematically and simplified a
L'îlot de contact 20 est obtenu de façon auto-alignée avec la zone de contact 18 en déposant une couche d'un métal réfractaire tel que le titane, sur l'ensemble de la structure, puis, par un traitement thermique convenable, à faire localement réagir la couche de titane avec les portions de surface de silicium qui ne sont pas couvertes par la couche diélectrique 19, et former un siliciure de titane à l'emplacement des zones de contact 18, puis enfin en enlevant par décapage sélectif le reste de la couche de titane n'ayant pas réagi. Il est connu et pratiquement nécessaire, à ce stade du procédé de stabiliser la composition de la couche de siliciure de titane en contact avec le matériau de la zone de contact par un deuxième traitement thermique, effectué de préférence sous atmosphère d'azote. C'est pourquoi l'îlot de contact 20 se compose finalement d'une couche de siliciure de titane 201 surmontée d'une mince couche de nitrure de titane 202 obtenue au cours du traitement mentionné par l'action de l'azote sur le siliciure de titane.The
A titre indicatif, un traitement d'une durée de 10 secondes à 850°C, sous azote, conduit à la formation d'une couche de nitrure de titane 202, de 6 à 8nm d'épaisseur, à la surface d'une couche de siliciure de titane 201 de l'ordre de 30nm d'épaisseur.As an indication, a treatment lasting 10 seconds at 850 ° C, under nitrogen, leads to the formation of a layer of
On procède alors à une croissance sélective de tungstène ayant pour objet de recouvrir les îlots de contact 20 par une couche métallique complémentaire, relativement mince.Selective growth of tungsten is then carried out with the aim of covering the
Dans cette opération, la couche de nitrure de titane 202 sert de base de nucléation pour la croissance du tungstène, alors que la couche diélectrique 19 inhibe au contraire cette croissance. Ainsi, la couche métallique complémentaire 30 se trouve localisée aux îlots de contact 20 comme indiqué à la figure 3, sans avoir recours à une opération de photomasquage. Le procédé de croissance sélective du tungstène est connu en tant que tel. Il utilise de préférence la méthode de dépôt en phase vapeur utilisant la réaction chimique de réduction du fluorure de tungstène (WF₆) par l'hydrogène (H₂), à une température comprise entre 300°C et 500°C, et sous une pression réduite de l'ordre de 6,6 à 266Pa (0,05 à 2 torr). Les débits gazeux de WF₆ et d'H₂, introduits lors de la réaction, sont choisis dans un rapport compris entre 1/1000 et 1/5.In this operation, the
La couche métallique complémentaire 30 peut encore, si on le désire, être réalisée par croissance sélective de molybdène selon des conditions opératoires très voisine de celles indiquées pour le tungstène. Dans la réaction indiquée, de réduction d'un hexafluorure de tungstène ou de molybdène par l'hydrogène, la couche de siliciure de titane 201 se trouverait attaquée si elle n'était pas protégée par une couche de nitrure de titane 202. Cette protection toutefois n'est plus indispensable et la couche de nitrure de titane 202 pourrait être omise dans une variante du procédé de dépôt chimique en phase vapeur selon laquelle la réduction de l'hexafluorure est complétée par l'introduction d'un débit de silane (SiH₄) dans les gaz de réaction, de valeur suffisamment faible, comparée au débit de l'hexafluorure, pour que la sélectivité de croissance soit préservée.The
Lorsque le rapport entre le débit de silane et le débit de l'hexafluorure utilisé est choisi dans la gamme de 1/5 à 3/1, un rapport de l'ordre de 1/1 étant particulièrement favorable, la sélectivité du dépôt est bien conservée, l'attaque du siliciure de titane (ou du silicium) est évitée alors que l'incorporation de silicium dans le métal déposé reste si faible qu'elle est difficilement mesurable et peut être considérée comme nulle, en pratique.When the ratio between the silane flow rate and the flow rate of the hexafluoride used is chosen from the range of 1/5 to 3/1, a ratio of the order of 1/1 being particularly favorable, the selectivity of the deposit is good preserved, the attack of titanium silicide (or of silicon) is avoided whereas the incorporation of silicon in the deposited metal remains so weak that it is difficult to measure and can be considered as null, in practice.
Bien qu'en réalité l'épaisseur de la couche métallique complémentaire 30 ne soit pas particulièrement critique, elle est choisie en général entre 20 et 150nm et de préférence entre 50 et 100nm.Although in reality the thickness of the
Au delà de 150nm d'épaisseur, on introduit un relief de topographie indésirable à la surface du dispositif et la durée de l'opération de dépôt est prolongée inutilement. En dessous de 20nm d'épaisseur, la couche métallique complémentaire 30 ne remplit plus complètement son rôle de barrière de décapage et peut présenter des discontinuités résultant de la phase initiale de croissance.Beyond 150nm of thickness, an undesirable topography relief is introduced on the surface of the device and the duration of the deposition operation is unnecessarily prolonged. Below 20nm of thickness, the
Comme représenté à la figure 4 on forme ensuite sur l'ensemble de la structure une couche isolante 32, par exemple en bioxyde de silicium, en utilisant toute méthode convenable par exemple la méthode de dépôt en phase vapeur utilisant l'oxydation d'un composé du silicium.As shown in FIG. 4, an insulating
Il peut être avantageux à ce stade du processus, de faire subir à la couche isolante 32 une opération dite de planarisation qui a pour but de rendre sa surface externe pratiquement plane alors que cette couche isolante repose sur une structure ayant un relief prononcé.It may be advantageous at this stage of the process to subject the insulating
A l'aide d'une opération de photomasquage, on procède au décapage d'ouvertures de contact 33 dans la couche isolante 32 en utilisant de préférence la technique dénommée gravure ionique réactive, qui permet d'obtenir des ouvertures de très petit diamètre, ayant des bords pratiquement verticaux. L'emplacement des ouvertures de contact 33 est tel que ces ouvertures mettent à découvert une portion de la surface de la couche métallique complémentaire 30 recouvrant les îlots de contact. La gravure ionique de la couche isolante 32 utilise de préférence le mélange gazeux CF₄+O₂ ionisé comme milieu chimique d'attaque.Using a photomasking operation, the
Dans ce processus la sélectivité de décapage de l'oxyde de silicium vis-à-vis du tungstène ou du molybdène dépasse un rapport de 30 : 1 de sorte que la couche métallique complémentaire 30 fournit un arrêt de décapage très efficace.In this process the pickling selectivity of silicon oxide with respect to tungsten or molybdenum exceeds a ratio of 30: 1 so that the
Dans le procédé de l'art antérieur, la gravure de la couche isolante 32 se termine sur un îlot de contact formé d'une couche double de nitrure de titane-siliciure de titane. La sélectivité de décapage de l'oxyde de silicium par rapport à ces matériaux n'est que d'un rapport voisin de 10 : 1. Le procédé selon l'invention permet donc de terminer le décapage des ouvertures de contact 33 sans risque de sous-gravure excessive et de dégradation de la couche de siliciure de titane. Cet avantage est particulièrement important lorsque sur un même substrat, des ouvertures de contact de différentes profondeurs doivent être décapées simultanément ainsi que cela a été représenté à la figure 1 pour les ouvertures de contact 23 et 25. Le masque de laque photosensible ayant servi à définir les ouvertures de contact 33 (non représenté sur la figure), est éliminé par exemple au moyen d'un décapage par plasma d'oxygène.In the method of the prior art, the etching of the insulating
La structure au stade représenté à la figure 4 est alors soumise à un nettoyage complémentaire de sa surface utilisant les bains chimique usuels en la matière, comme par exemple, un trempage dans l'acide nitrique puis dans de l'acide fluorhydrique dilué, suivi d'un rinçage soigneux dans de l'eau désionisée et d'un séchage par centrifugation.The structure at the stage shown in FIG. 4 is then subjected to an additional cleaning of its surface using the usual chemical baths in the material, such as, for example, soaking in nitric acid and then in dilute hydrofluoric acid, followed by careful rinsing in deionized water and drying by centrifugation.
L'opération suivante a pour but de remplir, au moins pour une partie substantielle de leur volume, les ouvertures de contact 33 par des éléments localisés d'un métal réfractaire tel que le tungstène ou le molybdène.The purpose of the following operation is to fill, at least for a substantial part of their volume, the
Des éléments localisés 26 tels qu'illustrés à la figure 5A peuvent être obtenus par un procédé de croissance sélective de tungstène ou de molybdène dans des conditions opératoires qui sont sensiblement les mêmes que pour la réalisation de la couche métallique complémentaire 30.
De préférence on utilisera le même métal, tungstène par exemple, pour former la couche métallique complémentaire 30 et les éléments localisés 26, ceci pour des raisons de simplicité et d'économie d'équipements notamment.Preferably, the same metal, tungsten for example, will be used to form the
Toutefois, cela n'est pas indispensable et on pourrait également réaliser la couche métallique complémentaire 30 en molybdène et faire croître ensuite des éléments localisés 26 en tungstène, ou inversement si on le désire, en fonction de circonstances particulières. Dans tous les cas, la surface métallique de la couche complémentaire 30 qui est exposée dans les ouvertures de contact 33 sert de base de nucléation pour la croissance sélective des éléments localisés 26, alors que sur la surface libre 34 de la couche isolante 32 la croissance ne se produit pas.However, this is not essential and the additional
Dans une application typique de circuit à haute intégration, les ouvertures de contact 33 ont un diamètre de 0,8µm et une profondeur qui peut varier de 0,5 à 0,9µm en fonction de la position de ces ouvertures.In a typical application of a highly integrated circuit, the
La durée de la croissance est déterminée de manière à ce que les ouvertures de contact les moins profondes soient remplies à l'excès et présentent des éléments localisés 26 dont le niveau supérieur forme une excroissance qui dépasse un peu le niveau de la couche isolante environnante et qui s'élargit latéralement mais toutefois sans que cela soit gênant pour le fonctionnement du dispositif.The duration of the growth is determined so that the shallowest contact openings are overfilled and have localized
Le cas d'une telle ouverture de contact remplie à l'excès est représenté à la figure 1 pour l'ouverture de contact 25. Les ouvertures de contact les plus profondes, au contraire, pendant le même dépôt, ne sont pas remplies complètement par les éléments localisés 26 comme cela a été représenté pour les ouvertures de contact 23 et 24 de la figure 1.The case of such a contact opening filled at the excess is shown in FIG. 1 for the
Ceci ne représente pas un inconvénient sérieux puisque la partie non remplie d'une telle ouverture de contact a un rapport d'aspect (profondeur/diamètre) qui est maintenant très inférieur à l'unité et dont le remplissage ultérieur par des techniques classiques de métallisation peut facilement être obtenu.This does not represent a serious drawback since the part not filled with such a contact opening has an aspect ratio (depth / diameter) which is now much less than the unit and whose subsequent filling by conventional metallization techniques can easily be obtained.
La réalisation des éléments localisés 26 est obtenue de manière directe et économique par le procédé de croissance sélective qui vient d'être mentionné. Cela n'est toutefois pas essentiel au regard de l'invention qui est basée essentiellement sur le recouvrement des îlots de contact par une couche complémentaire 30 de tungstène ou de molybdène.The realization of the
Les éléments localisés 26 peuvent encore être obtenus de manière indirecte, par exemple selon un processus qui va être décrit en se référant aux figures 5B et 5C.The
Comme représenté à la figure 5B, on dépose sur toute la surface, y compris la surface intérieure des ouvertures de contact 33 une couche d'adhésion 40, qui est mince vis-à-vis des dimensions des ouvertures de contact, par exemple 100nm d'un alliage de titane-tungstène (10%Ti, 90%W en poids).As shown in FIG. 5B, an
Il est important d'utiliser à cet effet un procédé de dépôt comme la pulvérisation cathodique qui assure une couverture pratiquement conforme de la surface, indépendamment de son relief, et dont l'épaisseur est sensiblement constante même à l'intérieur des ouvertures de contact.It is important to use for this purpose a deposition process such as sputtering which provides a substantially consistent coverage of the surface, regardless of its relief, and whose thickness is substantially constant even inside the contact openings.
Sur la couche d'adhésion 40 on fait croître ensuite une couche de remplissage 41 en tungstène en utilisant également un procédé de dépôt à propriété de recouvrement conforme, comme le procédé de dépôt en phase vapeur, à pression réduite. L'épaisseur de la couche de remplissage 41 est ici choisie suffisante pour remplir entièrement les ouvertures de contact 33 c'est-à-dire qu'elle est d'une valeur qui est au minimum de la moitié du diamètre de ces ouvertures.Next, on the
La couche d'adhésion et la couche de remplissage sont ensuite éliminées de la surface de la couche isolante 32 pour ne laisser subsister que les portions de ces couches qui sont situées à l'intérieur des ouvertures de contact 33 et forment ainsi des éléments localisés métalliques 26 comme indiqué à la figure 5C. Cette opération peut être réalisée par décapage dans un plasma de SF₆ qui attaque plus vite le tungstène et l'alliage titane-tungstène que l'oxyde de silicium.The adhesion layer and the filling layer are then removed from the surface of the insulating
L'élément localisé 26 fournit une partie d'une configuration métallique d'interconnexion. Comme indiqué figure 6 l'autre partie complémentaire, est réalisée en recouvrant la surface 34 du dispositif d'une couche métallique 35 dont les portions autres que celles de la configuration désirée sont éliminées par un décapage sélectif, localisé au moyen d'un masque de laque photosensible par exemple.The
La surface 34 sur laquelle repose la couche métallique 35 a, de préférence, été rendue sensiblement plane, de sorte que cette couche métallique 35 peut être obtenue sans difficulté en utilisant des techniques courantes. De nombreux métaux peuvent convenir pour réaliser cette opération et le choix sera guidé par les exigences d'adhérence mécanique à la surface de la couche isolante 32, par la recherche d'un minimum de conductivité électrique, et d'une bonne résistance au phénomène d'électromigration. A titre d'exemple, une couche d'aluminium ou d'un alliage d'aluminium-cuivre, de 0,8 à 1 µm d'épaisseur convient très bien. Bien entendu, des parties de la couche métallique 35 recouvrent les ouvertures de contact 33 pour y assurer la liaison électrique avec les éléments localisés 26.The
Bien que ceci n'a pas été réprésenté sur les figures, on peut compléter le dispositif, si on le désire, et en fonction de sa complexité, par au moins une configuration métallique d'interconnexion supplémentaire, établie à un niveau supérieur.Although this has not been shown in the figures, the device can be completed, if desired, and depending on its complexity, by at least one additional metallic interconnection configuration, established at a higher level.
Le procédé selon l'invention n'est pas limité à la fabrication d'une structure d'interconnexion sur un circuit intégré à transistors MOS. Il vise plus généralement la prise de contacts sur toute sorte de dispositifs semiconducteurs à substrat de silicium et de préférence lorsqu'on désire utiliser des zones de contact de très petites dimensions et y pratiquer des îlots de contact en siliciure d'un métal réfractaire autoalignés avec lesdites zones de contact.The method according to the invention is not limited to the fabrication of an interconnection structure on an integrated circuit with MOS transistors. It is more generally aimed at making contacts on all kinds of semiconductor devices with a silicon substrate and preferably when it is desired to use contact areas of very small dimensions and to practice thereon contact islands of refractory metal silicide self-aligned with said contact areas.
Claims (6)
- A method of manufacturing a structure of electrical interconnections on a semiconductor device having a silicon substrate, this method comprising especially the following successive steps:- producing contact zones at the surface of the semiconductor device,- forming contact islands comprising at least one layer of a silicide of a refractory metal, such as titanium or cobalt, covering the contact zones,- forming on the assembly an insulating layer in which contact openings are provided, in which at least portions of the surface of the said contact islands are exposed,- obtaining a metal interconnecting configuration by first carrying out a step of at least partly filling the contact openings with localized elements of a refractory metal, such as tungsten or molybdenum, and by then covering the assembly with a metal layer, which is subsequently cut into a given configuration, parts of this metal configuration covering the contact openings and being in electrical contact with the said localized elements,characterized in that, before the insulating layer is formed, the contact islands are covered by a complementary metal layer obtained by selective growth of tungsten or molybdenum, which is localized at the said islands.
- A method as claimed in Claim 1, characterized in that the thickness of the said complementary metal layer is chosen to lie between 20 and 150 nm and preferably between 50 and 100 nm.
- A method as claimed in any one of Claims 1 or 2, characterized in that, when titanium is chosen as the refractory metal for the formation of the said silicide layer, at its surface a layer of titanium nitride is formed which is used as a base for the selective growth of the complementary metal layer.
- A method as claimed in Claim 3, characterized in that the said titanium nitride layer is formed by a conversion treatment at the surface of the titanium silicide layer at a temperature of between 700 and 1000°C in a nitrogen atmosphere.
- A method as claimed in any one of Claims 1 to 4, characterized in that the complementary metal layer is formed by the method of chemical deposition from the vapour phase at a reduced pressure of between 6.6 and 266 Pa utilizing the reduction by hydrogen of tungsten hexafluoride (or molybdenum hexafluoride) at a temperature of between 300 and 500°C and a gas flowrate ratio hexafluoride/hydrogen of between 1/1000 and 1/5.
- A method as claimed in Claim 5, characterized in that moreover a flow of silane, of which the flowrate has a ratio to the flowrate of hexa-fluoride which is chosen to lie between 1/5 and 3/1, is introduced into the reaction gases of the aforementioned chemical deposition process.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR8716873A FR2624304B1 (en) | 1987-12-04 | 1987-12-04 | METHOD FOR ESTABLISHING AN ELECTRICAL INTERCONNECTION STRUCTURE ON A SILICON SEMICONDUCTOR DEVICE |
FR8716873 | 1987-12-04 |
Publications (2)
Publication Number | Publication Date |
---|---|
EP0325808A1 EP0325808A1 (en) | 1989-08-02 |
EP0325808B1 true EP0325808B1 (en) | 1992-08-19 |
Family
ID=9357493
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP88202724A Expired - Lifetime EP0325808B1 (en) | 1987-12-04 | 1988-11-30 | Process for producing an electric connexion on a silicon semiconductor device |
Country Status (6)
Country | Link |
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US (1) | US4851369A (en) |
EP (1) | EP0325808B1 (en) |
JP (1) | JP2685253B2 (en) |
KR (1) | KR890011042A (en) |
DE (1) | DE3873903T2 (en) |
FR (1) | FR2624304B1 (en) |
Families Citing this family (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4970573A (en) * | 1986-07-01 | 1990-11-13 | Harris Corporation | Self-planarized gold interconnect layer |
US4981550A (en) * | 1987-09-25 | 1991-01-01 | At&T Bell Laboratories | Semiconductor device having tungsten plugs |
US4962414A (en) * | 1988-02-11 | 1990-10-09 | Sgs-Thomson Microelectronics, Inc. | Method for forming a contact VIA |
US5104826A (en) * | 1989-02-02 | 1992-04-14 | Matsushita Electric Industrial Co., Ltd. | Method for fabricating semiconductor integrated circuit device using an electrode wiring structure |
DE69033424T2 (en) * | 1989-09-11 | 2000-06-21 | Texas Instruments Inc., Dallas | Process for making a protective barrier from silicide zones |
US5141897A (en) * | 1990-03-23 | 1992-08-25 | At&T Bell Laboratories | Method of making integrated circuit interconnection |
JP2720567B2 (en) * | 1990-03-28 | 1998-03-04 | ソニー株式会社 | Method for manufacturing semiconductor device |
US5213999A (en) * | 1990-09-04 | 1993-05-25 | Delco Electronics Corporation | Method of metal filled trench buried contacts |
EP0491433A3 (en) * | 1990-12-19 | 1992-09-02 | N.V. Philips' Gloeilampenfabrieken | Method of forming conductive region on silicon semiconductor material, and silicon semiconductor device with such region |
US5298463A (en) * | 1991-08-30 | 1994-03-29 | Micron Technology, Inc. | Method of processing a semiconductor wafer using a contact etch stop |
US5252518A (en) * | 1992-03-03 | 1993-10-12 | Micron Technology, Inc. | Method for forming a mixed phase TiN/TiSi film for semiconductor manufacture using metal organometallic precursors and organic silane |
US5187120A (en) * | 1992-08-24 | 1993-02-16 | Hewlett-Packard Company | Selective deposition of metal on metal nitride to form interconnect |
JP2616551B2 (en) * | 1993-11-16 | 1997-06-04 | 日本電気株式会社 | Semiconductor device and manufacturing method thereof |
US6001729A (en) * | 1995-01-10 | 1999-12-14 | Kawasaki Steel Corporation | Method of forming wiring structure for semiconductor device |
JPH08191054A (en) * | 1995-01-10 | 1996-07-23 | Kawasaki Steel Corp | Semiconductor device and manufacturing method thereof |
US5545592A (en) * | 1995-02-24 | 1996-08-13 | Advanced Micro Devices, Inc. | Nitrogen treatment for metal-silicide contact |
US5856236A (en) * | 1996-06-14 | 1999-01-05 | Micron Technology, Inc. | Method of depositing a smooth conformal aluminum film on a refractory metal nitride layer |
JPH1064848A (en) * | 1996-08-13 | 1998-03-06 | Toshiba Corp | Method and device for manufacturing semiconductor device |
US5856237A (en) * | 1997-10-20 | 1999-01-05 | Industrial Technology Research Institute | Insitu formation of TiSi2/TiN bi-layer structures using self-aligned nitridation treatment on underlying CVD-TiSi2 layer |
US7858518B2 (en) | 1998-04-07 | 2010-12-28 | Micron Technology, Inc. | Method for forming a selective contact and local interconnect in situ |
US6524956B1 (en) * | 1999-09-24 | 2003-02-25 | Novelius Systems, Inc. | Method for controlling the grain size of tungsten films |
US6429126B1 (en) * | 2000-03-29 | 2002-08-06 | Applied Materials, Inc. | Reduced fluorine contamination for tungsten CVD |
US7071563B2 (en) | 2001-09-28 | 2006-07-04 | Agere Systems, Inc. | Barrier layer for interconnect structures of a semiconductor wafer and method for depositing the barrier layer |
US8435873B2 (en) | 2006-06-08 | 2013-05-07 | Texas Instruments Incorporated | Unguarded Schottky barrier diodes with dielectric underetch at silicide interface |
US10454114B2 (en) | 2016-12-22 | 2019-10-22 | The Research Foundation For The State University Of New York | Method of producing stable, active and mass-producible Pt3Ni catalysts through preferential co etching |
Family Cites Families (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB216841A (en) * | 1923-05-31 | 1924-10-23 | Eugene Marie Bournonville | Improvements in rotary valves particularly for internal combustion engines |
US3601666A (en) * | 1969-08-21 | 1971-08-24 | Texas Instruments Inc | Titanium tungsten-gold contacts for semiconductor devices |
US4107726A (en) * | 1977-01-03 | 1978-08-15 | Raytheon Company | Multilayer interconnected structure for semiconductor integrated circuit |
US4121241A (en) * | 1977-01-03 | 1978-10-17 | Raytheon Company | Multilayer interconnected structure for semiconductor integrated circuit |
JPS5713753A (en) * | 1980-06-30 | 1982-01-23 | Fujitsu Ltd | Manufacture of semiconductor device |
US4339869A (en) * | 1980-09-15 | 1982-07-20 | General Electric Company | Method of making low resistance contacts in semiconductor devices by ion induced silicides |
JPS57114274A (en) * | 1981-01-08 | 1982-07-16 | Nippon Telegr & Teleph Corp <Ntt> | Electrode for semiconductor device and manufacture thereof |
JPS584924A (en) * | 1981-07-01 | 1983-01-12 | Hitachi Ltd | Forming method for semiconductor device electrode |
JPS5974668A (en) * | 1982-09-20 | 1984-04-27 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | Integrated circuit contact structure |
DE3301666A1 (en) * | 1983-01-20 | 1984-07-26 | Brown, Boveri & Cie Ag, 6800 Mannheim | METHOD FOR PRODUCING A MULTI-LAYER CONTACT METALIZATION |
DE3314879A1 (en) * | 1983-04-25 | 1984-10-25 | Siemens AG, 1000 Berlin und 8000 München | METHOD FOR PRODUCING STABLE, LOW-RESISTANT CONTACTS IN INTEGRATED SEMICONDUCTOR CIRCUITS |
US4545116A (en) * | 1983-05-06 | 1985-10-08 | Texas Instruments Incorporated | Method of forming a titanium disilicide |
JPS6050920A (en) * | 1983-08-30 | 1985-03-22 | Toshiba Corp | Manufacture of semiconductor device |
US4507852A (en) * | 1983-09-12 | 1985-04-02 | Rockwell International Corporation | Method for making a reliable ohmic contact between two layers of integrated circuit metallizations |
JPS6072272A (en) * | 1983-09-28 | 1985-04-24 | Toshiba Corp | Manufacturing method of semiconductor device |
JPS60245256A (en) * | 1984-05-21 | 1985-12-05 | Fujitsu Ltd | Semiconductor device |
US4672419A (en) * | 1984-06-25 | 1987-06-09 | Texas Instruments Incorporated | Metal gate, interconnect and contact system for VLSI devices |
US4641420A (en) * | 1984-08-30 | 1987-02-10 | At&T Bell Laboratories | Metalization process for headless contact using deposited smoothing material |
GB2168841B (en) * | 1984-12-22 | 1988-07-20 | Stc Plc | Semiconductor processing |
US4804636A (en) * | 1985-05-01 | 1989-02-14 | Texas Instruments Incorporated | Process for making integrated circuits having titanium nitride triple interconnect |
ATE46791T1 (en) * | 1985-07-29 | 1989-10-15 | Siemens Ag | METHOD FOR SELECTIVE FILLING OF CONTACT HOLES ETCHED IN INSULATING LAYERS WITH METALLIC CONDUCTIVE MATERIALS IN THE MANUFACTURE OF HIGHLY INTEGRATED SEMICONDUCTOR CIRCUITS AND A DEVICE FOR CARRYING OUT THE METHOD. |
JPS6231116A (en) * | 1985-08-02 | 1987-02-10 | Toshiba Corp | Manufacture of semiconductor device |
SE8603963L (en) * | 1985-09-27 | 1987-03-28 | Rca Corp | CONTACT WITH LAW RESISTANCE FOR A SEMICONDUCTOR ORGAN AND SETTING TO MAKE IT |
DE3534600A1 (en) * | 1985-09-27 | 1987-04-02 | Siemens Ag | INTEGRATED CIRCUIT WITH ELECTRICAL TRACKS AND METHOD FOR THEIR PRODUCTION |
JPH0611076B2 (en) * | 1985-10-08 | 1994-02-09 | 三菱電機株式会社 | Method for manufacturing semiconductor device |
US4690730A (en) * | 1986-03-07 | 1987-09-01 | Texas Instruments Incorporated | Oxide-capped titanium silicide formation |
EP0275299A1 (en) * | 1986-07-31 | 1988-07-27 | AT&T Corp. | Semiconductor devices having improved metallization |
DE3777538D1 (en) * | 1986-11-10 | 1992-04-23 | American Telephone & Telegraph | Tungsten Metallization. |
JPS6453573A (en) * | 1987-05-04 | 1989-03-01 | Texas Instruments Inc | Semiconductor device and its manufacture |
-
1987
- 1987-12-04 FR FR8716873A patent/FR2624304B1/en not_active Expired - Lifetime
-
1988
- 1988-11-07 US US07/268,149 patent/US4851369A/en not_active Expired - Lifetime
- 1988-11-30 EP EP88202724A patent/EP0325808B1/en not_active Expired - Lifetime
- 1988-11-30 DE DE8888202724T patent/DE3873903T2/en not_active Expired - Fee Related
- 1988-12-01 JP JP63302336A patent/JP2685253B2/en not_active Expired - Fee Related
- 1988-12-02 KR KR1019880016047A patent/KR890011042A/en not_active Application Discontinuation
Also Published As
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KR890011042A (en) | 1989-08-12 |
FR2624304B1 (en) | 1990-05-04 |
DE3873903T2 (en) | 1993-03-11 |
US4851369A (en) | 1989-07-25 |
FR2624304A1 (en) | 1989-06-09 |
DE3873903D1 (en) | 1992-09-24 |
JPH021981A (en) | 1990-01-08 |
JP2685253B2 (en) | 1997-12-03 |
EP0325808A1 (en) | 1989-08-02 |
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