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EP0253227B1 - Vorrichtung zum Programmieren einer nichtflüchtigen Speichervorrichtung für ein Uhrwerk - Google Patents

Vorrichtung zum Programmieren einer nichtflüchtigen Speichervorrichtung für ein Uhrwerk Download PDF

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Publication number
EP0253227B1
EP0253227B1 EP87109566A EP87109566A EP0253227B1 EP 0253227 B1 EP0253227 B1 EP 0253227B1 EP 87109566 A EP87109566 A EP 87109566A EP 87109566 A EP87109566 A EP 87109566A EP 0253227 B1 EP0253227 B1 EP 0253227B1
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EP
European Patent Office
Prior art keywords
frequency
timepiece
voltage
period
predetermined
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
EP87109566A
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English (en)
French (fr)
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EP0253227A1 (de
Inventor
Arthur Descombes
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EM Microelectronic Marin SA
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EM Microelectronic Marin SA
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Application filed by EM Microelectronic Marin SA filed Critical EM Microelectronic Marin SA
Publication of EP0253227A1 publication Critical patent/EP0253227A1/de
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Expired legal-status Critical Current

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    • G—PHYSICS
    • G04—HOROLOGY
    • G04D—APPARATUS OR TOOLS SPECIALLY DESIGNED FOR MAKING OR MAINTAINING CLOCKS OR WATCHES
    • G04D7/00—Measuring, counting, calibrating, testing or regulating apparatus
    • G04D7/002—Electrical measuring and testing apparatus
    • G04D7/003—Electrical measuring and testing apparatus for electric or electronic clocks
    • G—PHYSICS
    • G04—HOROLOGY
    • G04G—ELECTRONIC TIME-PIECES
    • G04G3/00—Producing timing pulses
    • G04G3/02—Circuits for deriving low frequency timing pulses from pulses of higher frequency
    • G04G3/022—Circuits for deriving low frequency timing pulses from pulses of higher frequency the desired number of pulses per unit of time being obtained by adding to or substracting from a pulse train one or more pulses

Definitions

  • the present invention relates to a device for programming an electrically alterable non-volatile memory for timepieces, said part comprising an oscillator, a frequency divider with several stages, the rate of division of which is to be adjusted by alteration of a number k of pulses delivered by a stage of the divider, the number k being representative of the frequency difference existing between the frequency of the oscillator and a standard frequency and being in a binary form written in the memory not volatile to modify, at regular intervals, the content of certain determined stages of the divider, a stepping motor receiving driving pulses coming from the divider to display the time in analogical manner and a housing for receiving a supply battery.
  • the cited patent proposes, on the one hand, to eliminate certain operations for adjusting the frequency of the quartz and consequently to lower its cost price while improving its stability and, on the other hand, to remove any electronic system from adjustment (trimmer) at the time base.
  • the divider has auxiliary electrical inputs whose logic state determines the division ratio
  • the timepiece includes a memory, connected to these auxiliary inputs, for retaining in coded form the information determining the division ratio by acting on these auxiliary inputs.
  • the system which has just been briefly described requires a relatively complex arrangement of the integrated circuit incorporated in the watch.
  • it includes a whole timed sequence circuit for programming control which starts when the power is brought to 6.3 volts. It also requires several detectors of different voltage levels.
  • the present invention provides an internal circuit to the watch which is simpler, which lowers the cost and increases its reliability.
  • the complexity of the programming circuits is transferred above all to an accessory external to the watch, which in itself poses no problem and rids the timepiece of a large number of elements or components that are only used when of programming. To do this, the means which appear in the claims are used.
  • FIG. 1 is a schematic representation of the device used according to the invention.
  • the timepiece 1 is here a wristwatch comprising a case 2, hands 3 driven by a stepping motor not shown and a battery housing 4 normally intended to receive a power source.
  • the watch also includes an integrated electronic circuit 5 powered by contacts 6 and 6 'leading to the battery housing.
  • the connector is provided with terminals 9 and 9 'which come into contact with contacts 6 and 6' of the watch.
  • the connector is connected to a measuring and adjusting device 10 by a cable 11.
  • the device 10 is connected to the industrial network by the cord 12.
  • the frequency of the internal oscillator of the watch can be measured by means of inductive or capacitive sensors which pick up the engine advance steps or the vibrations emitted by the quartz of the timepiece.
  • Quartz is generally cut so that its frequency is higher than the standard frequency, although there are systems where the frequency of the quartz is kept lower than the standard frequency.
  • the frequency divider is then adjusted by altering its division rate represented by a number k of pulses delivered by a stage of the divider.
  • pulses will be suppressed, which leads to the well-known inhibition systems.
  • less common we will add missing pulses. All the description which follows is based on the inhibition system, but the invention could be extended to the pulse addition system by analogy.
  • the number of bits is 6 which also indicates the number of divisors by 2 which will be affected by the correction.
  • the programming device comprises first means 14 controlled by the end of a driving pulse produced by the watch motor to introduce into certain determined stages of the divider of said watch a binary state corresponding to the number k of pulses measured by the device 10, and second means 5 to block the content of said stages as soon as the binary state in question is reached, then to write said content in the non-volatile memory.
  • This programming phase can be followed by a control phase in fast mode which makes it possible to check that the memory has indeed been programmed by the desired binary value.
  • the timepiece is removed from its setting, then fitted with a battery. From this moment the watch operates normally and the inhibition is executed with the periodicity which has been chosen.
  • FIG. 2 is a detailed diagram of the electronic circuit contained inside the watch, that is circuit 5 shown diagrammatically in FIG. 1.
  • a quartz 20 driving an oscillator 21 supplying a frequency at 32,768 Hz. This frequency is divided several times.
  • the frequency at 1 Hz drives a driver circuit 31 which in turn controls the stepping motor M which thus advances by one step per second.
  • the outputs Q1 to Q6 of each of the stages 24 to 29 are connected to the corresponding recording inputs of an electrically alterable non-volatile memory at 6 bits 32. All the elements of the circuit 5 are supplied by the voltage + V / -V in from the external circuit 14 linked to the connector 8.
  • the memory 32 is well known from the state of the art. A detailed description can be found, for example, in the book “Jeck der annometrie” volume 33, 1982, pages 47 to 55 under the title: “Non-volatile EEPROM memories, application to digital adjustment of a watch to quartz”. Suffice it to recall here that this type of memory can be programmed by the data present at its inputs by raising for a certain time (approximately 250 ms) its supply voltage at the same time as it is supplied to its PRGM input a registration authorization signal. The supply voltage required for registration is here of the order of 6V. Note that the memory is provided with internal amplifiers which raise this voltage to a value greater than 25V.
  • the authorization signal is itself supplied by a voltage detector 33, the output of which is 0 if the applied voltage is below a certain threshold and 1 if this voltage is above this threshold.
  • the detector 33 can be a comparator, for example an operational circuit.
  • the threshold is fixed at 3.5V, which means that the detector supplies a signal 0 when the supply voltage is at low level (for example 1.5V) and a signal 1 when this voltage is at high level (for example 6V).
  • FIG. 2 also shows that the output signal PRGM of the detector 33 is connected via an inverter 34 to a first input of an AND gate 35, the second input of this gate receiving pulses at 8 kHz from of the divider 23.
  • the output of the AND gate 35 is connected to the input of the chain of dividers 24 to 29.
  • FIG. 3 is a detailed diagram of the electronic circuit contained in the measuring device, outside the watch, that is circuit 14 shown diagrammatically in FIG. 1.
  • This circuit is equipped with a quartz time base 60 which delivers a frequency roughly tuned to the frequency of the watch's oscillator, here 32 kHz.
  • the signal at 32 kHz is applied to a first divider by 4 referenced 61 and which supplies a signal at 8 kHz.
  • the signal at 8 kHz in turn attacks a six-stage divider or down memory or memory 62 to 67 of the same binary weight as the six-stage divider 24 to 29 contained in the watch circuit.
  • Each stage of the down-counter has an input S (set) through which a binary value supplied by a corresponding AND gate 68 to 73 can be entered.
  • the first input of each of the AND gates leads to a switch 74 to 79 whose terminals switching are connected respectively to the. + and - of a DC power supply V.
  • the position of each of the switches is representative of the number k itself representative of the frequency difference between the frequency of the watch oscillator and a frequency standard, this difference being measured by the apparatus 10 in FIG. 1 as explained above.
  • the second inputs of AND gates 68 to 73 are connected together and receive an output signal from a flip-flop D 80 whose input D is connected to the value + V.
  • the clock input CI of the flip-flop 80 receives the output signal from an OR gate 81 itself provided with three inputs 82, 83 and 84.
  • the internal circuit 5 of the watch is supplied by terminals 9 and 9 ′, ie by a first power source at 1.5V through a switch 86, or by a second power source at 6V through a switch 87. In series in this supply there is a resistance Rm.
  • the input 84 of the OR gate 81 receives it , through the inverter 85, a signal 92 representative of the current Imot in the motor coil when the latter is supplied.
  • FIG. 3 also shows that the output 90 of the down-counting divider 62 to 67 is connected both to the input R of the flip-flop 80, to the input of a monostable flip-flop 89 and to the input S of an RS 88 flip-flop.
  • the output of the monostable 89 is connected to the R input of the RS 88 flip-flop whose output 0 controls the switch 86 and whose output Q controls the switch 87.
  • the flip- flop 88 thus plays the role of a switch enabling the circuit 5 of the watch to be supplied either with a low level voltage (1.5V) or with a high level voltage (6V) via the switch 87.
  • the apparatus 10 measures the frequency difference existing between the frequency of the watch oscillator and the standard frequency. This difference is expressed by a number k which is in binary form. Let 21 be this number which is written 101010 in 6-bit binary notation. This binary value is present in circuit 14 thanks to switches 74 to 79 positioned as illustrated in FIG. 3.
  • the binary state introduced into the dividers 24 to 29 (Q1 to Q6) of the circuit 5 corresponds to the emission of the pulse 91 from the last down-counter 67 of the circuit 14. It s' So now acts to block the content of the dividers 24 to 29 which corresponds to the binary number to be introduced into the non-volatile memory 32. To do this, the pulse 91 is introduced at the input S of the RS 88 flip-flop. moment its output Ci goes to zero and its output Q goes to 1 which has the effect of supplying circuit 5 of the watch with a high level voltage (6V) by the switch 87 which is activated.
  • 6V high level voltage
  • This high-level voltage has the effect of providing a signal 1 at the output of the voltage detector 33 (PRGM) which blocks the AND gate 35 by the inverter 34.
  • PRGM voltage detector 33
  • the non-volatile memory 32 is then supplied with a high level voltage and is thus predisposed to accept the writing of the binary value present at the outputs Q1 to Q6 of the dividers 24 to 29.
  • This writing requires a certain time which can be estimated at around 250 ms.
  • the duration of this registration period Ti is determined by the monostable flip-flop 89 contained in the external circuit 14 and which is controlled by the rising edge 94 of the pulse 91.
  • the flip-flop 89 therefore starts its counting time Ti at the same time as the high level voltage is applied to the memory 32.
  • the end of the period Ti resets the flip-flop 88 which toggles which has the effect of opening the switch 87 and closing the switch 86. From this instant, circuit 5 of the watch is again supplied with the low-level voltage of 1.5V and the programming phase is completed (PRGM signal at zero).
  • the programming phase which has been described above takes as reference the current caused by the driving pulse making the motor advance by one step. For this, only the battery terminals are necessary. If we had access to the motor terminals M1 and M2, we could use the same device as shown in Figure 3. In this case the motor terminals would be connected to additional inputs 97 and 98 of circuit 14, these terminals being connected respectively to inputs 82 and 83 of the OR circuit 81, the operation of the entire device remaining exactly the same.
  • the non-volatile memory programming device which has just been described in detail constitutes the main object of the present invention.
  • the internal circuit of the watch enabling this programming is sufficient with a single additional element in addition to the conventional elements present when it comes to inhibition: the voltage level detector 33.
  • the access to the battery terminals is sufficient to program the memory and this at the cost of an internal circuit whose complexity is reduced to its simplest expression.
  • the watch When the watch's power supply battery is reinstalled in its housing, the watch works normally with the inhibition imposed on it by the binary number written in the memory and this with a periodicity which has been discussed above.
  • the manner in which inhibition is carried out is known from the state of the art and is therefore not part of the present invention. However, it is believed that it should be described here for the sake of presenting a description which is complete and complete.
  • FIG. 5 presents on the first line the alternating driving pulses M1 and M2 and emitted every second.
  • Line 2 shows an inhibition authorization signal (ENINH) triggered every 60 seconds by a driving pulse M1.
  • Line 3 is the actual inhibition signal that is created while the ENINH signal lasts.
  • the dividers 24 to 29 are supplied through the AND gate 35 which is conducting for the pulses at 8 kHz designated by 8kP and delivered by the divider 23.
  • the divider 23 also supplies pulses at 8 kHz designated by 8kPl which are always inserted between the 8kP pulses.
  • the signal of 1 s which appears at the output of the divider 30 is applied to the input of the divider by 60 referenced 52.
  • the output of this divider produces every 60 seconds a pulse designated by 60sP which is applied to the input of the AND gate 48.
  • the gate 48 allows the 60sP pulse to pass and, through the OR circuit 50, causes the flip-flop RS 51 to toggle whose output Q goes to 1.
  • the signals of lines A and B are produced by the divider 30 and are decoding signals making it possible to fix the moment when the signal ENINH must be activated by signed by 128HP, but only once every 60 seconds, the signal ENINH.
  • This signal is applied to an input of AND gate 47 and predisposes said gate to be on when all of its other inputs are at 1.
  • the upper inputs of AND gate 47 are connected to outputs Q1 to Q6 of dividers 24 to 29 and pass all at 1 just before the next 128HP pulse marked with dotted lines in FIG. 6 appears.
  • an 8kP1 intermediate pulse is emitted and the AND gate 47 is on and produces the inhibition pulse INH.
  • the non-volatile memory presents at its outputs Q1 M to Q6M the binary value which has been programmed there according to the process indicated above. This value is carried over to the first inputs of the AND circuits 40 to 45.
  • the binary value, chosen at 101010 is carried over to the inputs R1 to R6 of the dividers 24 to 29 and modifies the content of said dividers as indicated in the diagram in FIG. 6.
  • inhibition pulse INH is used to reset the RS 51 flip-flop to zero, which ends the signal ENINH.
  • the programming phase can be followed by a control phase in quick mode to check whether the memory has been programmed at the desired binary value. This constitutes a characteristic dependent on the invention.
  • the device comprise third means, implemented after the application of the first and second means previously discussed, to check that the division rate corresponds to the number k introduced into memory.
  • these third means comprise a detector sensitive to the return of the voltage to its low level at the end of the period Ti to accelerate, for a predetermined period Tf, the motor to a speed v faster than that used to display the time, and the adjustment of the division rate at a speed v / 2, which thus allows the alternation of intervals between driving pulses with and without adjustment to measure the difference in frequency existing between the frequency of l watch oscillator and standard frequency.
  • the diagram in FIG. 7 schematically explains the phase of operation in fast mode.
  • FAST fast mode signal
  • the motor receives pulses (MOT) at 32 Hz and the signal authorizing the inhibition (ENINH), as well as the inhibition signal which is linked to it ( INH), are emitted at a speed twice as slow, ie 16 Hz.
  • ENINH the inhibition signal which is linked to it
  • INH inhibition signal which is linked to it
  • the circuit inside watch 5 includes a flip-flop D 55 as well as an AND gate 56 arranged as shown in FIG. 2.
  • the signals at 32 and at 16 Hz are taken from the divider by 128 referenced 30.
  • the signal at 32 Hz is sent to the driver circuit 31 and excites the motor at this speed when the FAST signal is present.
  • the signal at 16 Hz is sent to an input of the AND gate 56, a gate which plays exactly the same role as the AND gate 48 for the signal at 60 seconds 60sP.
  • the AND gate 48 is blocked by the inverter 49.
  • the signals ENINH and INH are created at the speed of 16 Hz and at a time fixed by the signals A and B as was the case for the normal execution phase of inhibition.
  • the FAST signal begins when the supply voltage has returned to its low level, at the end of the programming period Ti.
  • the detector 33 emits a signal received by the input CI of the flip-flop 55, the output Q of which passes to the high potential of its input D.
  • the signal FAST is thus present at the output Q of the flip -flop 55 and allows the control phase in rapid mode described above.
  • This control phase will last a period Tf, for example 4 times 1/32 of a second.
  • the period Tf is ended by a reset signal RAZ of the input R of the flip-flop 55. This signal can be taken from the combination of signals present in the divider at 128 referenced 30. As soon as the signal FAST is canceled, the watch circuit operates in normal mode.
  • FIG. 8 shows that the circuit authorizing the control phase in rapid mode can be used to advantage for control purposes only during a revision of the watch for example.
  • the time constant of the monostable 89 of the external circuit 14 is considerably shortened, so that the period Ti has insufficient duration to start the programming phase.
  • the falling edge of the pulse Ti which has previously been brought to a voltage greater than that of the triggering of the voltage detector 33 of the internal circuit 5, immediately starts the control phase in fast mode (FAST).
  • the frequency difference is then measured by the QUIS device of which we have already spoken. If this difference is correct, we will stop there. If this is not the case, a new programming phase is started.
  • a period Ti composed of a rise time of 300lis reaching 4V, followed immediately by a fall time of 3OOgs also, is perfectly suited to the only rapid control process.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Electric Clocks (AREA)
  • Electromechanical Clocks (AREA)
  • Read Only Memory (AREA)

Claims (4)

1. Anordnung für das Programmieren eines elektrisch veränderbaren nicht-flüchtigen Speichers (32) für eine Uhr, welche einen Oszillator (21), einen Frequenzteiler (22 bis 30) mit mehreren Stufen, deren Teilungsverhältnis einzustellen ist durch Ändern einer Anzahl k von Impulsen, die von einer Stufe (23) des Teilers geliefert werden, welche Zahl k repräsentativ ist für die Differenzfrequenz zwischen der Oszillatorfrequenz und einer Eichfrequenz und die in binärer Form in den nicht-flüchtigen Speicher eingeschrieben vorliegt zum in regelmäßigen Intervallen erfolgenden Modifizieren des Inhalts bestimmter festgelegter Stufen (24 bis 29) des Teilers, einen Schrittmotor (M), der Antriebsimpulse, abgegeben von dem Teiler, empfängt zur analogen Zeitanzeige, und eine Aufnahme (4) für das Einsetzen einer Speisespannungsquelle umfaßt, dadurch gekennzeichnet, daß sie erste Mittel umfaßt, gesteuert durch das Ende eines Antriebsimpulses, zum Eingeben eines binären Zustands entsprechend der Zahl k in die festgelegten Stufen des Tellers sowie zweite Mittel umfaßt zum Blockieren des Inhalts der genannten Stufen, sobald der genannte binäre Zustand erreicht worden ist, und nachfolgendes Einschreiben des genannten Inhalts in den nicht-flüchtigen Speicher.
2. Anordnung für das Programmieren nach Anspruch 1, dadurch gekennzeichnet, daß die ersten Mittel außerhalb der Uhr angeordnet sind und mit ihr elektrisch über einen in die Aufnahme für die Spannungsquelle eingefügten Verbinder mittels deren beiden Klemmen verbunden sind, welche ersten Mittel eine Speisequelle für die Speisung der Uhr mit einer Spannung niedrigen Pegels (1,5 V) oder einer Spannung hohen Pegels (6 V), einen Speicher-Abwärtszähler (62 bis 76), in den die Zahl k eingebbar ist, eine Zeitbasis (60), deren Frequenz grob mit der Oszillatorfrequenz der Uhr übereinstimmt, einen Detektor (80) für Antriebsimpulse (Imot, M1, M2), deren Ausgangsflanken (93) koinzident sind mit der Nullrücksetzung der festgelegten Teilerstufen, wobei die Ausgangsflanke eines der Antriebsimpulse den Beginn einer Periode TD definiert, deren Dauer definiert ist durch die Zeit, erforderlich für das Eingeben des Binärzustands entsprechend der Zahl k in dem Speicher-Abwärtszähler (62 bis 67) in die festgelegten Stufen, einen Kommutator (88) für das Umschalten der Speisequelle auf die Spannung hohen Pegels (6 V) am Ende der Periode TD und einen Verzögerungsschaltkreis (89) für das Halten der Spannung auf hohem Pegel während einer vorgegebenen Periode Ti umfassen, und daß die zweiten Mittel in der Uhr enthalten sind und einen Spannungspegeldetektor (33) umfassen, der bei Erreichen eines vorgegebenen Spannungswertes zwischen dem niedrigen und dem hohen Pegel den Inhalt der festgelegten Stufen des Teilers auf dem Binärwert blockiert, den sie am Ende der Periode TD erreicht haben, und während der vorgegebenen Periode Ti den genannten Inhalt in den nicht-flüchtigen Speicher einschreibt.
3. Anordnung zum Programmieren nach Anspruch 1, dadurch gekennzeichnet, daß sie ferner dritte Mittel umaßt, die nach Anwendung der ersten und zweiten Mittel in Betrieb gesetzt werden zum Kontrollieren, ob das Teilungsverhältnis der Zahl k entspricht, die repräsentativ ist für die Differenzfrequenz zwischen der Oszillatorfrequenz und der Eichfrequenz.
4. Anordnung für das Programmieren nach Anspruch 3, dadurch gekennzeichnet, daß die ersten Mittel außerhalb der Uhr angeordnet sind und mit ihr elektrisch über einen in die Aufnahme für die Spannungsquelle eingefügten Verbinder mittels deren beiden Klemmen verbunden sind, welche ersten Mittel eine Speisequelle für die Speisung der Uhr mit einer Spannung niedrigen Pegels (1,5 V) oder einer Spannung hohen Pegels (6 V), einen Speicher-Abwärtszähler (62 bis 76), in den die Zahl k eingebbar ist, eine Zeitbasis (60), deren Frequenz grob mit der Oszillatorfrequenz der Uhr übereistimmt, einen Detektor (80) für Antriebsimpulse (Imot, M1, M2), deren Ausgangsflanken (93) koinzident sind mit der Nullrücksetzung der festgelegten Teilerstufen, wobei die Ausgangsflanke eines der Antriebsimpulse den Beginn einer Periode TD definiert, deren Dauer definiert ist durch die Zeit, erforderlich für das Eingeben des Binärzustands entsprechend der Zahl k in dem Speicher-Abwärtszähler (62 bis 67) in die festgelegten Stufen, einen Kommutator (88) für das Umschalten der Speisequelle auf die Spannung hohen Pegels (6 V) am Ende der Periode TD und einen Verzögerungsschaltkreis (89) für das Halten der Spannung auf hohem Pegel während einer vorgegebenen Periode Ti umfassen, daß die zweiten Mittel in der Uhr enthalten sind und einen Spannungspegeldetektor (33) umfassen, der bei Erreichen eines vorgegebenen Spannungswertes zwischen dem niedrigen und dem hohen Pegel den Inhalt der festgelegten Stufen des Teilers auf dem Binärwert blockiert, den sie am Ende der Periode TD erreicht haben, und während der vorgegebenen Periode Ti den genannten Inhalt in den nicht-flüchtigen Speicher einschreibt, und daß die dritten Mittel einen Detektor (55) umfassen, empfindlich gegenüber der Rückkehr der Spannung auf ihren niedrigen Pegel am Ende der Periode Ti, zum Beschleunigen des Motors, während einer vorgegebenen Periode Tf, auf eine Geschwindigkeit v, die schneller ist als die normalerweise für die Zeitanzeige verwendete, und die Justierung des Teilungsverhältnisses auf eine Geschwindigkeit v/2, womit der Intervallwechsel zwischen Antriebsimpulsen mit und ohne Justierung zugelassen wird für die Messung der Differenzfrequenz zwischen der Frequenz des Oszillators (21) und der Eichfrequenz.
EP87109566A 1986-07-10 1987-07-03 Vorrichtung zum Programmieren einer nichtflüchtigen Speichervorrichtung für ein Uhrwerk Expired EP0253227B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CH277386A CH664868GA3 (de) 1986-07-10 1986-07-10
CH2773/86 1986-07-10

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EP0253227A1 EP0253227A1 (de) 1988-01-20
EP0253227B1 true EP0253227B1 (de) 1989-11-29

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US (1) US4763309A (de)
EP (1) EP0253227B1 (de)
JP (1) JP2519464B2 (de)
CH (1) CH664868GA3 (de)
DE (1) DE3761065D1 (de)
HK (1) HK2295A (de)

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US4763309A (en) 1988-08-09
EP0253227A1 (de) 1988-01-20
JP2519464B2 (ja) 1996-07-31
CH664868GA3 (de) 1988-04-15
DE3761065D1 (de) 1990-01-04
JPS6329291A (ja) 1988-02-06
HK2295A (en) 1995-01-13

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