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EP0161175B1 - Einrichtung zum Modifizieren des Aspektes der Bildpunkte auf einem Bildschirm eines graphischen Anzeigegerätes - Google Patents

Einrichtung zum Modifizieren des Aspektes der Bildpunkte auf einem Bildschirm eines graphischen Anzeigegerätes Download PDF

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Publication number
EP0161175B1
EP0161175B1 EP85400734A EP85400734A EP0161175B1 EP 0161175 B1 EP0161175 B1 EP 0161175B1 EP 85400734 A EP85400734 A EP 85400734A EP 85400734 A EP85400734 A EP 85400734A EP 0161175 B1 EP0161175 B1 EP 0161175B1
Authority
EP
European Patent Office
Prior art keywords
modification
graphic
memory
attribute
processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
EP85400734A
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English (en)
French (fr)
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EP0161175A1 (de
Inventor
Luc Pham Van Cang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thomson Video Equipement
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Thomson Video Equipement
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Filing date
Publication date
Application filed by Thomson Video Equipement filed Critical Thomson Video Equipement
Publication of EP0161175A1 publication Critical patent/EP0161175A1/de
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Publication of EP0161175B1 publication Critical patent/EP0161175B1/de
Expired legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/22—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of characters or indicia using display control signals derived from coded signals representing the characters or indicia, e.g. with a character-code memory
    • G09G5/30—Control of display attribute

Definitions

  • the present invention relates to a device for modifying the appearance of the points of an image on a screen of a graphic image display console, the image being analyzed according to the principle of analysis of television images, and the console being controlled by a graphics processor.
  • the display consoles controlled by a graphics processor include a random access graphics memory interposed between the console screen and the processor which stores the data relating to each point or "pixel of the graphic appearing on the screen.
  • the modification of the graph can be obtained at any time by changing the content of the data relating to each point of the graph stored in the graphic memory, which has the effect of affecting the luminance and / or the color of each point or pixel of the graph which is to be modified.
  • the modification is usually carried out by an operator who introduces on a keyboard linked to the processor the instructions which allow the modification of the data relating to each of the modified points.
  • the action of the operator on the keyboard triggers in the processor a modification cycle, which is executed either by the launching of a particular program or by the activation of wired logical operators.
  • the object of the invention is to overcome the aforementioned drawbacks.
  • the subject of the invention is a device for modifying the appearance of an image on the screen of a console for viewing graphic images analyzed according to the principle of analysis of television images controlled by a graphics processor, of the type comprising, a graphics memory of all the points of the screen interposed between the screen of the display console and the processor, the graphics memory being organized in words of n bits, each bit being representative of the state of a point of the image and having a value 1 or 0 depending on whether the point it represents on the image is visible or is confused with the background of the image and an attribute memory containing the attributes of each point of the image, characterized in that it also comprises a decoder for selecting a bit in each word read in the graphic memory and a modification circuit connected to the decoder, the attribute memory and the processor for modifying each attribute of the corresponding point to the selected bit of a word using modification bits supplied by the processor and memorizing each modified attribute inside the attribute memory, and a reforming circuit coupled to the modification circuit, to the decoder and to the graphic memory to reconstruct the
  • the main advantage of the device according to the invention is that it makes it possible to optimize the duration of the read, modify and write cycles of each point or pixel whose corresponding data are stored in the graphic memory as well as the range of operations that can be performed within this cycle.
  • the device according to the invention has great processing flexibility, practically identical to that which is obtained with systems with purely software processing while allowing faster processing.
  • the device 1 for modifying the appearance of the points of an image written on a screen of a display console according to the invention is represented in FIG. 1 inside a dotted line, coupled between a processor 2 designated by the abbreviation CPU which is the contraction of the English term Central Processing Unit and a display console 3.
  • the device 1 includes a graphic memory 4 which contains a binary matrix representation of all the characteristic points of the graphic image which is displayed on the display console 3, each bit of information contained in the graphic memory 4 having, for example, the value 0 when it corresponds to the uniform background of the graph and the binary value 1 when it corresponds to a point or pixel of the graphic that stands out on the bottom of it.
  • Memory graphic is organized in words of n bits representing the state of n pixels, each word being addressed either by processor 2 or by the display console 3 via a multiplexer circuit of address 5 with two multiplexing inputs , a first multiplexing input being connected by the address line 6 to the address output of processor 2 and a second address input being connected by the address line 7 to the address output of the console display 3.
  • the output of the address multiplexer 5 is connected to the addressing inputs of the graphics memory 4 by means of the address line 8.
  • the data read from the graphics memory 4 at the memory locations designated by the words addresses applied to the address line 8 are applied respectively to the inputs of a parallel-series register 10 and to the inputs of a multiplexer circuit 11.
  • the device 1 also includes an attribute memory 12 possibly formed by p planes additional memories elementary of the graphic memory 4 which contains the attributes coded on p bits respective to each of the n pixels represented in each word of n bits contained in the graphic memory 4, this attribute memory 12 being addressed simultaneously to the graphic memory 4 by the address line 8.
  • the words read in the graphic memory and in the attribute memory 12 are applied to the circuits not shown of the display console 3, via the register 10, to allow the display of the pixels that they represent by the display console.
  • the attribute words PA of each pixel, addressed by each of the address words applied to the address line 8, are applied by a data line 13 to a first input of a modification circuit 14 through the multiplexer 11 and a decoder 19 connected in series.
  • the modification circuit 14 is connected by second and third inputs to the data outputs of processor 2 by means of a data line 15 for the purpose of applying modification data denoted FM and PN to the second and third inputs. of the modification circuit 14, to modify the values of the attributes of the points or pixels PA read in the attribute memory 12 and which are applied to the first input of the modification circuit 14 by the data line 13.
  • the output of the modification 14 is connected by a data line 16 to a data input of a reforming circuit 17 to record each attribute modified PM by the modification circuit 14 at the location which it occupies in the attribute memory 12
  • the reforming circuit 17 is also connected by a second input, by means of line 18, to the output of the decoder 19 addressed by the address line 8 and connected by its input to the output of the multiplexer 11.
  • the decoder 19 address the purpose of the address line 8 is to select, within the word of n bits applied to the input of the multiplexer 11 each bit designated by the address word applied to its input and the attribute word PA coded on p bits which corresponds to it.
  • the bit representative of the selected pixel and its attribute PA are applied respectively to a fourth input and to the first input of the modification circuit 14 with the aim of possibly modifying their values as a function of the modification data which are applied to the second and third input. of the modification circuit 14.
  • the bits not selected by the decoder 19 are applied by the line 18 to the input of the reforming circuit 17 which reforms, as a function of the information modified or not supplied at the output of the modification circuit 14 , a new binary word which is applied to the input of a write demultiplexer circuit 20 by means of a data line 21 to write the possibly modified word and the attributes corresponding to the addresses which they normally occupy in the memory graphic 4 and the attribute memory 12.
  • the modification data of each of the words contained in the graphic memory 4 and the attribute memory 12 are introduced es from a keyboard 22 which is connected to processor 2 via the connection line 23.
  • a mass memory 24 is optionally coupled by a line 25 to processor 2 in order to transfer the processor 2 program instructions necessary for the operation of the assembly.
  • the processor 2 is also connected to a random access memory MMU 26 responsible for memorizing, during operation, the instructions and the data entered from the keyboard 22 or from the mass memory 24.
  • the graphic memory according to the invention is dual access by cycle sharing.
  • a first cycle is reserved for the operation of the display console 3
  • a second cycle is reserved for the operation of the modification process controlled by the processor 2, this modification cycle being characterized by a read cycle, a modification cycle and a cycle to rewrite the modified information in the graphic memory and a third direct reading cycle from the graphic memory, all of these cycles being represented by the time diagram in FIG. 2.
  • the cycles in FIG. 2 are executed by processor 2 which applies control signals to the control bus 27 to refresh the points or pixels of the graph displayed on the screen of the display console and to control the read and write cycles of the graphic memory 4 and the attribute memory 12.
  • the refresh cycle marked “VISU of the display console is represented with a duration T over a period of 2T
  • the cycle of reading L of the information contained in the graphic memory 4 and in the attribute memory 12 is shown interlaced for a duration T apart from the refresh duration of the display console 3 over a period of duration 4T
  • the modification cycle M follows the reading cycle L with the same duration T and the same equal period of duration 4T
  • the writing cycle E follows the modification cycle M with the same duration T during a period equal to 4T and the access cycle direct to memory graphic and in the attribute memory takes place - for a duration T between the instants of refreshment of the display console 3.
  • this mode of sharing of cycles can be advantageously used for the display of words of 16 pixels for a duration of 1184 nanoseconds and the execution of read-modify-write cycles of twice 1184 nanoseconds per pixel or point to be modified which makes it possible to cover high operating ranges, for example, processing of 720 points of image or pixels per scan line on 576 lines - respecting the CCIR standards for 625-line television scanning, the bit rate of the display console in this case corresponding to the digital television standard of 13.5 MHz for 25 images / second and the cycle time T being close to 400 nanoseconds.
  • the 3 attribute bits read in the attribute memory 12 corresponding to the point or to the pixel to be modified are applied to the first input of the modification circuit 14 while the processor 2 simultaneously applies via the data line 15.4 PN modification bits at the same time as 6 function bits corresponding to the FM modification function chosen by the operator allowing the execution of 64 modification functions.
  • the bit of the selected memory word and the corresponding attribute are modified to form a 4-bit PM word which is obtained at the output of the modification circuit 14 which is a function of the value 0 or 1 of the bit of the point or of the pixel to be modified.
  • PN modification data supplied by the processor 2 at the input of the modification circuit 14 and of the modification function also transmitted on the third input of the modification circuit 14 by the processor 2.
  • This transformation is carried out using electrically programmable read-only memories of the type known by the Anglo-Saxon designation "EPROM” or random access memories of the type known by the Anglo-Saxon designation "RAM »Containing tables of functions for modifying the appearance of the points of the graphic image addressed by the processor 2 and by the attribute bits PA of each selected word of the attribute memory, p to fulfill the multiple functions that can be given to the modification circuit, these functions being simple logical functions of the logical AND type, logical OR, OR EXCLUSIVE, or more complicated functions allowing the execution, for example, of linear interpolations between old “pixels” and new “pixels”, conditional operations, linear interpolation operations for the luminance attribute of a pixel as a function of the fractional addressing of the new pixel to resolve in particular the phenomena of aliasing known to graphics processors, or to execute image texture checks in overlay etc ...
  • the invention which has just been described using the embodiment shown in FIG. 1 is not limited to this type of embodiment, it goes without saying that other embodiments are also possible without however depart from the very framework of the invention, in particular it will be understood that the invention also applies as in the example represented in FIG. 3, to the production of more complex devices associating in parallel the device represented in FIG. 1 for versions of the invention requiring rapid processing.
  • the device represented in FIG. 3 is made up of four devices of the type represented in FIG. 1 composed in particular of 4 "4 2 , 4 3 and 4 4 graphic memories respectively and of 4 modification and reforming circuits 29, 30, 31, 32 similar to the example described in FIG.
  • the bus of data 15 acts on the modification and reforming circuits 29, 30, 31, 32 through a multiplexer 28 which directs the modification data on each of the inputs of the circuits placed inside the circuits 29, 30, 31, 32 PN and the FM modification function.
  • This organization allows for example in conditional transfer mode to modify all the pixels of the graphic memory concurrently with the same FM modification function applied to each of the modification and reformation circuits 29, 30, 31, 32 while in graphic mode, for example, in vector trace mode, a single FM modification function corresponding to the single pixel addressed is activated.
  • conditional transfer speed is very significantly increased under these conditions, in practice it is possible with a parallel configuration making it possible to process for example eight pixels in parallel, and to obtain an access time equivalent to 1200ns / 8, ie: 150 nanoseconds per pixel, i.e. a conditional transfer time of the order of 80 milliseconds for an image of 512x512 pixels.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Image Generation (AREA)

Claims (10)

1. Vorrichtung (1) zum Verändern des Aussehens der Punkte eines Bildes auf einem Bildschirm eines Sichtanzeigegeräts (3) für graphische, nach dem Analyseprinzip der Fernsehbilder analysierte Bilder, die von einem graphischen Prozessor (2) des Typs mit einem graphischen Speicher (4) aller Bildschirmpunkte gesteuert wird, welcher zwischen dem Bildschirm des Sichtanzeigegeräts (3) und dem Prozessor (2) eingefügt ist, wobei der graphische Speicher (4) in Wörter zu N-Bits organisiert ist, jedes Bit für den Zustand eines Bildpunktes repräsentativ ist und einen Wert 1 oder 0 aufweist, je nachdem, ob der Punkt, den er auf dem Bildschirm darstellt, sichtbar ist oder im Bildhintergrund verschwindet, sowie mit einem Attributspeicher (12), welcher die Attribute jedes der Bildpunkte beinhaltet, dadurch gekennzeichnet, daß sie ferner einen Decoder (19) zur Selektion eines Bits in jedem in dem graphischen Speicher (4) gelesenen Wort sowie eine Veränderungsschaltung (14) umfaßt, die mit dem Decoder (19), dem Attributspeicher (12) und dem Prozessor (2) verbunden ist, um jedes Attribut des dem selektierten Bit eines Worts entsprechenden Punkts mittels von dem Prozessor (2) gelieferter Veränderungsbits zu verändern, und um jedes veränderte Attribut innerhalb des Attributspeichers (12) zu speichern, sowie eine mit der Veränderungsschaltung (14), dem Decoder (19) und dem graphischen Speicher (4) gekoppelte Neubildungsschaltung (17), um das veränderte Wort wiederherzustellen und es innerhalb des graphischen Speichers zu speichern.
2. Schaltung nach Anspruch 1, dadurch gekennzeichnet, daß die Veränderungsschaltung (14) aus programmierbaren Speichern besteht, die Funktionstabellen zum Verändern des Aussehens der Punkte des graphischen Bildes beinhalten und durch den graphischen Prozessor (2) sowie die Attributbits jedes selektierten Worts des Attributsspeichers (12) adressiert werden.
3. Vorrichtung nach Anspruch 1 oder 2, dadurch gekennzeichnet, daß die Bits zum Verändern und zum Adressieren der Veränderungsfunktionen durch den graphischen Prozessor (2), ausgehend von über eine Tastatur (22) in den Prozessor (2) eingegebenen Befehlen, erzeugt sind.
4. Vorrichtung nach einem der Ansprüche 1 bis 3, dadurch gekennzeichnet, daß der graphische Speicher (4) einerseits durch das Sichtanzeigegerät und andererseits den graphischen Prozessor (2) adressiert wird, mittels eines Adressenmultiplexers, der über den Prozessor gesteuert wird, um die Zyklen des Zugriffs auf den graphischen Speicher zu teilen, die durch das Sichtanzeigegerät (3) und den Prozessor (2) initiiert werden.
5. Vorrichtung nach Anspruch 4, dadurch gekennzeichnet, daß der graphische Speicher (4) in Wörter mit fester Länge organisiert ist.
6. Vorrichtung nach den Ansprüchen 4 und 5, dadurch gekennzeichnet, daß der Zugriffszyklus des Prozessors (2) für den graphischen Speicher (4) aus einem Zyklus zum Auslesen jedes Worts, in welchem sich das Bit eines zu verändernden Bildpunkts befindet, sowie des entsprechenden Attributworts in dem Attributspeicher (12), besteht, aus einem Zyklus zum Verändern des Bits des entsprechenden, zu verändernden Punktes, der innerhalb des gelesenen Worts in dem graphischen Speicher identifiziert wird, auf den ein Zyklus zum Verändern des in dem Attributsspeicher (12) gelesenen Attributworts folgt, auf darf wiederum ein Zyklus zum Neuschreiben des das veränderte Bit enthaltenden Worts irr-den.graphischen Speicher (4) und ein Zyklus zum Neuschreiben des veränderten Attributworts in den Attributspeicher (12) folgen.
7. Vorrichtung nach einem der Ansprüche 2 bis 6, dadurch gekennzeichnet, daß die programmierbaren Speicher der Veränderungsschaltung elektrisch programmierbare Festwertspeicher sind.
8. Vorrichtung nach einem der Ansprüche 2 bis 6, dadurch gekennzeichnet, daß die programmierbaren Arbeitsspeicher der Veränderungsschaltung Arbeitsspeicher sind.
9. Vorrichtung zum Verändern des Aussehens der Funkte eines Bildes auf einem Bildschirm eines Sichtanzeigegeräts (3) für graphische Bilder, die nach dem Analyseprinzip der Fernsehbilder anlaysiert werden, die durch einen graphischen Prozessor (2) gesteuert wird, dadurch gekennzeichnet, daß sie mehrere parallelgekoppelte Vorrichtungen nach einem der Ansprüche 1 bis 8 umfaßt.
10. Vorrichtung nach Anspruch 9, dadurch gekennzeichnet, daß die Koppelung der Vorrichtungen mittels einer Multiplexerschaltung (28) erreicht wird, die das Veränderungsdatum sowie die Veränderungsfunktion zu jedem der Eingänge der Veränderungsschaltungen führt, um die Veränderung aller Punkte des graphischen Bildes mit derselben Veränderungsfunktion zu ermöglichen.
EP85400734A 1984-04-17 1985-04-12 Einrichtung zum Modifizieren des Aspektes der Bildpunkte auf einem Bildschirm eines graphischen Anzeigegerätes Expired EP0161175B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR8406052 1984-04-17
FR8406052A FR2563024B1 (fr) 1984-04-17 1984-04-17 Dispositif pour modifier l'aspect des points d'une image sur un ecran d'une console de visualisation d'images graphiques

Publications (2)

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EP0161175A1 EP0161175A1 (de) 1985-11-13
EP0161175B1 true EP0161175B1 (de) 1988-08-17

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EP85400734A Expired EP0161175B1 (de) 1984-04-17 1985-04-12 Einrichtung zum Modifizieren des Aspektes der Bildpunkte auf einem Bildschirm eines graphischen Anzeigegerätes

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US (1) US4692759A (de)
EP (1) EP0161175B1 (de)
DE (1) DE3564501D1 (de)
FR (1) FR2563024B1 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2520872B2 (ja) * 1985-12-10 1996-07-31 オリンパス光学工業株式会社 画像表示装置
JPS6358395A (ja) * 1986-08-11 1988-03-14 テクトロニックス・インコ−ポレイテッド カラ−表示装置
US4988985A (en) * 1987-01-30 1991-01-29 Schlumberger Technology Corporation Method and apparatus for a self-clearing copy mode in a frame-buffer memory
FR2644960B1 (fr) * 1989-03-21 1991-05-31 Thomson Consumer Electronics Dispositif de detection de fin de connexion a un programme payant recu par un poste d'abonne via un reseau de teledistribution interactive
GB9027678D0 (en) * 1990-12-20 1991-02-13 Ncr Co Videographics display system
TW266277B (en) * 1994-12-31 1995-12-21 Sega Of America Inc Videogame system and methods for enhanced processing and display of graphical character elements
AU2003263769A1 (en) * 2002-07-01 2004-01-19 Xidem, Inc. Electronically controlled electric motor
US7590290B2 (en) * 2004-07-21 2009-09-15 Canon Kabushiki Kaisha Fail safe image processing apparatus

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Publication number Priority date Publication date Assignee Title
US4303986A (en) * 1979-01-09 1981-12-01 Hakan Lans Data processing system and apparatus for color graphics display
JPS57101893A (en) * 1980-12-17 1982-06-24 Hitachi Ltd Liquid crystal display character generation circuit
US4462028A (en) * 1981-02-19 1984-07-24 Honeywell Information Systems Inc. Access control logic for video terminal display memory
US4420770A (en) * 1982-04-05 1983-12-13 Thomson-Csf Broadcast, Inc. Video background generation system
US4504828A (en) * 1982-08-09 1985-03-12 Pitney Bowes Inc. External attribute logic for use in a word processing system

Also Published As

Publication number Publication date
EP0161175A1 (de) 1985-11-13
DE3564501D1 (en) 1988-09-22
FR2563024A1 (fr) 1985-10-18
US4692759A (en) 1987-09-08
FR2563024B1 (fr) 1986-05-30

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