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EP0031375A1 - Apparatus and an improved method for processing of digital information - Google Patents

Apparatus and an improved method for processing of digital information

Info

Publication number
EP0031375A1
EP0031375A1 EP80901520A EP80901520A EP0031375A1 EP 0031375 A1 EP0031375 A1 EP 0031375A1 EP 80901520 A EP80901520 A EP 80901520A EP 80901520 A EP80901520 A EP 80901520A EP 0031375 A1 EP0031375 A1 EP 0031375A1
Authority
EP
European Patent Office
Prior art keywords
data
track
information
synchronization
playback
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP80901520A
Other languages
German (de)
French (fr)
Other versions
EP0031375A4 (en
Inventor
Thomas Greenway Stockham, Jr.
Bruce Coates Rothaar
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SOUNDSTREAM Inc
Original Assignee
SOUNDSTREAM Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SOUNDSTREAM Inc filed Critical SOUNDSTREAM Inc
Publication of EP0031375A1 publication Critical patent/EP0031375A1/en
Publication of EP0031375A4 publication Critical patent/EP0031375A4/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B27/00—Editing; Indexing; Addressing; Timing or synchronising; Monitoring; Measuring tape travel
    • G11B27/10—Indexing; Addressing; Timing or synchronising; Measuring tape travel
    • G11B27/19—Indexing; Addressing; Timing or synchronising; Measuring tape travel by using information detectable on the record carrier
    • G11B27/28—Indexing; Addressing; Timing or synchronising; Measuring tape travel by using information detectable on the record carrier by using information signals recorded by the same method as the main recording
    • G11B27/30—Indexing; Addressing; Timing or synchronising; Measuring tape travel by using information detectable on the record carrier by using information signals recorded by the same method as the main recording on the same track as the main recording
    • G11B27/3027—Indexing; Addressing; Timing or synchronising; Measuring tape travel by using information detectable on the record carrier by using information signals recorded by the same method as the main recording on the same track as the main recording used signal is digitally coded
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
    • G11B20/1803—Error detection or correction; Testing, e.g. of drop-outs by redundancy in data representation

Definitions

  • This invention relates to apparatus and methods for conversion of analog information into digital for- mat and includes error detection/correction techniques and data analysis schemes that provide for recording redundant information to minimize a fatal dropout of information.
  • the present invention involves apparatus for performing digital recording of analog information and is particularly suited to reproduction of audio infor ⁇ mation.
  • digital recording dependent upon the recording medium used, as for example, a magnetic tape, and taking into account the mechanical imperfections in
  • O digital form of course, consists of numerical represen ⁇ tations of increments of a fluctuating analog signal, and lends itself to alteration by simple numeric addi ⁇ tions or substractions.
  • a digital format therefore, simplifies signal filtering, and like operations. How ⁇ ever, the medium on which the ' data is recorded is sub ⁇ ject to defect and even the machinery for performing that recording is not error-free. Therefore, to pro ⁇ consider the highest quality of reproduction where a large number of bits of information are processed each second, it is necessary to be able to identify, for reproduction, the most likely correct information.
  • the present inven ⁇ tion preferably incorporates a full reproduction of primary data on a backup track, and recognizes that such exact reproduction and substitution, where appropriate, of backup for primary data on discovery of an error, is not in itself new.
  • Such is well known in the art and is shown in patents by Dirks, U. S. Patent No. 3,281,804, and Hendrichs et al, U. S. Patent No. 3,665,430. How- ever, the particular error detection tests and correction techniques employed by the present invention to command substitution of backup track data for main track data is not shown in either of these prior patents nor, to the knowledge of the present inventors, has such been known before.
  • the present invention additional thereto and unique within the knowledge of the inventors, also makes an assessment of signal quality for each data group recorded on both the tracks and com ⁇ pares signal qualities such as: track signal amplitude where a drop in amplitude would indicate a tape dropout; proper location of track signal axis crossings where improper crossings could indicate tape dropouts or signal phase anomalies indicative of excessive head wear or misaligned tape playback equilization; and number of axis crossings where insufficient crossings can cause a bit synchronizer to lose count of bit periods. Signal quality is evaluated as an indicator of the possible presence of an error.
  • the present in ⁇ vention adds to the three criterion of the earlier patent application a comparison of signal qualities between main and backup track data groups.
  • a comparison of signal qualities between main and backup track data groups is made.
  • a signal strength evaluation has been shown in an earlier United States Patent by Gabor, No. 3,264,623, such signal monitoring was to provide for switching from one track to the other on signal loss only.
  • the present invention compares signal quality, as described above, with a difference between main and backup track information evaluated as an
  • the present invention provides cir ⁇ cuitry and procedure for looking behind and looking ahead in main and backup track data flows. Thereby, when an error is detected that requires a selection of the other track data, that selection will include a number of data groupings before and after the bad data grouping.
  • the present invention further includes a new synchroniza ⁇ tion code format and a system for more rapidly and ac ⁇ curately locating and locking onto synchronization coding to prevent a premature declaration of synchronization, particularly upon startup.
  • the present inven ⁇ tion provides for synchronizing of data on separate tracks recorded independently and at different times, whereby time differences are averaged to simplify over- dubbing of one track over another, which arrangement is also believed to be unique.
  • Another object of the present invention is to pro ⁇ vide apparatus and a method for looking ahead and look- ing behind in a data flow on each track whereby a de ⁇ tected error will cause the data coming before and after to be deemed to be suspect, commanding a selection on the other track data over that period to improve the accuracy of the error detection/correction processes.
  • Another object of the present invention is to pro ⁇ vide a recording format that includes an alternating synchronization code format that facilitates identifi ⁇ cation thereof from the other content of data groups
  • Still another object of the present invention is to provide circuitry for rapidly acquiring synchroniza- tion, particularly at startup, that includes an arrange ⁇ ment wherein acquired synchronization codes and the spacing therebetween are checked for a number of data groups or words before synchronization is declared.
  • Still another object of the present invention it to provide appropriate circuitry and a scheme for its use for controlling the speed of travel of a tape whereon two tracks of data are recorded, such that data re ⁇ corded on different tracks at different times can be synchronized together for providing a smooth over-dub- bing and synchronized playback of finished analog signals.
  • Principal features of the present invention in an apparatus and method include a recording apparatus where ⁇ in analog signals are converted to a digital form for permanent recording on an appropriate medium, such as a magnetic tape.
  • the present invention pro ⁇ vides for duplication of recorded data by recording for each channel of a multi-channelrecorder the same data on main and backup tracks.
  • the two data flow consist of data words, preferably, of sixteen bits of informa ⁇ tion and a parity bit and three synchronization code bits therewith.
  • the present invention provides error detection circuitry whereby each data word on each track is sub ⁇ jected to four tests for determining which main or back- up track information is most likely correct, with, when main track data is deemed to be correct, it is passed automatically.
  • the four error detection tests of the present invention include: checking for the presence
  • Such signal quality analysis can in ⁇ clude sensing; a track signal amplitude that could in ⁇ dicate a dropout; proper location of track signal axis crossing where an improper crossing could indicate a tape dropout or signal phase anomalies indicative of excessive head wear or misaligned tape playback equali ⁇ zation; number of axis crossings where insufficient crossings can cause a bit synchronizer to lose count of bit periods; or the like.
  • the playback thereby "locking up" improperly out of synchronization.
  • the present invention pre ⁇ ferably, alternates each sync code in each data word, as say from 110 in a first data group or word to 001 in a following data group or word, and so on. So arranged, the playback would pickup a first sync code found, look over a proper number of bits thereafter in a following data group and then look for an alternated sync code, and so on. Alternating sync coding minimizes a pos ⁇ sibility that a signal in a data group or word could be sensed as sync code.
  • the present invention provides circuitry for looking ahead and 'looking behind or back in the data flow on each track.
  • looking ahead involves an intro ⁇ duction of a delay into the data flow whereby the four error detection tests are performed on each data word prior to that data word arriving at a point in the circuitry where a decision to playback main or select backup track data needs to be made.
  • an error de ⁇ termination results in identifying a number of data words ahead of and a certain number of data words be- hind the error in the flow as being suspect.
  • data words will be picked up for playback from the backup track before and after the error. So arranged, error trends occurring on one track, are anticipated and provided for by this look-ahead/look-behind feature of the pre ⁇ sent invention.
  • OMPI spacing between data words as soon as possible during playback provides synchronization engine circuitry.
  • This circuitry can be described as operating in essen ⁇ tially four states and is particularly useful at start- up, to locate synchronization codes and spacing there ⁇ between in the data flows.
  • the synchroni ⁇ zation engine looks in a data flow at startup for any sync code and, when such sync code is found, counts ahead to where the next sync code should be. If a proper sync code is found thereat again the circuitry counts ahead to where the next sync code should be, con ⁇ tinuing looking in the data flow until a certain number (n) of properly located sync codes are discovered whereat synchronization is declared and normal playback is ordered.
  • the present invention also in ⁇ cludes an arrangement for averaging tape speeds between tracks such that information recorded on one track, can be synchronized with information on another and over- dubbed thereover.
  • the circuitry arrangement to perform this data matching provides for averaging of tape speed whereby first-in-first-out buffer circuit for each audio channel is maintained at a certain desired level of fullness as compared or averaged with other channel buffer circuits so as to compensate for the effects of wow and flutter across the tracks.
  • FIGURE 1 is a block schematic of a single channel of a multi-channel digital tape recorder, that should be understood to receive data, in the form of an analog signal, to process and convert that signal to digital form and to record in duplicate, that information on two tracks, the Figure showing inputs, and circuitry associ ⁇ ated with the data conversion, recording, error detection/ correction and playback and further shows, in schematic, circuitry to perform look-behind and look-ahead schemes of the present invention;
  • FIGURE 2(a) shows a schematic of a flow of main track data ' words 1 through 16, with data word 6 identi ⁇ fied as containing a bad parity indicator that results in generation of a command to thereafter select data on a backup track which command is shown therein to con- tinue for a number of following data words illustrating a look-behind scheme of the present invention;
  • FIGURE 2(b) shows a schematic of the flow of main track data words of FIGURE 2(a), showing the same error indication in block 6, which block 6 error is shown sensed before block 6 arrives at a point in the flow where a selection decision is required, resulting in a command to select backup track data for a number of data words prior to the error indication, illustrating a look-ahead scheme of the present invention
  • FIGURE 2(c) shows a combination of the flows of FIGURES 2(a) and 2(b);
  • FIGURE 3(a) a schematic representation of a signal train of data words arranged between conventional synchronization codes
  • FIGURE 3(b) a schematic like that of FIGURE 3(a) only showing what appears to be a synchronization code within a data word;
  • FIGURE 3(c) a schematic like that of FIGURE 3(a) and 3(b) only showing alternating synchronization codes arranged between each data word;
  • FIGURE 4 a block schematic function flow of syn ⁇ chronization engine circuitry of the present invention.
  • FIGURE 5 a block schematic of first-in-first-out buffer memory circuits of a four channel unit that are connected so as to pass, when filled appropriately, signals that control tape speed whereby tracks recorded at different tapes can be synchronized in over-dubbing operations.
  • FIGURE 1 is shown a block schematic that illus ⁇ trates a signal flow through a single channel 10 that should be understood to be one channel of a multiple channel digital tape recorder of the present invention.
  • the single channel 10 shown in FIGURE 1 is representa ⁇ tive of each channel of such multi-channel digital tape recorder, which digital tape recorder is preferably arranged to involve a non-return to zero (NZR) re ⁇ cording.
  • NZR non-return to zero
  • FIGURE 1 the blocks shown and identified therein should be understood to be indicative of standard electrical circuits and, as appropriate, are essentially like the circuits shown and described in the application for United States Patent entitled “Apparatus and Method for Providing Error Recognition and Correction of Recorded Digital Information", assigned serial number 946,067, cited earlier herein.
  • the present invention includes a combination of circuitry and that together, function uniquely as will be described, and so specific electrical components within a block of circuitry, their connections, and individual operations, except where appropriate, will not be shown in detail herein.
  • an audio input is shown passed into an amplifier 11.
  • the amplifier 11 conventionally increases the strength of the received signal and passes it to a low pass filter 12 wherein frequencies above so called Niquist Frequency are filtered out.
  • Such signal fil ⁇ tration is to prevent aliasing in the sample and hold and analog to digital conversion circuitry to follow.
  • A/D converter 14 under the control of the clocking pulses, the analog signal is converted to digital form, preferably incre ⁇ ments of the analog signal are represented as 16-bit data words, and each data word is fed, at intervals, simultaneously into a bit stream generator 15 and into a parity generator 16.
  • the bit stream generator 15 re ⁇ arranges the parallel data words into a serial con ⁇ figuration- and synchronization or sync codes and in- eludes therewith.
  • a parity bit is included therein by parity generator 16 and the bit stream generator 15 dup ⁇ licates each data word for simultaneous recording on main and backup tracks.
  • the data words with parity and sync codes therein from the bit stream generator travel, as shown, through lines 17a and 17b to a conven ⁇ tional mechanism, not shown, that records the serial information, as main and backup track flows, onto a permanent media.
  • the permanent media as shown in FIGURE 1 as broken lines boxes, is preferably magnetic tape 18.
  • the main and backup track data flows are recorded on magnetic tape 18 along side one another and spaced apart such that a data loss on one track, as with a tape defect-, or the like, will not neces- sarily extend to the other track.
  • a loss of data, error, or the like, occurring on the main track will cause or trigger a switching of the playback to the backup track and, of course, if a problem occurs with the backup track, the main track data will continue to be passed for playback. So arranged, a loss on one track only will not result in an unrecoverable loss of information.
  • serial information is taken off from magnetic tape 18 by bit synchronizers A and B, 19a and 19b, whereat the signal quality of each main and backup track data flow is checked, as indicated by meters 22a and 22b, and that information passed through lines 23 for evaluation, as will be explained later herein, in error detection and correction circuitry 24.
  • Meters 22a and 22b should be understood to be symbolic of apparatus for performing signal quality evaluation and should not be understood to limit such signal evalua- tion to tests performed by a meter only. Rather, signal quality evaluation can.
  • track signal amplitude where a drop in amplitude could indicate a tape dropout
  • proper location of track signal axis crossings where improper crossings could indicate tape dropouts or signal phase anomalies in ⁇ dicative of excessive recorder head wear, not shown, or misaligned tape playback equalization
  • number of signal axis crossings where, it is assumed, insufficient crossings can cause a bit synchronizer to lose count of bit periods and the like.
  • the main and backup track information A and B is passed to serial to parallel converters 20a and 20b and sync finder circuitry 21a and 21b that are also connected together.
  • the serial to parallel converters 20a and 20b reconvert the data to parallel arrangement for passage to a holding register 26a and 26b and simultaneously, to the sync finder 21a and 21b.
  • the sync finder 21a and 21b looks for the presence of proper synchronization codes between data words and information about the presence or absence of the proper synchronization codes is passed to error detection and correction circuitry 24.
  • Sync finder circuitry 21a and 21b in the present invention prefer ⁇ ably includes synchronization engine circuitry 40, shown in FIGURE 4.
  • the synchroniza ⁇ tion engine 40 utilizes the sync finder to rapidly lo ⁇ cate what appears to be a valid synchronization or sync code and will count from that sync code, a certain number of bits, as say the 20 bits per word of the pre ⁇ sent invention, and will then look for another' proper sync code. This process is repeated until either a set number (n) of properly located sync codes are found or a sum of the proper sync codes less erroneous sync codes found equals zero whereupon "sync code found" is declared and the sync finder 21a and 21b is directed to again search to locate a proper sync code.
  • the present invention preferably employs an arrangement for alternating sync coding between each data word for more accurately obtain ⁇ ing synchronization. It should be understood that the alternating sync coding is first recorded on the mag ⁇ netic code 18 and is picked up by bit synchronizers 17a and 17b and scanned up by sync finders 21a and 21b.
  • a comparison of the data on the main and backup tracks or A and B tracks is made at data compare circuitry 29, with information about that comparison passed through line 30 to the error de ⁇ tection and correction circuitry 24.
  • the present invention tests a data word coming off magnetic tape 18 with four separate error detection tests that Include: a signal quality evaluation of each data word on each track, as illustrated by meters 22a and 22b; for proper location of proper syn ⁇ chronization codes between data words by sync finders 21a and 21b; for the presence of proper parity code bits in each data word on both tracks by parity circuitry 27a and 27b; and for a meter between data words on the main and backup tracks by data comparison circuitry 29.
  • a bad parity or synchronization code error or a data word mismatch constitutes an error that will cause, if the problem is on the main track, a switching to the backup track.
  • a signal quality difference or fluctuation, how ⁇ ever, is not treated as an error requiring track switch ⁇ ing. Rather, a signal quality difference is treated as indicative of the possibility of an error, and used as a "tie-breaker" in determining, from the other enumerated error detection procedures, which track information is most likely correct. For example, when a mismatch is discovered and the parity and synchronization codes are proper, a signal quality difference will be used to determine which track data is most likely correct.
  • the results of the error detection checks are evaluated by the error detection correction circuitry 24. That cir- cuitry makes a decision as to which data word on main and backup tracks is to be selected as most likely cor-, rect for further passage, which decision is passed to date selector circuitry 33, as shown by line 32.
  • main and backup track informa- tion is passed through digital delay circuits 31a and 31b prior to the data reaching the data select circuit 33.
  • digital delay circuits a delay is created between when a selection determination is made and when the particular data word actually reaches the data selector circuitry 33. Therefore, as shown best in
  • FIGURE 2(b) by creating a delay between when a problem is sensed on one track, a data selector can be made in anticipation of an error before the particular question ⁇ able data word actually needs to be acted upon.
  • FIGURE 2(b) shows an illustration of how an error sensed as a parity error in a main track data word causes or triggers selection of, as shown in the lowerline thereof, a number of backup track data words immediately preceding that bad data word.
  • Such early selection of backup track data over main track data assumes, and it has been found in practice, that errors occur in series. Therefore, such early selection anticipates the occurrence of other errors and is to minimize a chance for distortion, to provide for a best possible data reproduction by switch- ing from one track to the other in anticipation of a problem.
  • the data selector circuitry pre ⁇ ferably, on receipt of an error indication line 32 orders that a data selection decision be held in over a number of following data words to further minimize distortion where, it can be assumed, the track data is just re ⁇ covering from the problem that caused the error and could be prone to further error.
  • FIGURES 2(a) and 2(b) A combination of FIGURES 2(a) and 2(b) is shown in FIGURE 2(c) wherein the digital delay circuitry 31a and 31b and data selec ⁇ tor circuitry 33 provide both a holding in of an error and selection of backup track data words before and after an error occurs, providing "look behind" and "look ahead” functions to insure a most faithful data reproduction possible. Utilizing this approach, track data, before a dropout and after one has occurred, is not used. The data selected therefore has a greater likelihood of being correct than was heretofore pos ⁇ sible.
  • the selected data word flow passes to a holding register 34 that also receives commands or signals through line 35 from the error detection/cor ⁇ rection circuit 24.
  • a holding register 34 that also receives commands or signals through line 35 from the error detection/cor ⁇ rection circuit 24.
  • the signal is passed to a FIFO, or first-in-first-out, buffer memory 36 that is connected, not shown, to the tape drive for controlling speed thereof.
  • the FIFO buffer memory 36 controls the tape speed to maintain a certain percentage fullness. That fullness is compared with buffer memory fullness of the other channels, not shown, for synchronizing recording of information recorded on the tape so that it may be played back in sunchronization.
  • the preferred arrangement of the buffer memory 35 in con ⁇ junction with other buffer memories for providing tape speed control will be discussed in detail later with respect to FIGURE 5.
  • FIGURE 3(a) shows a conventional or common digital sync coding arrangement as consisting of a 110 followed by a data word containing also a parity bit. Shown in FIGURE 3(b), the data word itself is shown as also containing a 110 that could erron ⁇ eously be picked up as sync code during startup or re- covery from a dropout that would cause a restart of sync locator circuitry and a data loss.
  • FIGURE 3(c) shows a preferred sync code arrangement where sync codes are alternated, one after another. So arranged, starting with 110 as the sync code, the following sync code would be 001. In FIGURE 3(c), the same false sync signal shown in FIGURE 3(b) is repeated, but would not be picked up as a sync code because of the alternating code arrangement of the present invention. Of course, so arranged, the sync finder 21a and 21b will be pro- grammed to pickup the alternating bits as proper sync codes.
  • the sync finders 21a and 21b look for the presence of proper synchronization codes between data words.
  • the present invention preferably also includes within the sync finder circuitry, circuitry identified hereinafter as sync engine 40.
  • FIGURE 4 shows a schematic wherein is detailed the function of that sync engine 40, which circuitry should be understood to consist of arrangements of electronic components that are not in themselves unique, but are unique in combina ⁇ tion for performing the functions detailed hereinafter with respect to FIGURE 4.
  • Sync engine 40 operates in essentially four states, analyzing each data word from the bit synchronizer and, as illustrated in block 41, looks for any synchronization code therein.
  • sych synchronization code can be alter- nated as say between 110 and 001 and so the sync engine would preferably provide for searching for alternating sync codes.
  • a locating of a sync code as illustrated at 42 causes a transition to block 43. However, if a sync code is not found, a transition is made back to block 41 to restart looking for any sync code. This may be the result of engine 40 locating a false sync code within the data bits upon startup.
  • the finding of a next sync code causes a transition, via block 44, to block 46 wherein the presence or absence of sync codes are counted by a counter 47.
  • the condition of block 49 is invoked, de ⁇ claring sync code found and the . beginning of playback. If a single bad sync code is encountered, the counting state, the condition of block 41, is invoked, via 51, commanding a restart of the looking for any sync code. So arranged, if a number of bad sync codes are encountered where the sum of the good and bad sync codes equal zero, then the sync engine 40 reverts to looking for any sync code mode, its first state of operation, as illustrated by block 41. If (n) good sync codes are discovered, the fourth state is invoked where normal playback is initiated as illustrated by block 49.
  • FIGURE 4 illustrates the four states of operation of the sync engine 40, which sync engine is preferably incorporated within the sync finder 21a and 21b circuitry that has been discussed with respect to FIGURE 1. While the described arrangement and function ⁇ ing of sync engine 40 is preferred it should be obvious that sync finder circuitry could be employed alone and, particularly with the preferred alternating sync format of the present invention, would constitute a satisfactory sync location system. Sync engine 40 therefore provides an improved arrangement for accurately identifying syn ⁇ chronization coding to obtain as faithful a playback of recorded information as possible.
  • a preferred multi-channel digital tape recorder of the present invention includes a first-in-first-out buffer memory 35 for each channel.
  • FIGURE 5 is shown, in schematic, a 4-channel digital tape recorder that includes with each channel first-in-first-out buf- fer memories 25a, 35b, 35c, and 35d.
  • the FIFO buffer memories 35a through 35d should be taken as being identi ⁇ cal to one another, each individually performing the functions described earlier herein for buffer memory 35. Further, it should be understood that the blocks immedi- ately preceding the FIFO buffer memories 35a through 35d represent the logic for each main and backup track for each channel of a four-channel recorder.
  • Each FIFO buffer memory 35a through 35d is shown in FIGURE 5
  • meters 56a, 56b, 56c, and 56d connected through lines 55a through 55d, respectively, to what appear to be meters 56a, 56b, 56c, and 56d.
  • Meters 56a through 56d illustrate that FIFO buffer memory fullness preferably registers or is measured as a digital number.
  • Each FIFO buffer memory is preferably maintained approximately half full and, at that desired half-full level, arrows 57a, 57b, 57c, and 57d of meters 56a through 56d would be at the same mid-point.
  • the present inven ⁇ tion provides for an averaging of the fullness levels of the buffer memories, illustrated by arrows 57a through 57d, when a channel has data and is not recording, in ⁇ creasing or decreasing tape speed to provide an average half-full level.
  • a uniform tape speed is ob ⁇ tained such that playback of the tracks of the different channels can be synchronized, as say for the over-dubbing of one track over another, or like operations.
  • averaging the digital number from each meter 56a through 56d is passed to appropriate logic circuitry identified as 58a, 58b, 58c, and 58d that are essentially gates that also receive, along with the buffer memory fullness values, signals representing channel recording status and whether the channel is re ⁇ cording.
  • the channel status signals are shown by arrows 60a through 60d that indicate if a particular channel has data thereon. Whether or not the channel is re ⁇ cording is represented by lines 61a through 61d.
  • the dates 58a through 58d will pass the fullness values of the buffer memory 35a through 35d to an averager as digital numbers. If the channel is recording, the gate will not pass that digital num ⁇ ber.
  • the averager 62 provides thereby an average digital number that represents buffer memory fullness for those channels not in a record mode that have data thereon, which average digital number is then converted to a corresponding voltage in a DAC circuit 63.
  • That voltage from the DAC circuit 63 is then passed to a variable frequency oscillator labeled VCO 64 that con ⁇ trols tape speed and passes an appropriate signal through a switch 65 and through a line 66 to a tape speed control drive box 67 to appropriately control tape speed. Should all channels be in a record mode, then no signal is, of course, passed to the averager 62 which condition would cause switch 65 to move to a position where a median tape speed is commanded by an external oscillator 68.
  • tape speed is controlled by an average buffer memory fullness of tracks with data thereon that are not in a record mode, preventing buffer memories in a record mode from being considered in the averaging.
  • new material being recorded on an active channel will not affect the speed of that re- cording. Rather, the speed of recording of that new material is controlled by data already recorded on another channel.
  • a synchronizing or bringing into synchronization of data already recorded with material being recorded is accomplished. So arranged, materials recorded at different times can therefore be brought into synchronization for over-dubbing opera ⁇ tions, or the like.
  • the present invention consists of combinations of circuitry for performing the error detection/correction functions enumerated herein. While the preferred re ⁇ cording format of the present invention involves the inclusion of a parity bit in each data word, which parity bit is then checked in the error detection
  • the present inven ⁇ tion includes a synchronization code format for facilitating and insuring that proper sync code will be identified as early in the playback mode as pos ⁇ sible to reduce information loss, which synchronization code format can be used with synchronization engine cir ⁇ cuitry that operates in four states to facilitate ac ⁇ curate acquisition of synchronization.
  • the present invention provides circuitry for averaging buffer memory fullness for a plurality of channels to consider only those channels not recording with data thereon whereby existing data controls the recording speed of new material providing for a smooth over-dub- bing of information being recorded with information recorded earlier.
  • a four-channel recorder has been shown to be preferred, it should be under ⁇ stood not to be limited- to recorders of any particular numbers of channels. While preferred embodiments of our invention and methods have been shown and described herein, it should be obvious that this disclosure is made by way of example and variations are possible without departing from subject matter coming within the scope of the following claims, which claims we regard as out inven ⁇ tion.

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  • Signal Processing For Digital Recording And Reproducing (AREA)

Abstract

Appareil et methode de traitement d'informations numeriques comprenant la duplication des informations provenant de chaque canal d'un enregistreur a multi canaux sur des pistes principale et de reserve et formant une combinaison d'appareils et de procedes de detection d'erreurs ou des groupements ou des mots de donnees sur chaque piste sont soumis individuellement a quatre tests separes pour detecter les erreurs et selectionnant, a partir de cette analyse, les donnees les plus susceptibles d'etre correctes en vue d'un traitement ulterieur. De plus, une plus grande fiabilite du systeme est obtenue en prevoyant un circuit par lequel une erreur detectee active une selection de groupements de donnees venant avant et apres l'erreur detectee, assurant le cas echeant, la commutation de donnees de la piste principale a la piste de reserve sur un certain nombre de groupements de donnees. Il est egalement prevu un format de codage de synchronisation unique avec un reseau de circuit et un procede pour son utilisation permettant d'effectuer rapidement un codage de synchronisation dans un flot de donnees, ainsi qu'un dispositif de calcul de la moyenne du contenu des tampons-premiers arrives, premiers traites-de chaque piste, pour commander la vitesse de la bande pour permettre un doublage regulier d'informations enregistrees a des moments differents sur des pistes separees.Apparatus and method for processing digital information comprising duplicating information from each channel of a multi-channel recorder on main and reserve tracks and forming a combination of apparatus and methods for detecting errors or groupings where data words on each track are individually subjected to four separate tests to detect errors and select, from this analysis, the data most likely to be correct for further processing. In addition, greater reliability of the system is obtained by providing a circuit by which a detected error activates a selection of groups of data coming before and after the detected error, ensuring, if necessary, the switching of data from the main track to the reserve track on a certain number of data groupings. There is also provided a single synchronization coding format with a circuit network and a method for its use allowing rapid synchronization coding in a data stream, as well as a device for calculating the average of the content of the buffers-first arrivals, first milks-of each track, to control the speed of the tape to allow regular doubling of information recorded at different times on separate tracks.

Description

APPARATUS AND AN IMPROVED METHOD FOR PROCESSING OF DIGITAL INFORMATION
BRIEF DESCRIPTION OF THE INVENTION
Field of the Invention
This invention relates to apparatus and methods for conversion of analog information into digital for- mat and includes error detection/correction techniques and data analysis schemes that provide for recording redundant information to minimize a fatal dropout of information.
Background of the Invention
The present invention involves apparatus for performing digital recording of analog information and is particularly suited to reproduction of audio infor¬ mation. In such digital recording, dependent upon the recording medium used, as for example, a magnetic tape, and taking into account the mechanical imperfections in
OMPI WIPO recording apparatus, it is often the case that informa¬ tion can be lost in the recording and retrieval process. Such information loss has, in the past, generally re¬ quired an averaging between good data or a picking up and reproducing of last good data, or the like, to fill a gap or space left when a loss occurs.
That some information will be lost is a statistical probability that increases with equipment age, magnetic tape wear, and like factors, and so must be planned for to achieve a most faithful reproduction possible. As will be outlined hereinafter, a number of techniques and schemes have been proposed and implemented for re¬ ducing information losses. An apparatus and a method for providing a faithful information reproduction was disclosed in an earlier United States Patent Application entitled, "Apparatus and Method For Providing Error Recognition and Correction of Recorded Digital Informa¬ tion", invented by one of the present inventors, filed September 27, 1978, and assigned serial number 946,067. The present invention preferably includes certain of the circuitry and error detection/correction techniques disclosed in that earlier application for United States Patent, but expands therefrom to provide a more accurate and faithful data reproduction than was heretofore achieved.
Prior Art
As detailed in the above-cited earlier United States Patent Application entitled, "Apparatus and Method for Providing Error Regognition and Correction of Recorded Information", there are numerous advantages to repro¬ ducing audio information into a digital form. Such
O digital form, of course, consists of numerical represen¬ tations of increments of a fluctuating analog signal, and lends itself to alteration by simple numeric addi¬ tions or substractions. A digital format therefore, simplifies signal filtering, and like operations. How¬ ever, the medium on which the 'data is recorded is sub¬ ject to defect and even the machinery for performing that recording is not error-free. Therefore, to pro¬ duce the highest quality of reproduction where a large number of bits of information are processed each second, it is necessary to be able to identify, for reproduction, the most likely correct information. The present inven¬ tion preferably incorporates a full reproduction of primary data on a backup track, and recognizes that such exact reproduction and substitution, where appropriate, of backup for primary data on discovery of an error, is not in itself new. Such is well known in the art and is shown in patents by Dirks, U. S. Patent No. 3,281,804, and Hendrichs et al, U. S. Patent No. 3,665,430. How- ever, the particular error detection tests and correction techniques employed by the present invention to command substitution of backup track data for main track data is not shown in either of these prior patents nor, to the knowledge of the present inventors, has such been known before.
Within the redundant recording scheme of the pre¬ sent invention, it is necessary to provide for an accur¬ ate determination of which information to select as being correct or most likely correct for further processing. The aforesaid United States Application for Patent pro¬ vides three independent information checking techniques for application to each data group or data word. Speci¬ fically, this prior patent application involves checking, in each data group for sync coding and parity, and in¬ cludes checking for an information match between main and backup track data groups. The present invention additional thereto and unique within the knowledge of the inventors, also makes an assessment of signal quality for each data group recorded on both the tracks and com¬ pares signal qualities such as: track signal amplitude where a drop in amplitude would indicate a tape dropout; proper location of track signal axis crossings where improper crossings could indicate tape dropouts or signal phase anomalies indicative of excessive head wear or misaligned tape playback equilization; and number of axis crossings where insufficient crossings can cause a bit synchronizer to lose count of bit periods. Signal quality is evaluated as an indicator of the possible presence of an error. In practice, it has been found that where there is a signal quality fluctuation on a track the probability is increased that the data on that track, proximate to that signal fluctuation, will be suspect or unreliable. Therefore, the present in¬ vention adds to the three criterion of the earlier patent application a comparison of signal qualities between main and backup track data groups. Of course, once an error is detected, then a determination of the most likely correct data is made and a substitution of backup track for main track information is made. While a signal strength evaluation has been shown in an earlier United States Patent by Gabor, No. 3,264,623, such signal monitoring was to provide for switching from one track to the other on signal loss only. The present invention, unlike this earlier patent, compares signal quality, as described above, with a difference between main and backup track information evaluated as an
O element in the error detection process and does not re¬ quire a complete signal loss to declare that informa¬ tion suspect.
Prior art devices known to the present inventors, including the present inventor's aforementioned appli¬ cation for United States Patent, have all involved look¬ ing at information only as it passes a certain point or location whereat a decision has to be made to select main or backup information or integrate between data. This, of course, means that each data grouping on each main and backup track for each channel is evaluated separately to determine which is most likely correct information for further processing. Since no error detection process can guarantee perfect detection of bad data, to further improve the accuracy of the error detection process of the present invention, it is use¬ ful, when bad data is detected to declare the data coming before and thereafter as being suspect and to therefore utilize the other track data. Specifically, and unique from the prior art within the knowledge of the present inventors, the present invention provides cir¬ cuitry and procedure for looking behind and looking ahead in main and backup track data flows. Thereby, when an error is detected that requires a selection of the other track data, that selection will include a number of data groupings before and after the bad data grouping.
Additional to the error detection/correction schemes and look-behind and look-ahead scheme outlined herein- above and unique within the knowledge of the inventors, the present invention further includes a new synchroniza¬ tion code format and a system for more rapidly and ac¬ curately locating and locking onto synchronization coding to prevent a premature declaration of synchronization, particularly upon startup. Further, the present inven¬ tion provides for synchronizing of data on separate tracks recorded independently and at different times, whereby time differences are averaged to simplify over- dubbing of one track over another, which arrangement is also believed to be unique.
Within the knowledge of the inventors, there has not heretofore existed apparatus and a method like that of the present invention to include the particular error detection system and techniques for selection of data for further processing, synchronization format and ar¬ rangement for acquistion of synchronization codes and track synchronization techniques, which apparatus and methods are believed to be new and unique and a signifi¬ cant improvement in the art.
It is a principal object of the present invention to provide an improved method for error detection of digital data recorded on main and backup tracks, and to provide criterion for selection of the most likely cor¬ rect information on main or backup tracks for further processing.
Another object of the present invention is to pro¬ vide apparatus and a method for looking ahead and look- ing behind in a data flow on each track whereby a de¬ tected error will cause the data coming before and after to be deemed to be suspect, commanding a selection on the other track data over that period to improve the accuracy of the error detection/correction processes. Another object of the present invention is to pro¬ vide a recording format that includes an alternating synchronization code format that facilitates identifi¬ cation thereof from the other content of data groups
O or words for preventing a premature declaration or synchronization.
Still another object of the present invention is to provide circuitry for rapidly acquiring synchroniza- tion, particularly at startup, that includes an arrange¬ ment wherein acquired synchronization codes and the spacing therebetween are checked for a number of data groups or words before synchronization is declared.
Still another object of the present invention it to provide appropriate circuitry and a scheme for its use for controlling the speed of travel of a tape whereon two tracks of data are recorded, such that data re¬ corded on different tracks at different times can be synchronized together for providing a smooth over-dub- bing and synchronized playback of finished analog signals.
Principal features of the present invention in an apparatus and method include a recording apparatus where¬ in analog signals are converted to a digital form for permanent recording on an appropriate medium, such as a magnetic tape. Preferably, the present invention pro¬ vides for duplication of recorded data by recording for each channel of a multi-channelrecorder the same data on main and backup tracks. The two data flow consist of data words, preferably, of sixteen bits of informa¬ tion and a parity bit and three synchronization code bits therewith. The present invention provides error detection circuitry whereby each data word on each track is sub¬ jected to four tests for determining which main or back- up track information is most likely correct, with, when main track data is deemed to be correct, it is passed automatically. The four error detection tests of the present invention include: checking for the presence
_ OMPI_ of proper parity and synchronization codes in each data word; determining if a match exists between the main and backup track data words; and checking for a varia¬ tion in signal quality between main and backup track data word flows. Such signal quality analysis can in¬ clude sensing; a track signal amplitude that could in¬ dicate a dropout; proper location of track signal axis crossing where an improper crossing could indicate a tape dropout or signal phase anomalies indicative of excessive head wear or misaligned tape playback equali¬ zation; number of axis crossings where insufficient crossings can cause a bit synchronizer to lose count of bit periods; or the like. While such signal quality veriation or fluctuation will not necessarily indicate the presence of an error, it has been found in practice that such fluctuations often accompany a problem with recorded data. Therefore, for example, if the signal strength is found to be weak on the main track, and problems exist with parity, sync coding, or there is a data mis-match between the main and backup track infor¬ mation, then the backup track information, would be selected for reproduction, and vice versa. The system of the present invention preferably provides that a signal quality variation or fluctuation without the presence of another error or errors will be ignored. Therefore, a signal quality variation or fluctuation is used as a "tie-breaker", to further add to the accuracy of the error detection capabilities of the present in¬ vention. In practice it has been found, particularly where a constant audio signal is introduced, that the signal it¬ self may periodically reproduce the synchronization coding. Such false code could then be picked up as a
OMΓ synchronization code or sync code, the playback thereby "locking up" improperly out of synchronization. To avoid this potential difficulty, the present invention, pre¬ ferably, alternates each sync code in each data word, as say from 110 in a first data group or word to 001 in a following data group or word, and so on. So arranged, the playback would pickup a first sync code found, look over a proper number of bits thereafter in a following data group and then look for an alternated sync code, and so on. Alternating sync coding minimizes a pos¬ sibility that a signal in a data group or word could be sensed as sync code.
As an additional error minimizing procedure, the present invention provides circuitry for looking ahead and 'looking behind or back in the data flow on each track. Specifically, looking ahead involves an intro¬ duction of a delay into the data flow whereby the four error detection tests are performed on each data word prior to that data word arriving at a point in the circuitry where a decision to playback main or select backup track data needs to be made. From the results of the four tests outlined hereinabove, an error de¬ termination results in identifying a number of data words ahead of and a certain number of data words be- hind the error in the flow as being suspect. There¬ fore, where the error is in the main track, data words will be picked up for playback from the backup track before and after the error. So arranged, error trends occurring on one track, are anticipated and provided for by this look-ahead/look-behind feature of the pre¬ sent invention.
Additional to the described alternating synchroniza¬ tion coding, the present invention, to lock into proper
OMPI spacing between data words as soon as possible during playback, provides synchronization engine circuitry. This circuitry can be described as operating in essen¬ tially four states and is particularly useful at start- up, to locate synchronization codes and spacing there¬ between in the data flows. In operation, the synchroni¬ zation engine looks in a data flow at startup for any sync code and, when such sync code is found, counts ahead to where the next sync code should be. If a proper sync code is found thereat again the circuitry counts ahead to where the next sync code should be, con¬ tinuing looking in the data flow until a certain number (n) of properly located sync codes are discovered whereat synchronization is declared and normal playback is ordered. However, if sync codes are not located where they should be In the data flow, then such failures are substracted from successes until either (n) successes are found or a total of successes less failures reaches zero whereat the circuitry returns to the first state of looking for any sync code. This circuitry and its functioning provides for a more positive location of synchronization within the shortest period of time pos¬ sible so as to prevent declaring synchronization pre¬ maturely and creating thereby unwanted noise. Additional to the detection techniques, synchroniza¬ tion code format, and synchronization engine circuitry, outlined hereinabove, the present invention also in¬ cludes an arrangement for averaging tape speeds between tracks such that information recorded on one track, can be synchronized with information on another and over- dubbed thereover. The circuitry arrangement to perform this data matching provides for averaging of tape speed whereby first-in-first-out buffer circuit for each audio channel is maintained at a certain desired level of fullness as compared or averaged with other channel buffer circuits so as to compensate for the effects of wow and flutter across the tracks. Other features, objects and steps in practicing the present invention will become more apparent from the following detailed description, taken together with the accompanying drawings.
THE DRAWINGS
FIGURE 1, is a block schematic of a single channel of a multi-channel digital tape recorder, that should be understood to receive data, in the form of an analog signal, to process and convert that signal to digital form and to record in duplicate, that information on two tracks, the Figure showing inputs, and circuitry associ¬ ated with the data conversion, recording, error detection/ correction and playback and further shows, in schematic, circuitry to perform look-behind and look-ahead schemes of the present invention; FIGURE 2(a), shows a schematic of a flow of main track data' words 1 through 16, with data word 6 identi¬ fied as containing a bad parity indicator that results in generation of a command to thereafter select data on a backup track which command is shown therein to con- tinue for a number of following data words illustrating a look-behind scheme of the present invention;
FIGURE 2(b), shows a schematic of the flow of main track data words of FIGURE 2(a), showing the same error indication in block 6, which block 6 error is shown sensed before block 6 arrives at a point in the flow where a selection decision is required, resulting in a command to select backup track data for a number of data words prior to the error indication, illustrating a look-ahead scheme of the present invention;
FIGURE 2(c), shows a combination of the flows of FIGURES 2(a) and 2(b);
FIGURE 3(a), a schematic representation of a signal train of data words arranged between conventional synchronization codes;
FIGURE 3(b), a schematic like that of FIGURE 3(a) only showing what appears to be a synchronization code within a data word;
FIGURE 3(c), a schematic like that of FIGURE 3(a) and 3(b) only showing alternating synchronization codes arranged between each data word; FIGURE 4, a block schematic function flow of syn¬ chronization engine circuitry of the present invention; and
FIGURE 5, a block schematic of first-in-first-out buffer memory circuits of a four channel unit that are connected so as to pass, when filled appropriately, signals that control tape speed whereby tracks recorded at different tapes can be synchronized in over-dubbing operations.
DETAILED DESCRIPTION
Referring now to the drawings:
In FIGURE 1, is shown a block schematic that illus¬ trates a signal flow through a single channel 10 that should be understood to be one channel of a multiple channel digital tape recorder of the present invention. The single channel 10 shown in FIGURE 1 is representa¬ tive of each channel of such multi-channel digital tape recorder, which digital tape recorder is preferably arranged to involve a non-return to zero (NZR) re¬ cording.
In the schematic of FIGURE 1 the blocks shown and identified therein should be understood to be indicative of standard electrical circuits and, as appropriate, are essentially like the circuits shown and described in the application for United States Patent entitled "Apparatus and Method for Providing Error Recognition and Correction of Recorded Digital Information", assigned serial number 946,067, cited earlier herein.
The present invention includes a combination of circuitry and that together, function uniquely as will be described, and so specific electrical components within a block of circuitry, their connections, and individual operations, except where appropriate, will not be shown in detail herein.
In the single channel 10 schematic of FIGURE 1, reading from left to right therein, an audio input is shown passed into an amplifier 11. It should however be understood that any analog signal input would be appro¬ priate for processing within and by the present inven¬ tion. For purposes of this disclosure the signal input will be assumed to be an audio signal as from a musical performance. The amplifier 11 conventionally increases the strength of the received signal and passes it to a low pass filter 12 wherein frequencies above so called Niquist Frequency are filtered out. Such signal fil¬ tration is to prevent aliasing in the sample and hold and analog to digital conversion circuitry to follow.
From the low pass filter 12 the signal passes to a sample and hold circuitry 13 wherein is contained a
- \JR£ ^ OM?I_ WIPO clock, not shown, that is part of a record control to provide clocking pulses that are imposed upon the in¬ put signals and function as timing pulses to control the operation of an analog to digital converter cir- cuit that is shown in FIGURE 1 and hereinafter re¬ ferred to as an A/D converter 14. In A/D converter 14, under the control of the clocking pulses, the analog signal is converted to digital form, preferably incre¬ ments of the analog signal are represented as 16-bit data words, and each data word is fed, at intervals, simultaneously into a bit stream generator 15 and into a parity generator 16. The bit stream generator 15 re¬ arranges the parallel data words into a serial con¬ figuration- and synchronization or sync codes and in- eludes therewith. A parity bit is included therein by parity generator 16 and the bit stream generator 15 dup¬ licates each data word for simultaneous recording on main and backup tracks. The data words with parity and sync codes therein from the bit stream generator travel, as shown, through lines 17a and 17b to a conven¬ tional mechanism, not shown, that records the serial information, as main and backup track flows, onto a permanent media. The permanent media, as shown in FIGURE 1 as broken lines boxes, is preferably magnetic tape 18.
So arranged, the main and backup track data flows are recorded on magnetic tape 18 along side one another and spaced apart such that a data loss on one track, as with a tape defect-, or the like, will not neces- sarily extend to the other track. As will be more fully discussed later herein, a loss of data, error, or the like, occurring on the main track will cause or trigger a switching of the playback to the backup track and, of course, if a problem occurs with the backup track, the main track data will continue to be passed for playback. So arranged, a loss on one track only will not result in an unrecoverable loss of information. Shown in FIGURE 1, serial information is taken off from magnetic tape 18 by bit synchronizers A and B, 19a and 19b, whereat the signal quality of each main and backup track data flow is checked, as indicated by meters 22a and 22b, and that information passed through lines 23 for evaluation, as will be explained later herein, in error detection and correction circuitry 24. Meters 22a and 22b should be understood to be symbolic of apparatus for performing signal quality evaluation and should not be understood to limit such signal evalua- tion to tests performed by a meter only. Rather, signal quality evaluation can. include, but is not limited to: track signal amplitude where a drop in amplitude could indicate a tape dropout; proper location of track signal axis crossings where improper crossings could indicate tape dropouts or signal phase anomalies in¬ dicative of excessive recorder head wear, not shown, or misaligned tape playback equalization; and for number of signal axis crossings where, it is assumed, insufficient crossings can cause a bit synchronizer to lose count of bit periods and the like.
From the bit sync 19a and 19b, the main and backup track information A and B is passed to serial to parallel converters 20a and 20b and sync finder circuitry 21a and 21b that are also connected together. The serial to parallel converters 20a and 20b, reconvert the data to parallel arrangement for passage to a holding register 26a and 26b and simultaneously, to the sync finder 21a and 21b. The sync finder 21a and 21b looks for the presence of proper synchronization codes between data words and information about the presence or absence of the proper synchronization codes is passed to error detection and correction circuitry 24. Sync finder circuitry 21a and 21b in the present invention prefer¬ ably includes synchronization engine circuitry 40, shown in FIGURE 4. At system startup, the synchroniza¬ tion engine 40 utilizes the sync finder to rapidly lo¬ cate what appears to be a valid synchronization or sync code and will count from that sync code, a certain number of bits, as say the 20 bits per word of the pre¬ sent invention, and will then look for another' proper sync code. This process is repeated until either a set number (n) of properly located sync codes are found or a sum of the proper sync codes less erroneous sync codes found equals zero whereupon "sync code found" is declared and the sync finder 21a and 21b is directed to again search to locate a proper sync code.
Further, as part of a preferred data format of the present invention, as will be discussed later herein with respect to FIGURE 3(a) through 3(c), the present invention preferably employs an arrangement for alternating sync coding between each data word for more accurately obtain¬ ing synchronization. It should be understood that the alternating sync coding is first recorded on the mag¬ netic code 18 and is picked up by bit synchronizers 17a and 17b and scanned up by sync finders 21a and 21b.
Sync finders 21a and 21b are also connected to main and backup track holding registers A and B, shown at 26a and 26b, that synchronize the two flows for passage to digital delay circuits 31a and 31b. Also, the data flows from holding registers 26a and 26b, prior to their reaching the digital delay circuit, are each evaluated by parity check circuitry 27a and 27b, wherein a check is made of the parity bit in each data word, and data compare circuitry 29. Information concerning the presence or absence of a proper parity bit in each data word is passed from parity check circuitry 27a and 27b through lines 28 to error detection and correction cir¬ cuitry 24. Also, prior to the signals reaching digital delay circuitry 31a and 31b, a comparison of the data on the main and backup tracks or A and B tracks, is made at data compare circuitry 29, with information about that comparison passed through line 30 to the error de¬ tection and correction circuitry 24.
As detailed above, the present invention tests a data word coming off magnetic tape 18 with four separate error detection tests that Include: a signal quality evaluation of each data word on each track, as illustrated by meters 22a and 22b; for proper location of proper syn¬ chronization codes between data words by sync finders 21a and 21b; for the presence of proper parity code bits in each data word on both tracks by parity circuitry 27a and 27b; and for a meter between data words on the main and backup tracks by data comparison circuitry 29. A bad parity or synchronization code error or a data word mismatch constitutes an error that will cause, if the problem is on the main track, a switching to the backup track. A signal quality difference or fluctuation, how¬ ever, is not treated as an error requiring track switch¬ ing. Rather, a signal quality difference is treated as indicative of the possibility of an error, and used as a "tie-breaker" in determining, from the other enumerated error detection procedures, which track information is most likely correct. For example, when a mismatch is discovered and the parity and synchronization codes are proper, a signal quality difference will be used to determine which track data is most likely correct. The results of the error detection checks are evaluated by the error detection correction circuitry 24. That cir- cuitry makes a decision as to which data word on main and backup tracks is to be selected as most likely cor-, rect for further passage, which decision is passed to date selector circuitry 33, as shown by line 32.
Shown in FIGURE 1, main and backup track informa- tion is passed through digital delay circuits 31a and 31b prior to the data reaching the data select circuit 33. in which digital delay circuits a delay is created between when a selection determination is made and when the particular data word actually reaches the data selector circuitry 33. Therefore, as shown best in
FIGURE 2(b), by creating a delay between when a problem is sensed on one track, a data selector can be made in anticipation of an error before the particular question¬ able data word actually needs to be acted upon. FIGURE 2(b) shows an illustration of how an error sensed as a parity error in a main track data word causes or triggers selection of, as shown in the lowerline thereof, a number of backup track data words immediately preceding that bad data word. Such early selection of backup track data over main track data assumes, and it has been found in practice, that errors occur in series. Therefore, such early selection anticipates the occurrence of other errors and is to minimize a chance for distortion, to provide for a best possible data reproduction by switch- ing from one track to the other in anticipation of a problem. Further, as errors tend to occur in bursts, as shown in FIGURE 2(a), the data selector circuitry, pre¬ ferably, on receipt of an error indication line 32 orders that a data selection decision be held in over a number of following data words to further minimize distortion where, it can be assumed, the track data is just re¬ covering from the problem that caused the error and could be prone to further error. A combination of FIGURES 2(a) and 2(b) is shown in FIGURE 2(c) wherein the digital delay circuitry 31a and 31b and data selec¬ tor circuitry 33 provide both a holding in of an error and selection of backup track data words before and after an error occurs, providing "look behind" and "look ahead" functions to insure a most faithful data reproduction possible. Utilizing this approach, track data, before a dropout and after one has occurred, is not used. The data selected therefore has a greater likelihood of being correct than was heretofore pos¬ sible.
Shown in FIGURE 1, from the data selector cir¬ cuitry 33, the selected data word flow passes to a holding register 34 that also receives commands or signals through line 35 from the error detection/cor¬ rection circuit 24. When and if the holding register 34 is informed by the error detection/correction cir- cuite 24 that a fatal dropout has occurred on both main and backup tracks, and therefore neither main or backup track data is usable, it will hold and pass the last good data word until notified that correct data is available.
From the holding register 34, the signal is passed to a FIFO, or first-in-first-out, buffer memory 36 that is connected, not shown, to the tape drive for controlling speed thereof. So arranged, as will be explained in detail later herein, the FIFO buffer memory 36 controls the tape speed to maintain a certain percentage fullness. That fullness is compared with buffer memory fullness of the other channels, not shown, for synchronizing recording of information recorded on the tape so that it may be played back in sunchronization. The preferred arrangement of the buffer memory 35 in con¬ junction with other buffer memories for providing tape speed control will be discussed in detail later with respect to FIGURE 5.
As was mentioned earlier herein, the present inven- tion, with respect to FIGURES 3(a) through 3(c) also in¬ cludes, as a preferred data recording format, alternating synchronization or sync codes to facilitate location and pickup thereof to minimize a potential for an erroneous sync identification. FIGURE 3(a) shows a conventional or common digital sync coding arrangement as consisting of a 110 followed by a data word containing also a parity bit. Shown in FIGURE 3(b), the data word itself is shown as also containing a 110 that could erron¬ eously be picked up as sync code during startup or re- covery from a dropout that would cause a restart of sync locator circuitry and a data loss. FIGURE 3(c) shows a preferred sync code arrangement where sync codes are alternated, one after another. So arranged, starting with 110 as the sync code, the following sync code would be 001. In FIGURE 3(c), the same false sync signal shown in FIGURE 3(b) is repeated, but would not be picked up as a sync code because of the alternating code arrangement of the present invention. Of course, so arranged, the sync finder 21a and 21b will be pro- grammed to pickup the alternating bits as proper sync codes.
As detailed earlier herein with respect to FIGURE 1, the sync finders 21a and 21b look for the presence of proper synchronization codes between data words. The present invention, as shown best in FIGURE 4, preferably also includes within the sync finder circuitry, circuitry identified hereinafter as sync engine 40. FIGURE 4 shows a schematic wherein is detailed the function of that sync engine 40, which circuitry should be understood to consist of arrangements of electronic components that are not in themselves unique, but are unique in combina¬ tion for performing the functions detailed hereinafter with respect to FIGURE 4. Sync engine 40 operates in essentially four states, analyzing each data word from the bit synchronizer and, as illustrated in block 41, looks for any synchronization code therein. As detailed earlier herein, sych synchronization code can be alter- nated as say between 110 and 001 and so the sync engine would preferably provide for searching for alternating sync codes. A locating of a sync code as illustrated at 42 causes a transition to block 43. However, if a sync code is not found, a transition is made back to block 41 to restart looking for any sync code. This may be the result of engine 40 locating a false sync code within the data bits upon startup. The finding of a next sync code causes a transition, via block 44, to block 46 wherein the presence or absence of sync codes are counted by a counter 47. When a number (n) is received, the condition of block 49 is invoked, de¬ claring sync code found and the .beginning of playback. If a single bad sync code is encountered, the counting state, the condition of block 41, is invoked, via 51, commanding a restart of the looking for any sync code. So arranged, if a number of bad sync codes are encountered where the sum of the good and bad sync codes equal zero, then the sync engine 40 reverts to looking for any sync code mode, its first state of operation, as illustrated by block 41. If (n) good sync codes are discovered, the fourth state is invoked where normal playback is initiated as illustrated by block 49.
The schematic of FIGURE 4 illustrates the four states of operation of the sync engine 40, which sync engine is preferably incorporated within the sync finder 21a and 21b circuitry that has been discussed with respect to FIGURE 1. While the described arrangement and function¬ ing of sync engine 40 is preferred it should be obvious that sync finder circuitry could be employed alone and, particularly with the preferred alternating sync format of the present invention, would constitute a satisfactory sync location system. Sync engine 40 therefore provides an improved arrangement for accurately identifying syn¬ chronization coding to obtain as faithful a playback of recorded information as possible.
As discussed earlier herein with respect to FIGURE 1, a preferred multi-channel digital tape recorder of the present invention includes a first-in-first-out buffer memory 35 for each channel. In FIGURE 5 is shown, in schematic, a 4-channel digital tape recorder that includes with each channel first-in-first-out buf- fer memories 25a, 35b, 35c, and 35d. The FIFO buffer memories 35a through 35d should be taken as being identi¬ cal to one another, each individually performing the functions described earlier herein for buffer memory 35. Further, it should be understood that the blocks immedi- ately preceding the FIFO buffer memories 35a through 35d represent the logic for each main and backup track for each channel of a four-channel recorder. Each FIFO buffer memory 35a through 35d is shown in FIGURE 5
_G, connected through lines 55a through 55d, respectively, to what appear to be meters 56a, 56b, 56c, and 56d. Meters 56a through 56d illustrate that FIFO buffer memory fullness preferably registers or is measured as a digital number. Each FIFO buffer memory is preferably maintained approximately half full and, at that desired half-full level, arrows 57a, 57b, 57c, and 57d of meters 56a through 56d would be at the same mid-point. The present inven¬ tion provides for an averaging of the fullness levels of the buffer memories, illustrated by arrows 57a through 57d, when a channel has data and is not recording, in¬ creasing or decreasing tape speed to provide an average half-full level. Thereby, a uniform tape speed is ob¬ tained such that playback of the tracks of the different channels can be synchronized, as say for the over-dubbing of one track over another, or like operations. To pro¬ vide such fullness averaging the digital number from each meter 56a through 56d is passed to appropriate logic circuitry identified as 58a, 58b, 58c, and 58d that are essentially gates that also receive, along with the buffer memory fullness values, signals representing channel recording status and whether the channel is re¬ cording. The channel status signals are shown by arrows 60a through 60d that indicate if a particular channel has data thereon. Whether or not the channel is re¬ cording is represented by lines 61a through 61d. Assuming the presence of data and that the channel is not in a record mode, the dates 58a through 58d will pass the fullness values of the buffer memory 35a through 35d to an averager as digital numbers. If the channel is recording, the gate will not pass that digital num¬ ber. The averager 62 provides thereby an average digital number that represents buffer memory fullness for those channels not in a record mode that have data thereon, which average digital number is then converted to a corresponding voltage in a DAC circuit 63. That voltage from the DAC circuit 63 is then passed to a variable frequency oscillator labeled VCO 64 that con¬ trols tape speed and passes an appropriate signal through a switch 65 and through a line 66 to a tape speed control drive box 67 to appropriately control tape speed. Should all channels be in a record mode, then no signal is, of course, passed to the averager 62 which condition would cause switch 65 to move to a position where a median tape speed is commanded by an external oscillator 68.
As per the above, tape speed is controlled by an average buffer memory fullness of tracks with data thereon that are not in a record mode, preventing buffer memories in a record mode from being considered in the averaging. Thereby, new material being recorded on an active channel will not affect the speed of that re- cording. Rather, the speed of recording of that new material is controlled by data already recorded on another channel. Thereby, a synchronizing or bringing into synchronization of data already recorded with material being recorded is accomplished. So arranged, materials recorded at different times can therefore be brought into synchronization for over-dubbing opera¬ tions, or the like.
The present invention consists of combinations of circuitry for performing the error detection/correction functions enumerated herein. While the preferred re¬ cording format of the present invention involves the inclusion of a parity bit in each data word, which parity bit is then checked in the error detection
OM process, it should be obvious that such parity bit inclusion could be dispensed with within the scope of this disclosure. Obviously, if such parity bit is not included, the error detection arrangement would not look for it, the present invention then including checking for synchronization coding, data match, and for signal quality, only. Further, the present inven¬ tion includes a synchronization code format for facilitating and insuring that proper sync code will be identified as early in the playback mode as pos¬ sible to reduce information loss, which synchronization code format can be used with synchronization engine cir¬ cuitry that operates in four states to facilitate ac¬ curate acquisition of synchronization. Further, the present invention provides circuitry for averaging buffer memory fullness for a plurality of channels to consider only those channels not recording with data thereon whereby existing data controls the recording speed of new material providing for a smooth over-dub- bing of information being recorded with information recorded earlier. Also while a four-channel recorder has been shown to be preferred, it should be under¬ stood not to be limited- to recorders of any particular numbers of channels. While preferred embodiments of our invention and methods have been shown and described herein, it should be obvious that this disclosure is made by way of example and variations are possible without departing from subject matter coming within the scope of the following claims, which claims we regard as out inven¬ tion.

Claims

We Claim:
1. Apparatus for processing of digital informa¬ tion comprising a recorder wherein analog information is converted to digital form and recorded on a permanent media onmain and backup tracks, said backup track con¬ taining a duplication of the main track information that consists of data words that each contain synchroni¬ zation codes, said recorder including circuitry for picking up information off said permanent media for playback; means for retrieving said main and back¬ up track flows; means for measuring and comparing the signal quality of each data word in main and backup track flows; means for locating proper synchronization codes in said data words in said main and backup track flows; means for comparing said data words in said main and backup track flows against one another; means for receiving and evaluating infor¬ mation from: said means for locating synchronization codes; means for comparing data words; and means for measuring and comparing signal quality, so as to select most likely correct data words from said main and back¬ up tracks for playback; and playback means for converting selected digital information back to analog form for playback.
2. Apparatus for processing digital information as recited in Claim 1, wherein each data word includes a parity bit therein, and further including means for identifying proper parity codes in data words in each main and backup track flow; and the means for receiving and evaluating information is connected to receive information from said means for identifying proper parity codes and use that information in determining most likely correct information.
3. Apparatus for processing digital information as recited in Claim 1, further including, delay means arranged in the main and backup tracks for providing a delay to the data flows whereby a selection of most likely correct information and, as necessary, a track switching can be made by the means for receiving and evaluating information in anti- cupation of a sensed error.
4. Apparatus for processing digital information as recited in Claim 3, wherein the means for receiving and evaluating information provides for holding a sensed error for a number of data words in the flow after a data word is identified as being in error.
5. Apparatus for processing digital information as recited in Claim1, further including
_ Q.-:PI -2S-
a holding register means for holding and duplicating for playback a last good data word where the means for receiving and evaluating information is unable to identify a following most likely correct data word for those on the main and backup tracks.
6. Apparatus for processing digital information as recited in Claim 1, further including a first-in-first-out buffer memory means arranged to receive the flow of most likely correct data words for providing a constant output therefrom for playback; and means for controlling tape speed so as to maintain a desired first-in-first-out buffer memory fullness.
7. Apparatus for processing digital information as recited in Claim 6, further including a first-in-first-out buffer memory means for each channel of a multi-channel recorder; means for measuring said buffer memory means fullness; means for averaging said buffer memory means fullness connected to said means for measuring said buffer memory means fullness and to the means for controlling tape speed; and means fullness to those channels with data thereon and not recording.
8. Apparatus for processing digital information as recited in Claim 7, further including switch means whereby, when all channels are recording, the means for controlling tape speed will be operated at a medium speed.
9. Apparatus for processing digital information as recited in Claim 7, wherein the averaged buffer memory means fullness is reflected as a voltage passed to an oscillator means for controlling tape speed.
10. Apparatus for processing digital information as recited in Claim 1, wherein the recorder provides for recording of alternating synchronization codes; and the means for locating proper synchroniza¬ tion codes in said data words is programmed to looking for and act on said alternating synchronization codes .
11. Apparatus for processing digital information as recited in Claim 1, further including, with the means for locating proper synchronization codes, sync engine means for accurately ac¬ quiring proper synchronization for playback of a digital data flow at startup, by looking for any synchronization code, and upon finding a synchroniza- tion code counting to where a next synchronization code should be, and reflecting the presence and absence of proper synchronization codes respectively, as plusses
c-:? ~ and minuses, combining said plusses and minuses together and, when a sum thereof equals a desired number, declaring synchronization and when a sum there- equals zero, declaring synchronization not found and the process of looking for any synchronization code restarted.
12. Apparatus for providing uniform tape speed control for a multi-channel digital tape recorder com¬ prising, logic circuitry for each channel for conversion of an analog signal to digital form and re¬ cording that digital data on a tape media and includes tape speed control circuitry and circuitry for re¬ trieving that recorded data to pass most likely correct if information for playback; first-in-first-out buffer memort means connected to receive the information flow passed from said digital .tape recorder; means for measuring the fullness of said buffer memory means and passing that information to gate means; gate means connected to receive the measure ent of said fullness of said buffer memory means of each channel and to receive channel status information as to the conditions that data is present and that information is not being recorded, to pass said fullness measure¬ ment when both said channel status conditions are pre- sent; averaging means connected to receive said measurements of said buffer memory means fullness from said gate means for providing an average buffer memory means fullness; and oscillator means connected to receive said averaged buffer memory means fullness whose output frequency reflects said averaged buffer memory means fullness and is connected to control operation of said tape speed control circuitry.
13. Apparatus for providing uniform tape speed control as recited in Claim 12, further including switch means arranged with said oscil¬ lator means whereby if no indicator of buffer memory means fullness is present, said switch means will pass a voltage to operate the tape speed control circuitry at a medium speed.
14. Apparatus for arrangement in a digital tape recorder for accurately acquiring proper synchronization for playback of a digital data flow as startup including, means for identifying synchronization cedes in data words in a digital data flow; means for locking an identified synchroni¬ zation code; locator means arranged for counting a cer¬ tain number of bits from said identified synchroniza¬ tion code to look for a following synchronization code; counter means arranged for counting the numbers of properly located synchronization codes and failures to locate synchronization codes, which counter means will subtract the failures to locate from the properly located synchronization codes; and declaration means arranged to receive from said counter means for number of properly located syn- chronization codes less the failures to locate for, when a certain number of properly located synchronization codes are located, declaring synchronization and ini¬ tiating recorder playback and, when the number of properly located synchronization codes less the failures to locate reaches zero, declaring synchronization not found and reactivating the means for identifying any synchronization code.
15. A method for providing improved error detection and correction of digital information recorded on a re- cording media as a flow of data words duplicated on main and backup tracks that include synchronization code bits with each data word of each track, for identifying erroneous data words on each track, including the steps of, checking and comparing the signal quality of each data word on said main track with the complement data word on said backup track; checking for the presence of a proper syn¬ chronization code in each data word on each track; checking for a match between complementary data words on main and backup tracks; and analyzing the results of the checks to de¬ termine most likely correct data for passage for playback.
16. A method for providing improved error detection and correction of digital information as recited in Claim
15, wherein analyzing the results of the check's includes, identifying a data word that fails a check for proper synchronization code as being in error;
_ O.MPI identifying the existence of an error when main and backup tracks data words fail to match; and comparing a difference in signal quality between main and backup track data words with said other erroneous data word indicators to select a most likely correct data word.
17. A method for providing improved error detection and correction of digital information as recited in Claim 15, in data words containing parity bits further including, checking for the presence of a proper parity bit in each data word on each track; and evaluating the results of that parity check with the other checks to determine most likely correct data for playback.
18. A method for providing improved error detection and correction of digital information as recited in Claim 17, wherein analyzing the results of the four checks includes, identifying a data word that fails a check for proper parity code as being in error; identifying a data word that fails a check for proper synchronization code as being in error; identifying the existence of an error when main and backup tracks data words fail to match; and comparing a difference in signal quality between main and backup track data words with said other erroneous data word indicators to select a most likely correct data word.
19 A method for providing improved error detection and correction of digital information as recited in Claim 15, further including alternating synchronization code bits between each data word.
20. A method for providing improved error detection and correction of digital information as recited in Claim 15, further including, providing a delay between the determination of the presence of an erroneous data word and a selection of which data word on the main and backup tracks to pass for playback; and identifying a number of data words coming before the erroneous data word as being in error causing a selection of other track data words for passage for playback.
21. A method for providing improved error detection and correction of digital information as recited in Claim
15, further including providing a delay between the determination of the presence of an erroneous data word and a selection of which data word on the main and backup tracks to pass for playback; and identifying a number of data words follow- ing the erroneous data words as being in error to cause a selection of other track data words for passage for playback.
22. A method for providing an improved synchroniza¬ tion coding of digital information recorded on a re¬ cording media as data words for separating data words including the step of, alternating synchronization code bits between each data word.
23. A method for accurately acquiring synchroniza¬ tion of digital data words coming off a permanent media during playback including the steps of, looking for any synchronization code; counting ahead a certain number of bits in the data word and looking for a proper synchronization code; continuing counting ahead the certain number of bits in each data word and looking for proper synchronization codes; subtracting failures to locate proper synchronization codes from located proper synchroniza¬ tion codes; upon locating (n) proper synchronization codes, declaring synchronization and beginning playback; and where properly located synchronization codes less failures to locate proper synchronization codes equal zero, declaring synchronization not found and looking again in the data flow for any synchroniza¬ tion code.
24. In a multi-channel digital recorder that in¬ cludes memory for each track of each channel a method for synchronizing playback of information recorded on dif¬ ferent tracks on a tape media including the steps of, measuring memory fullness of each track; averaging memory fullness of tracks not recorded to provide and average fullness measurement; and utilize that average fullness measurement to control tape speed.
25. A method as recited in Claim 24, further in¬ cluding converting the memory fullness of each track to a voltage thereby providing a single voltage as the average of memory fullness measurement; and controlling that controls tape speed,
26. A method as recited in Claim 24, further in- eluding, moving the tape at a medium speed when all tracks are recording.
OMP
EP19800901520 1979-07-06 1981-01-26 Apparatus and an improved method for processing of digital information. Withdrawn EP0031375A4 (en)

Applications Claiming Priority (2)

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US06/055,689 US4328580A (en) 1979-07-06 1979-07-06 Apparatus and an improved method for processing of digital information
US55689 1979-07-06

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EP0031375A1 true EP0031375A1 (en) 1981-07-08
EP0031375A4 EP0031375A4 (en) 1981-09-21

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US (1) US4328580A (en)
EP (1) EP0031375A4 (en)
JP (1) JPS56500826A (en)
GB (3) GB2065342B (en)
NL (1) NL8020284A (en)
WO (1) WO1981000160A1 (en)

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Also Published As

Publication number Publication date
NL8020284A (en) 1981-06-16
GB8301342D0 (en) 1983-02-16
JPS56500826A (en) 1981-06-18
EP0031375A4 (en) 1981-09-21
US4328580A (en) 1982-05-04
GB2065342B (en) 1984-02-08
GB8301341D0 (en) 1983-02-16
GB2065342A (en) 1981-06-24
WO1981000160A1 (en) 1981-01-22

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