JPS62248173A - Digital signal recording and reproducing device - Google Patents

Abstract

PURPOSE:To accurately judge the reliability of a reproduced data at the time of high-speed reproduction by detecting that errors are not occurring in the two blocks whose block addresses are consecutive in the reproduced data. CONSTITUTION:A signal reproduced by a rotary head is inputted from an input terminal 10 and supplied to a synchronizing detection circuit 11 and a data demodulation circuit 12. The output of the circuits 11 and 12 pass through a timing detection circuit 13, a parity check circuit 14, a latch circuit 15, gates 17, 18, 19, a counter 20; whether or not two blocks having no error are couse cutive is detected in a detection circuit 21, and further whether or not the address signals of the said two blocks are consecutive is detected in a counter 22, gates 23, 24, and 25, and a resulting detection signal is outputted from a flag terminal 29. The block thus checked of its errors is judged to have a high reliability.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital signal recording and reproducing device such as a rotary head type digital audio tape recorder.
In particular, the present invention relates to a device suitable for high-speed search and the like.

[Conventional technology]

A rotary head digital audio tape recorder (hereinafter referred to as R-DAT) is one of the devices that uses a rotary head to record and reproduce PCM audio signals. An independent subcode area is provided in the trunk for recording not only the PCM audio signal but also additional information for time display and finding the beginning of a song.

Figure 3 shows the block configuration of R-DAT signals. One block consists of a synchronization signal (SYNC), an identification code (ID),
Block address signal (ADH).

Parity (PR) added to ID and ADR
, and data (DATA), where the DATA part is a PCM audio signal and its error correction code in the PCM signal area, and a signal such as time information in the subcode area. Further, a signal for locating the beginning of a song is recorded in the ID, so that a simple search can be performed by reproducing only the ID.

[Problem that the invention seeks to solve]

In such a situation, a simple high-speed search based on the track start signal is not possible, but a complex search based on ID code, time unit, etc. (for example, 8
(e.g., retrieval from minute seconds to C minutes and d seconds) can be realized using the information contained in DATA, but in any case, it is necessary to read the signal correctly when the tape is running at high speed.

Therefore, in general, the relative speed between the drum provided with the rotary head and the tape is not controlled to be kept constant, but No. 3 is read. In Figure 4, which shows the trajectory of F and C with respect to the trunk at this time, 1
is the tape, 2 is the track, 3 is the normal tape running direction, 4
5 is the head scanning direction, 5 is the head trajectory during high-speed tape rewinding, and 6 is the head trajectory during high-speed tape forwarding.

As shown in this figure, during high-speed searches, signals are read while the head scans across multiple tracks, which increases the error rate in the reproduced data and lowers the reliability of the data. Parity is provided to detect whether there are errors in the ID code or ADR, but if there are many errors as described above, errors may be overlooked, making it difficult to perform high-speed searches or display time, etc. There are many inconveniences.

This invention was made to solve the above-mentioned problems. Even when the data reading condition is poor, such as during high-speed search, highly reliable data can be obtained, and it is possible to obtain good high-speed data. It is an object of the present invention to provide a digital signal recording and reproducing device that can perform searches.

[Means for solving problems]

The digital signal recording and reproducing apparatus according to the first invention of the present application includes a detection means for detecting that no error is detected in a plurality of consecutive blocks of reproduced data, and a reliability of the reproduced information signal according to the detection result. A means for making judgments is provided.

In addition to the above-mentioned first invention, the digital signal recording/reproducing device according to the second invention of the present application checks whether consecutive reproduced data blocks are indeed continuous within a track, that is, the continuity of block addresses. Provide a judgment means to judge,
The reliability of data is determined according to the detection results and determination results.

[Effect]

In this invention, it is confirmed that no error is detected in consecutive blocks of reproduced data, or at the same time, it is confirmed that the blocks are indeed continuous within a track, and these judgment results are used. Determine the reliability of data based on

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a schematic configuration of a digital signal recording and reproducing apparatus according to an embodiment of the second invention of the present application.
In the figure, 10 is an input terminal to which a signal reproduced by a rotary head (not shown) is supplied; 1) is a synchronization signal detection circuit that performs block synchronization and PIP synchronization of the reproduced signal and outputs a reproduced clock; 12 is a demodulation circuit that restores the original digital signal sequence from the reproduced signal; 13 is a timing control circuit that generates locking required for each block based on the clock obtained from the synchronization signal detection circuit 1); and 14 uses a parity code. 15 is a launch circuit that holds the ADR of each block for one block period; 16 is I
It is a register or memory that stores D code and DATA. 17°18.19 is the parity check circuit 14
The counter 20 and its output detection circuit 21 are used to detect two consecutive blocks of "no error" results in the parity check circuit 14. be. Further, 22 is a counter that increments for each block by using the output of the Ranoji circuit 15 as load data.
With gates 3, 24, 25°26, "no errors"
This is to detect that the two ADH blocks determined to be consecutive. Reference numeral 27 is a register for holding this result as a flag, and when the data is output from the output terminal 28 to a microcomputer or the like, the flag is also output from the terminal 29.

Next, the operation will be explained using the timing chart shown in FIG.

First, the playback signal input from the terminal 10 is transmitted to the synchronization detection circuit 1.
), and this synchronization detection circuit 1) detects a match with a predetermined synchronization pattern to reproduce the block synchronization clock (Fig. 2 (b)) indicating the block start point, and also performs bit synchronization. is taken and Figure 2 tc+
A reproduced clock corresponding to the symbol is generated as follows. In addition, the synchronous reproduction signal is converted to the original digital 1 in the 1g tone circuit 12.
8 is returned to the parity check circuit 14 as the data string shown in FIG. Latch circuit 15. The data is supplied to the data register 16. In the timing control circuit 13 that receives the recovered clock, rD, ADR, P within the block
A necessary lock corresponding to the position of each symbol such as R is generated and supplied to each block. Based on this clock,
The parity check circuit 14 calculates parity and
and check whether there are any data errors in ADR,
If there is no error, a "0" level is output during the PR symbol generation period, as shown in FIG. 2(d), and if there is an error, a "1" level is output. From the timing control circuit 13, a clock corresponding to the PR symbol position shown in FIG. If so, a signal is given so that the output of the counter 20 is reset to zero. That is, as shown in FIG. 2 (fl), the counter 20 continues to turn when there is no error in the data in the block, and is reset when there is an error.The output of this counter 20 is detected by the detection circuit 21, and the number of consecutive blocks without errors is determined. The probability that this will be missed twice in a row is extremely low, and in this case it can be said that the 4R reliability of the data is high.

On the other hand, the playback data is also input to the launch circuit 15, and the second
Since it is latched by the clock corresponding to the position of the ADH symbol in Figure 2 (A), its output represents the ADR of that block, as shown in Figure 2 fhl.However, this ADR may be an error. Therefore, the result of the parity check is used, and if there is no error in that block and the result of no error in consecutive blocks up to that block is 0, the gate 23 uses the clock shown in FIG. 2 (1). is supplied as a load clock to the counter 22, and the output of the latch circuit 15 is loaded as data.Since this counter 22 is configured to increment using, for example, a block synchronization clock, its output is as shown in FIG. ), this output and the output of the launch circuit 15 are connected to the gate 24.
The output is “0” if the two inputs match, and “1” if they do not match.
5, when the output of the detection circuit 21 is 1 and there is no error in the next block, that is, when no error is detected in two consecutive blocks, a signal as shown in FIG. 2 (kl) is output. Therefore, In the gate 26, when both of them are "0", that is, there are no errors in two consecutive blocks, and the second
“O” when the ADH of the block takes continuous values.
” and supplies it to the flag register 27.

The reproduced data is simultaneously supplied to the data register 16, and is captured into the register 16 at all times or as needed using the capture clock supplied from the timing control circuit 13. After being fetched, the data is taken out from the register 16 using, for example, a clock with a constant interval lower than the clock for fetching, and is supplied to an external microcomputer or the like from an output terminal 28 for processing. At the same time, a flag indicating the reliability of the captured data is output from the flag output terminal 29. For example, the flag register 27 is set to "1" in advance before capturing the playback data, and is reset to 10' under the above conditions, and is sent at the same time as the data is output. Accuracy can be expressed.

In this way, in this embodiment, instead of simply detecting ID code errors by a parity check, it is confirmed that no errors are detected in two consecutive blocks, and furthermore, the block address signals of the two blocks are continuous. This guarantees the reliability of the data if it is detected that
Has extremely high reliability.

The microcontroller that receives this data uses the information to display track numbers and perform high-speed searches, so the reliability of the data itself is particularly advantageous during high-speed searches with poor error conditions. This allows smooth access.

Note that in the above embodiment, a flag indicating the reliability of data is used, but for example, control may be performed such that data is output only when highly reliable data is obtained without transmitting the flag. , According to such an embodiment, a flag register is not required.

However, since data is not always available, it is not possible to receive data at regular intervals.

Next, an embodiment of the first invention of the present application will be described.

In this embodiment, only the "error-free" continuity of the blocks is checked in the embodiment shown in FIG. 1 above. That is, the continuity of two consecutive blocks of ADR is not particularly determined, and its configuration is similar to circuit 15.7 in FIG. 1 above. counter 2
2. This can be realized by omitting the gates 23 to 26, and inputs the "1" output, which is the detection result of "no error in two blocks" from the detection circuit 21, to the flag register 27, and registers the register 27 in the same manner as in the above embodiment. The content may be reset to "O".

Note that in each of the above embodiments, block continuity is detected for only two blocks, but it is clear that the reliability can be increased by further increasing the number of blocks.

〔Effect of the invention〕

As described above, according to the present invention, it is determined that errors in reproduced data are not detected over multiple blocks,
Furthermore, the continuity of the block is verified by detecting the block address to guarantee the reliability of the data, so even in conditions with a fairly low error rate, such as during high-speed searches, highly reliable data can be retrieved. This has the effect of providing a digital signal recording/reproducing device that can output the information to a microcomputer or the like, and is convenient for high-speed searching, displaying, etc.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a digital signal recording/reproducing device according to an embodiment of the second invention of the present application, FIG. 2 is a timing diagram showing its operation, and FIG. 3 is a data configuration diagram to which the present invention can be applied. FIG. 4 is a schematic diagram showing the head trajectory on the tape during high-speed search in this type of device. 14... Parity check circuit, 15... Block address latch circuit, 16... Data register, 20
... Counter, 21... Counter output detection circuit,
22...Counter, 27...Flag register. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (2)

[Claims] (1) In a digital signal recording and reproducing apparatus that records and reproduces data such that one block is composed of at least a synchronization signal, one or more information signals, and a code for detecting errors in the information signal, the reproduced Error detection means for detecting an error in the information signal; detection means for detecting that a state in which no error is detected continues for at least two blocks; and a reliability determination means for determining the reliability of the reproduced information signal according to the detection result. A digital signal recording and reproducing device characterized by comprising: means. (2) In a digital signal recording and reproducing apparatus that records and reproduces data such that one block is composed of at least a synchronization signal, one or more information signals, and a code for detecting errors in the information signal, the reproduced Error detection means for detecting an error in an information signal; detection means for detecting a state in which no error is detected for at least two consecutive blocks; A digital signal comprising: determining means for determining whether the signal is continuous; and reliability determining means for determining reliability of the reproduced information signal according to the detection result and the determination result. Recording and playback device.