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DE69916377D1 - Speicheranordnung und -verfahren - Google Patents

Speicheranordnung und -verfahren

Info

Publication number
DE69916377D1
DE69916377D1 DE69916377T DE69916377T DE69916377D1 DE 69916377 D1 DE69916377 D1 DE 69916377D1 DE 69916377 T DE69916377 T DE 69916377T DE 69916377 T DE69916377 T DE 69916377T DE 69916377 D1 DE69916377 D1 DE 69916377D1
Authority
DE
Germany
Prior art keywords
storage arrangement
arrangement
storage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69916377T
Other languages
English (en)
Other versions
DE69916377T2 (de
Inventor
Akihiro Okumura
Testujiro Kondo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Publication of DE69916377D1 publication Critical patent/DE69916377D1/de
Application granted granted Critical
Publication of DE69916377T2 publication Critical patent/DE69916377T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/04—Arrangements for selecting an address in a digital store using a sequential addressing device, e.g. shift register, counter
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/76—Television signal recording
    • H04N5/907—Television signal recording using static stores, e.g. storage tubes or semiconductor memories
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
    • H04N7/0117—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level involving conversion of the spatial resolution of the incoming video signal
    • H04N7/012—Conversion between an interlaced and a progressive signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/14—Picture signal circuitry for video frequency region
    • H04N5/21—Circuitry for suppressing or minimising disturbance, e.g. moiré or halo

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Computer Graphics (AREA)
  • Signal Processing (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Picture Signal Circuits (AREA)
  • Dram (AREA)
  • Television Signal Processing For Recording (AREA)
  • Image Input (AREA)
  • Controls And Circuits For Display Device (AREA)
DE69916377T 1998-02-16 1999-02-16 Speicheranordnung und -verfahren Expired - Lifetime DE69916377T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP3291398 1998-02-16
JP3291398 1998-02-16
PCT/JP1999/000662 WO1999041751A1 (en) 1998-02-16 1999-02-16 Memory device and method

Publications (2)

Publication Number Publication Date
DE69916377D1 true DE69916377D1 (de) 2004-05-19
DE69916377T2 DE69916377T2 (de) 2005-05-04

Family

ID=12372146

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69916377T Expired - Lifetime DE69916377T2 (de) 1998-02-16 1999-02-16 Speicheranordnung und -verfahren

Country Status (7)

Country Link
US (1) US6486885B2 (de)
EP (1) EP0976133B1 (de)
JP (2) JP4434322B2 (de)
KR (1) KR100602399B1 (de)
CN (1) CN1123891C (de)
DE (1) DE69916377T2 (de)
WO (1) WO1999041751A1 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4462823B2 (ja) * 2002-11-20 2010-05-12 ソニー株式会社 画像信号の処理装置および処理方法、それに使用される係数データの生成装置および生成方法、並びに各方法を実行するためのプログラム
US10102892B1 (en) * 2017-06-01 2018-10-16 Intel Corporation RAM-based shift register with embedded addressing

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2582423A1 (fr) * 1985-05-22 1986-11-28 Grenoble Inst Nal Polytechni Memoire tampon a interposer entre deux systemes synchrones a vitesses differentes
JPS6211977A (ja) * 1985-07-10 1987-01-20 Toshiba Corp 画像メモリ
JPH01114272A (ja) * 1987-10-28 1989-05-02 Daikin Ind Ltd フレームメモリアクセス方法
JPH0642196B2 (ja) * 1988-06-09 1994-06-01 株式会社東芝 倍密度走査用ラインメモリ
JPH0681276B2 (ja) * 1988-10-19 1994-10-12 松下電器産業株式会社 画像メモリ装置
JPH05289934A (ja) * 1992-04-15 1993-11-05 Sharp Corp 画像メモリー装置
JP3579461B2 (ja) 1993-10-15 2004-10-20 株式会社ルネサステクノロジ データ処理システム及びデータ処理装置
JP3253481B2 (ja) 1995-03-28 2002-02-04 シャープ株式会社 メモリインターフェイス回路
JP3630249B2 (ja) * 1995-04-07 2005-03-16 ソニー株式会社 映像信号変換装置
JP2956527B2 (ja) * 1995-04-28 1999-10-04 松下電器産業株式会社 画像メモリ機能付き映像装置
JPH09114970A (ja) * 1995-10-17 1997-05-02 Fuji Photo Film Co Ltd 画像データ記憶装置
US5710604A (en) * 1996-02-09 1998-01-20 Texas Instruments Incorporated Video memory device for color-sequential-type displays
JP3322613B2 (ja) 1997-08-27 2002-09-09 シャープ株式会社 映像信号変換器

Also Published As

Publication number Publication date
KR100602399B1 (ko) 2006-07-20
JP5151786B2 (ja) 2013-02-27
KR20010006367A (ko) 2001-01-26
US20020054045A1 (en) 2002-05-09
DE69916377T2 (de) 2005-05-04
EP0976133B1 (de) 2004-04-14
CN1123891C (zh) 2003-10-08
WO1999041751A1 (en) 1999-08-19
JP2001520782A (ja) 2001-10-30
JP2008262707A (ja) 2008-10-30
US6486885B2 (en) 2002-11-26
JP4434322B2 (ja) 2010-03-17
CN1256784A (zh) 2000-06-14
EP0976133A1 (de) 2000-02-02

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Legal Events

Date Code Title Description
8332 No legal effect for de
8370 Indication related to discontinuation of the patent is to be deleted
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)