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DE69830550D1 - Arbitrierungssystem - Google Patents

Arbitrierungssystem

Info

Publication number
DE69830550D1
DE69830550D1 DE69830550T DE69830550T DE69830550D1 DE 69830550 D1 DE69830550 D1 DE 69830550D1 DE 69830550 T DE69830550 T DE 69830550T DE 69830550 T DE69830550 T DE 69830550T DE 69830550 D1 DE69830550 D1 DE 69830550D1
Authority
DE
Germany
Prior art keywords
arbitration system
arbitration
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69830550T
Other languages
English (en)
Inventor
Andrew Michael Jones
Peter Malcolm Barnes
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Ltd Great Britain
STMicroelectronics lnc USA
Original Assignee
STMicroelectronics Ltd Great Britain
SGS Thomson Microelectronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics Ltd Great Britain, SGS Thomson Microelectronics Inc filed Critical STMicroelectronics Ltd Great Britain
Application granted granted Critical
Publication of DE69830550D1 publication Critical patent/DE69830550D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0215—Addressing or allocation; Relocation with look ahead addressing means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1626—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests
    • G06F13/1631—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests through address comparison

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
DE69830550T 1997-09-08 1998-09-02 Arbitrierungssystem Expired - Lifetime DE69830550D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GBGB9719047.4A GB9719047D0 (en) 1997-09-08 1997-09-08 Arbitration system

Publications (1)

Publication Number Publication Date
DE69830550D1 true DE69830550D1 (de) 2005-07-21

Family

ID=10818732

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69830550T Expired - Lifetime DE69830550D1 (de) 1997-09-08 1998-09-02 Arbitrierungssystem

Country Status (4)

Country Link
US (1) US6301642B1 (de)
EP (1) EP0901080B1 (de)
DE (1) DE69830550D1 (de)
GB (1) GB9719047D0 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6662251B2 (en) * 2001-03-26 2003-12-09 International Business Machines Corporation Selective targeting of transactions to devices on a shared bus
JP3606852B2 (ja) * 2001-08-13 2005-01-05 沖電気工業株式会社 バス制御システム
KR100455396B1 (ko) * 2002-10-14 2004-11-06 삼성전자주식회사 마스터 블록들의 우선 순위를 결정하는 파라미터 발생회로 및 파라미터 발생 방법.
US8539096B2 (en) * 2003-09-26 2013-09-17 Lsi Corporation Systems and methods for configuring ports of an SAS domain
EP1692617B1 (de) * 2003-12-09 2009-04-08 THOMSON Licensing Speichersteuerung
JP4055903B2 (ja) * 2003-12-26 2008-03-05 シャープ株式会社 バス通信システム
US7975086B1 (en) * 2004-03-08 2011-07-05 Pmc-Sierra Us, Inc. Apparatus for real-time arbitration between masters and requestors and method for operating the same
US7467247B2 (en) * 2005-10-31 2008-12-16 Hewlett-Packard Development Company, L.P. Timeouts on accessing a shared resource
US7426621B2 (en) * 2005-12-09 2008-09-16 Advanced Micro Devices, Inc. Memory access request arbitration
US20080059672A1 (en) * 2006-08-30 2008-03-06 Irish John D Methods and Apparatus for Scheduling Prioritized Commands on a Bus
US8904108B2 (en) 2012-10-31 2014-12-02 Lsi Corporation Methods and structure establishing nested Redundant Array of Independent Disks volumes with an expander
US9135198B2 (en) 2012-10-31 2015-09-15 Avago Technologies General Ip (Singapore) Pte Ltd Methods and structure for serial attached SCSI expanders that self-configure by setting routing attributes of their ports based on SMP requests
US8904119B2 (en) 2012-10-31 2014-12-02 Lsi Corporation Method and structures for performing a migration of a logical volume with a serial attached SCSI expander
US8756345B2 (en) 2012-10-31 2014-06-17 Lsi Corporation Methods and structure for managing protection information with a serial attached SCSI expander
US8782292B2 (en) 2012-10-31 2014-07-15 Lsi Corporation Methods and structure for performing a rebuild of a logical volume with a serial attached SCSI expander
US11144457B2 (en) * 2018-02-22 2021-10-12 Netspeed Systems, Inc. Enhanced page locality in network-on-chip (NoC) architectures

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4623986A (en) * 1984-02-23 1986-11-18 Texas Instruments Incorporated Memory access controller having cycle number register for storing the number of column address cycles in a multiple column address/single row address memory access cycle
US5193194A (en) * 1988-10-18 1993-03-09 Motorola, Inc. Concurrent arbitration system and method for bus control
US5655102A (en) * 1993-09-29 1997-08-05 Silicon Graphics, Inc. System and method for piggybacking of read responses on a shared memory multiprocessor bus
TW388982B (en) * 1995-03-31 2000-05-01 Samsung Electronics Co Ltd Memory controller which executes read and write commands out of order
US5987574A (en) * 1997-04-30 1999-11-16 Sony Corporation Bank arbitration for SDRAM memory control
US6049855A (en) * 1997-07-02 2000-04-11 Micron Electronics, Inc. Segmented memory system employing different interleaving scheme for each different memory segment
US5983325A (en) * 1997-12-09 1999-11-09 Advanced Micro Devices, Inc. Dataless touch to open a memory page
US6052134A (en) * 1997-12-22 2000-04-18 Compaq Computer Corp. Memory controller and method for dynamic page management
US6052756A (en) * 1998-01-23 2000-04-18 Oki Electric Industry Co., Ltd. Memory page management

Also Published As

Publication number Publication date
GB9719047D0 (en) 1997-11-12
EP0901080A1 (de) 1999-03-10
US6301642B1 (en) 2001-10-09
EP0901080B1 (de) 2005-06-15

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Legal Events

Date Code Title Description
8332 No legal effect for de