DE69810270T2 - DIFFERENTIAL FLASH STORAGE CELL AND OPERATING METHOD THEREFOR - Google Patents

Description

Technical field of the invention

The present invention relates generally to the field of electronic devices and, more particularly, to a differential flash memory cell and a method for programming this memory cell.

Background of the invention

Typically, computer systems store their data on a magnetic medium such as a hard disk drive. The hard disk drive is an electromechanical component of the computer system that holds the polarity of a magnetic material that can be rewritten quickly and indefinitely. A typical hard disk drive contains at least two moving parts that respond to control signals generated by a processor of the computer system. Traditionally, the hard disk drive includes a disk made of an aluminum substrate that is rotatably mounted on a base. A magnetic material is applied to the surface of the substrate. A pivoting actuator arm moves a ceramic transducer across the surface of the disk to read data from and write data to the disk. The mechanical parts are more delicate and less reliable than the other semiconductor components of the computer system. However, magnetic hard disk systems dominate the storage media space for computers and similar systems because of the low cost and high storage density of current magnetic hard disk systems compared to traditional semiconductor alternatives.

Semiconductor memories store data in storage locations called "cells." Conventional designs allow only a single bit of data to be stored in a cell at a time. Typically, the cell includes an access transistor and a storage element such as a capacitor or floating gate that stores data based on the electrical charge on the storage element. The electrical charge represents either a binary "1" or a binary "0" in conventional applications, so the conventional design requires a transistor for each bit of data. The storage density of semiconductor memories is limited by the maximum possible packing density of transistors on a semiconductor substrate. But even though transistors are packed more and more densely in each new generation of technology, this density is still not comparable to the storage density of a magnetic medium.

There have been recent attempts to increase the storage density of flash memory cells by creating memory cells that can store more than one bit of data, called "multi-state" flash memory cells. In a conventional flash memory, charge is stored on the floating gate of a field-effect transistor in response to a signal applied to a control gate. The charge on the floating gate represents either a binary "1" or a binary "0" based on the effect of the charge on the current through the transistor. When there is charge on the floating gate, the drain current is reduced. Initially, there is no charge on the floating gate, representing a binary "1." When a binary "0" is stored, a voltage on the control gate sufficient to inject hot electrons forces electrons into the floating gate, reducing the drain current of the transistor. Therefore, by detecting the drain current of the transistor, the value of the data bit stored in the flash memory cell can be determined.

To increase the number of states that can be stored, attempts have been made to make adjustments to the threshold voltage of the transistor. However, this technique can only store two to four bits of data in a cell at most due to the variations in the threshold voltage of the individual transistors in an array of memory cells. Otherwise, complex programming techniques are required to adjust the threshold voltage of the transistors for each read and write operation. Current flash memory devices with multiple storage states therefore represent little improvement over conventional semiconductor memories due to the difficulty of reading the state stored on the floating gate.

For these and other reasons hereinafter which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need for a semiconductor memory in which multi-bit data can be effectively stored and retrieved in each memory cell.

From EP-A-0139185 a flash memory cell is known with two transistors, each having a floating gate, wherein a data bit is stored by charging one or the other of the floating gates and the data is read out by detecting the voltage difference between the floating gates, thereby determining which of the gates is charged.

From US-A-5418743 memory cells are known in which a memory transistor is programmed by adding charge to the floating gate until the drain current assumes one of a number of possible values corresponding to data values. Reference transistors are provided to set the reference drain currents corresponding to the possible values of the data.

The aspects of the present invention are set out in the appended claims.

A flash memory cell and a method for programming this memory cell are described which enable the storage of a number of bits in each cell.

In particular, an exemplary embodiment of the present invention includes a flash memory cell having first and second transistors. The first transistor includes a control gate connected to a word line, a drain connected to a data line, and a floating gate. The second transistor similarly includes a control gate connected to the word line, a drain connected to a second data line, and a second floating gate. The first floating gate stores the state of the second transistor prior to programming the flash memory cell. The second floating gate stores the programmed state of the second transistor. The difference between the states of the first and second transistors represents the value of the data stored in the flash memory cell.

Another embodiment of the present invention includes a method of storing multi-bit data in a flash memory cell. In this method, the memory and reference transistors of the flash memory cell are first equalized. That is, the transistors are forced to assume substantially the same conductivity state. Then, charges are stored on the floating gate of the memory transistor such that the drain current of the memory transistor changes in measurable steps. The number of step changes in the drain current of the memory transistor corresponds to the value of the multi-bit data stored in the flash memory cell.

In another embodiment of the present invention, a flash memory cell includes a reference transistor having a first floating gate and a storage transistor having a second floating gate. The reference and storage transistors are connected to a common word line. The reference and storage transistors are also connected to different data lines. The flash memory cell generates a differential output signal on the data lines based on the charges stored on the first and second floating gates. The differential output signal represents the multi-bit data stored in the flash memory cell.

In another embodiment of the present invention, a flash memory cell includes a reference transistor having a first floating gate and a storage transistor having a second floating gate. The first transistor stores the state of the second transistor before programming the flash memory cell. The difference between the state of the first transistor and the state of the second transistor after programming therefore represents the value of the data stored in the flash memory cell.

In another embodiment of the present invention, a memory device includes an array of flash memory cells. Each cell includes a reference transistor having a first floating gate and a storage transistor having a second floating gate. The memory device further includes an addressing circuit coupled to the array for accessing a cell of the array. Finally, the memory device includes a detection circuit coupled to the array for receiving signals from the reference and storage transistors of the cell being accessed to determine the multi-bit data stored in the memory cell based on the difference in the drain current of the reference and storage transistors.

Short description of the drawings

Fig. 1 is a schematic representation of an embodiment of a flash memory cell according to the teachings of the present invention;

2A and 2B are schematic illustrations of charging devices for the flash memory cell of FIG. 1 in accordance with an embodiment of the present invention;

Fig. 3 is a cross-sectional view of a floating gate transistor of a number of gate elements for the flash memory cell of Fig. 1;

Fig. 4 is a graphical representation of the relationship between the rate of hot electron injection and the voltage applied to a transistor with a floating gate;

Fig. 5 is a schematic diagram illustrating aspects of the operation of the flash memory cell of Fig. 1; and

Fig. 6 is a block diagram of a flash memory device according to the teachings of the present invention.

The following detailed description of preferred embodiments is made with reference to the accompanying drawings which form a part hereof, and in which is shown by way of example specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that logical, mechanical and electrical changes may be made without departing from the scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense.

For the purposes of this description, prepositions such as "on," "side" (as in "sidewall"), "higher," "lower," "above," and "below" are defined with respect to the conventional flat work surface located on top of the chip or wafer, regardless of how the chip is actually held.

Figure 1 is a schematic diagram of an exemplary embodiment of a flash memory cell, generally designated 10, constructed in accordance with the teachings of the present invention. The memory cell 10 includes first and second field effect transistors 12 and 14. The transistors 12 and 14 include floating gates 16 and 18. The term "floating gate" indicates that the gates 16 and 18 are electrically isolated in an insulating material, such as a gate oxide. Cell 10 stores data based on the difference in charges on floating gates 16 and 18. Cell 10 is essentially non-volatile (i.e., when power is removed from cell 10, data stored on floating gates 16 and 18 is not lost) because of the low refresh requirement to maintain the charge on floating gates 16 and 18. Transistors 12 and 14 include control gates 20 and 22. Control gates 20 and 22 are connected together and coupled to a word line 36.

In one embodiment, floating gates 16 and 18 are constructed from a number of insulating crystals of a conductive material, as described below with reference to FIG. 3. Instead of this nanocrystal structure, other structures may be used for floating gates 16 and 18, as long as they allow the charges stored on the floating gates to cause measurable changes in the drain current of the transistors, as described below. This includes polycrystalline silicon gates, such as those normally used in flash memories. Transistors 12 and 14 also include source terminals 24 and 26 and drain terminals 28 and 30. Source terminals 24 and 26 are connected to ground and the drain terminals 28 and 30 are connected to data lines 32 and 34. The data lines 32 and 34 are connected to a load such as the charging circuit 37 of Fig. 2A or the charging circuit 46 of Fig. 2B. Each of these charging circuits will be described in more detail below with respect to their function in the operation of the flash memory cell 10.

In operation, the flash memory cell 10 stores data using the floating gates 16 and 18 of the transistors 12 and 14. To "program" or "write" data into the cell 10, the transistors 12 and 14 are first "equalized." The term "equalized" means that the transistors are adjusted to have substantially the same conduction state or drain current. The transistors 12 and 14 are equalized by adjusting the charge on the floating gates 16 and 18, as described below. After the transistors 12 and 14 are equalized, the cell 10 can be programmed by storing charge on the floating gate 18, for example, by injecting hot electrons. In this way, transistor 12 stores the initial state of transistor 14, or its state before programming (through the equalization operation), and the difference between the state of transistor 12 and the state of programmed transistor 14 forms the value of the data stored in cell 10.

To balance transistors 12 and 14, data lines 32 and 34 are connected to a power source through small resistors using, for example, charging circuit 37 of Fig. 2A. Charging circuit 37 includes first and second resistors 38 and 40 and a voltage supply VDD. Resistor 38 is connected between VDD and data line 32. Similarly, resistor 40 is connected between data line 34 and VDD. In this configuration, the voltages at drains 28 and 30 are substantially the same. Due to small variations in the characteristics of transistors 12 and 14, e.g., threshold voltage, one transistor may have a higher drain current than the other transistor. As shown in Fig. 4, the rate of hot electron injection in a floating gate transistor is a function of the gate-source overvoltage above the threshold voltage (VGS - VT) of the transistor as shown by curve 42 of Fig. 4. Curve 42 assumes a fixed drain-source voltage. In region 44, curve 42 is substantially linear with a positive slope when a logarithmic scale is used to record the rate of hot electron injection. When transistors 12 and 14 are biased in region 44, the transistor with the smaller threshold voltage exhibits a greater rate the injection of hot electrons. As a result, the threshold voltage of this transistor increases more rapidly until the conductivities of the two transistors are substantially equal. Transistors 12 and 14 may be biased in region 44 by enhancement mode devices with a positive threshold voltage that is a fraction of the power supply voltage. The extent of equalization may be determined by connecting data lines 32 and 34 to a differential sense amplifier (not shown) and monitoring the small voltage drop across resistors 38 and 40. The equalization operation may be terminated when the conductivity of transistors 12 and 14 reaches an acceptable equalization level.

When transistors 12 and 14 are balanced, cell 10 can be programmed by storing charge on the floating gate 18 of transistor 14. This operation is shown graphically in Figure 5. The voltage labeled Vx is applied to data line 34 and a smaller voltage Vx/1.5 is applied to data line 32. This causes hot electron injection into transistor 14. Only a negligible injection of hot electrons occurs at transistor 12 because the gate voltage is higher than the drain voltage, so that transistor 12 is in the linear region. The characteristics of transistor 12 therefore do not change substantially while charges are built up on the floating gate 18 of transistor 14, reducing its conductivity state. The change in conductivity of transistor 14 can be monitored during programming to store a value representative of a number of data bits.

As described below, cell 10 uses a floating gate that causes step changes in drain current as charges accumulate on floating gate 18. The step changes in drain current of transistor 14 are monitored (e.g., counted) during programming. The number of step changes in drain current can be converted to a binary representation, e.g., a number of bits. For example, the binary number 1001 can be programmed into cell 10 by storing enough charge on floating gate 18 to cause nine step changes in drain current of transistor 14.

It should be noted that the programming step may include the step of storing no additional charge on the floating gate 18 so that the charge difference between the floating gates 16 and 18 is substantially zero.

During readout, data is read from cell 10 by amplifying the difference in charges stored on floating gates 16 and 18. For example, charging circuit 46 of Figure 2B is connected to data lines 32 and 34 to sense and amplify any imbalance in charges on floating gates 16 and 18. Charging circuit 46 includes first and second p-channel field effect transistors connected together in a differential configuration. That is, the gate of transistor 48 is connected to the gate of transistor 50. The source of transistor 48 and the source of transistor 50 are connected to power supply VDD. The drain of transistor 48 is connected to the gate of transistor 48 and to data line 32. Finally, the drain of transistor 50 is connected to data line 34. The differential design of charging circuit 46 amplifies the differences in drain current of transistors 12 and 14 caused by the difference in charges stored on floating gates 16 and 18. Since charging circuit 46 can have a very large gain with a very small offset, even small charge differences can be sensed, including charge differences as small as the charge of a single electron. Thus, by storing a charge on floating gate 18 of cell 10, cell 10 can be programmed with a large number of different charge states corresponding to step changes in drain current. Thus, by counting the number of steps in the difference in drain current between transistors 12 and 14, a differential signal is generated that corresponds to the value for the data stored in cell 10. This signal can be converted into a binary number based on the number of step changes in the drain current.

The floating gates 16 and 18 are constructed to allow detection of step changes in drain current when storing charge. For example, the floating gates 16 and 18 may be made from a layer of polysilicon material deposited in a gate oxide using 0.3 micron technology and a gate oxide thickness of 100 Å (10⁻⁸ m). In this construction, the floating gates 16 and 18 have a capacitance on the order of 0.3 fF. A single electron changes the potential of such a floating gate by about 0.5 mV. Since the charging circuit 46 has a gain of at least 10, a difference of a single electron between the floating gates 16 and 18, based on the modified drain current of the transistor 18, results in an output of the charging circuit 46 of about 5 mV. This voltage level is easily detectable using conventional circuits. The effect of a difference of a single Electrons in the stored charge are therefore measurable, and a value representing multi-bit data can be stored in cell 10 by counting the number of measurable steps of change in the drain current of transistor 14 compared to the drain current of transistor 12.

In an alternative embodiment, floating gates 16 and 18 may be of nanocrystalline construction. Figure 3 shows a cross-section through a transistor memory cell 10. The transistor of Figure 3 is described here with reference to transistor 14 of cell 10. However, it will be understood that transistor 12 may be constructed in the same manner. Floating gate 18 comprises crystals of, for example, silicon, silicon carbide or other suitable semiconductor material implanted into oxide layer 52 at low density using conventional process techniques. Due to the low density of the implantation, the semiconductor material forms grains which form crystals 54. Crystals 54 are referred to as "nanograins" or "nanocrystals" because of their typical size with a surface area in the range of 10-13 cm2.

The crystals 54 of the floating gate 18 are formed at a distance of about 50 to 100 Å (5 x 10-9 to 10-8 m) from the working surface 56 of the semiconductor layer 58. Advantageously, this distance, in conjunction with the size of the crystals 54, allows each crystal 54 to capture at most one electron, which causes a step change in the drain current of the transistor 14. This step change in the drain current is measurable and therefore allows multi-bit data to be stored in a single transistor 14.

The stepwise change in the current of the transistor 14 can be seen from the following analysis. The capacitance between the crystal 54 and the semiconductor layer 56 is given by the following equation:

C = (εrε₀ · area)/d + correction for edge effects,

where C is the capacitance, "area" is the surface area of the crystal 54, and d is the distance between the crystal 54 and the surface 56 of the semiconductor layer 58, and the correction term takes into account that the crystal 54 has a smaller surface area than the semiconductor layer 56 and therefore the electric field varies around the periphery of the crystal 54. If d is 100 angstroms (10-8 m) and the crystal 54 has a surface area in the range of 10-13 cm2, the capacitance of the crystal 54 is about 1.0 x 10-19 farads. The charge of an electron is 1.6 x 10-19 coulombs and results in a change in the potential of the crystal 54 of about 1.6 volts. The crystal 54 repels electrons when it is in contact with the writing operation has captured a single electron. Each crystal 54 is therefore limited to a certain change in charge state by capturing only a single electron. The change in charge state in turn causes a certain step change in the drain current of transistor 14. Transistor 14 amplifies the change in drain current, making the change easily detectable.

The floating gate 18 of the memory cell 10 can be programmed to store the value for a number of bits at a time. This is done by counting the number of step changes in the drain current during the write operation. The number of step changes in the drain current is related to the value of the bits stored. In this way, a variety of different states can be stored that are related to the storage of a number of bits on a single floating gate 18.

It should be noted that a programmed cell is erased by driving the voltage on word line 36 to a large negative value so that the charge on floating gate 18 is discharged via conventional tunneling techniques.

Figure 6 is a block diagram of one embodiment of a memory device, generally designated 100, constructed in accordance with the teachings of the present invention. The memory device 100 includes an array 102 of flash memory cells. The array 102 stores data using a number of memory cells of the type shown and described above with reference to Figures 1-5.

Each cell in the array 102 can be accessed according to address signals from an electronic system 104. The address lines 109 are connected to a word line decoder 106 and a data line decoder 110. The word line decoder 106 and the data line decoder 110 are connected to the array 102. Connected to the data line decoder 110 is a detection circuit 114 which represents the output of the flash memory device 100.

In operation, the flash memory device 100 writes, reads, and erases multi-bit data to or from each memory location of the array 102.

In write mode, flash memory device 100 is supplied with an address on address line 109. Word line decoder 106 decodes the associated word line for a particular cell and activates the word line. Data line decoder 110 similarly decodes the data line for the desired cell. The selected cell in array 102 is then brought to a particular state and stores a number of bits in the cell as described above.

Similarly, in read mode, the address of the selected cell is decoded and a specific cell of array 102 is accessed. Data line decoder 110 connects the selected cell to detection circuit 114, which outputs a signal having a number of bits based on the detected difference in the drain currents of the two transistors in that cell.

Conclusion

Certain embodiments have been shown and described. However, those skilled in the art will recognize that these embodiments may be replaced by any arrangement that achieves the same purpose. This application is intended to cover all adaptations and variations of the present invention. For example, the data line decoders are not required if a sense amplifier is provided for each data line. Also, the crystals 30 may be formed from other materials capable of capturing an electron from a hot electron injection. Other floating gate configurations may also be used as long as measurable steps in drain current can be measured when storing charges on the floating gates.

Claims (13)

1. A method for storing multi-bit data in a flash memory cell (10) of an array (102) of flash memory cells, each memory cell having a memory transistor (14) with a floating gate (18), comprising the following steps: storing charge on the floating gate of the memory transistor to change its drain current by a measurable amount, the amount of change in the drain current having a value corresponding to one of a number of possible values for the multi-bit data to be stored in the flash memory cell; characterized in that the method comprises, prior to the storing step, an equalizing step by which the conductivity state of the storage transistor and that of a corresponding reference transistor (12) of the memory cell are made substantially equal, so that the conductivity state of the reference transistor after the storing step continues to reflect the conductivity state of the storage transistor prior to the storing step. 2. The method of claim 1, wherein the balancing step includes a step of applying a load (37, 46) to a first and a second data line (32, 34) of the flash memory cell to change the conductivity state of the memory or reference transistor by an injection of hot electrons. 3. A method according to any preceding claim, wherein the step of storing a charge on the floating gate of the memory transistor comprises the following steps: Applying a first voltage to a data line (34) of the memory transistor; and Applying a second voltage, which is less than the first voltage, to a data line (32) of the reference transistor. 4. A method according to any preceding claim, wherein the storing step comprises monitoring stepwise changes in the drain current of the memory transistor, counting the number of stepwise changes and terminating the storing step when the number of stepwise changes is equal to a numerical value of the data to be stored. 5. Flash memory device (100) for storing multi-bit data in a flash memory cell (10) of an array (102) of flash memory cells of the device, wherein each memory cell has a memory transistor (14) with a floating gate (18), with storage means for storing charge on the floating gate of the memory transistor to change the drain current thereof by a measurable amount, the amount of change in the drain current having a value corresponding to one of a number of possible values for the multi-bit data to be stored in the flash memory cell; characterized by equalizing means operable upstream of the storage means for substantially equalizing the conductivity state of the storage transistor and that of a corresponding reference transistor (12) of the memory cell such that the conductivity state of the reference transistor after storing charge on the floating gate of the storage transistor continues to reflect the conductivity state of the storage transistor prior to storing charge. 6. The device of claim 5, wherein the equalizing means comprises a charging circuit (37, 46) for connection to a first and a second data line (32, 34) of the flash memory cell in order to change the conductivity state of the memory or reference transistor by an injection of hot electrons. 7. Device according to claim 5 or 6, wherein the storage device comprises means for applying a first voltage to a data line (34) of the memory transistor; and means for applying a second voltage, which is less than the first voltage, to a data line (32) of the reference transistor. 8. Device according to one of claims 5 to 7, wherein the storage device has means for monitoring step-by-step changes in the drain current of the memory transistor, a device for counting the number of step changes, and means for terminating the storage of load when the number of incremental changes is equal to a numerical value of the data to be stored. 9. Device according to one of claims 5 to 8, with an addressing circuit (106, 110) connected to the array for accessing a cell of the array; and a detection circuit (114) coupled to the array for receiving signals from the reference and storage transistors of a memory cell being accessed to determine multi-bit data stored in the memory cell based on the difference in drain current of the reference and storage transistors. 10. Flash memory cell (10) for use in a device according to claim 5, with a reference transistor (12) having a control gate (20) connected to a word line (36), a drain (28) connected to a first data line (32) and a first floating gate (16); a memory transistor (14) having a control gate (22) connected to the word line, a drain (30) connected to a second data line, and a second floating gate (18); wherein the first floating gate stores a state of the memory transistor before programming of the flash memory cell and the second floating gate stores a programmed state of the memory transistor; wherein the memory cell further comprises a charging circuit (37, 46) connectable to the first and second data lines to equalize the states of the reference and storage transistors prior to programming the flash memory cell, and wherein the common connection of the reference and storage transistors to the word line and the various first and second data lines provides a differential output signal of the flash memory cell on the data lines due to charge stored on the first and second floating gates, and the differential output signal represents multi-bit data stored in the flash memory cell. 11. A flash memory cell according to claim 10, wherein the floating gates each include a number of silicon crystals (18). 12. The flash memory cell of claim 10, wherein the first and second floating gates comprise silicon crystals disposed in the gate oxides of the reference and storage transistors. 13. The flash memory cell of claim 10, wherein the first and second floating gates include layers of conductive material formed in the gate oxides of the reference and storage transistors to cause measurable step-by-step changes in drain current in the transistors when charge is applied to the floating gates.